Obviousness

Analysis of Obviousness for U.S. Patent No. 8,400,835

Date of Analysis: April 26, 2026

Patent under Review: U.S. Patent No. 8,400,835 (hereinafter "'835 patent")

Statutory Basis for Analysis: 35 U.S.C. § 103 (Conditions for patentability; non-obvious subject matter)

Introduction

This analysis examines whether the claims of the '835 patent would have been obvious to a person having ordinary skill in the art (PHOSITA) of non-volatile semiconductor memory design at the time the invention was made, considering the prior art cited in the patent's prosecution history. An invention is considered obvious if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a PHOSITA.

The core of the '835 patent's claimed invention lies in a non-volatile semiconductor memory architecture designed to reduce variations in write speed when simultaneously writing to multiple memory cells. This is achieved by providing M data lines connected to the bit lines, with each data line having N switches controlled by a dedicated switch control circuit. These circuits can individually change the levels or application periods of the drain voltages for each memory cell being written to.

Prior Art References

The following prior art references, cited during the prosecution of the '835 patent, are considered in this analysis:

• US 2003/0063494 A1 ("'494 publication"): Discloses a semiconductor memory device that aims to reduce fluctuations in writing speed by adjusting the bit line voltage based on the write address. This addresses the issue of voltage drops along the bit line.
• JPH0562484A: Describes a nonvolatile semiconductor memory device with a mechanism to prevent erroneous writing by controlling the bit line potential.
• JPH06150670A: Relates to a semiconductor memory device with improved write and erase characteristics.
• US 2003/0218897 A1 ("'897 publication"): Discloses a nonvolatile semiconductor memory device capable of uniformly inputting/outputting data, addressing variations in memory cell characteristics.
• JP2004220728A: Describes a non-volatile multi-level semiconductor memory and a method for writing data to it.
• US 2004/0174745 A1 ("'745 publication"): Details a drain pump for a flash memory device.
• US 8,085,609 B2 ("'609 patent"): Pertains to a nonvolatile semiconductor memory and a method for detecting leakage defects.

Obviousness Combination Analysis

A strong argument for the obviousness of the claims of the '835 patent can be constructed by combining the teachings of the '494 publication with the general knowledge of a PHOSITA regarding circuit design and the motivation to improve performance and reliability in memory devices.

1. Combination of '494 publication and Known Circuit Elements/Techniques

• '494 publication's Contribution: The '494 publication explicitly recognizes the problem of write speed variation due to voltage drops on bit lines, a problem central to the '835 patent. It proposes a solution: adjusting the bit line voltage based on the address of the memory cell being written to. This establishes the motivation to control drain voltage on a more granular level to compensate for physical variations within the memory array.

• Motivation to Combine with Individual Switching Elements: A PHOSITA, faced with the problem of write speed variations among simultaneously written cells (as acknowledged in the '835 patent's background), would be motivated to find a mechanism for individual cell control. The '494 publication teaches adjusting voltage based on address, but for simultaneous writes to multiple cells connected to different data lines, a more localized control would be a natural and logical next step.

  The implementation of N switches per data line, as claimed in the '835 patent, represents a well-understood engineering choice for achieving variable voltage or timing control. A PHOSITA would be aware that using multiple transistors in parallel (as shown in Figure 2 of the '835 patent) allows for adjustable impedance and thus variable voltage levels. Similarly, using transistors of different types (P-type and N-type, as in Figure 4) or employing delay circuits (Figure 6) are standard techniques for controlling voltage levels and pulse widths (application periods).

  Therefore, a PHOSITA, starting with the problem of write-speed variation and the solution framework provided by the '494 publication (adjusting drain voltage), would find it obvious to implement this adjustment on a per-data-line basis using well-known switching and control circuit designs. The motivation would be to achieve finer control over the write process for simultaneously programmed cells, thereby improving uniformity and reducing overall write time.

2. Additional Supporting Rationale from Other References

• The '897 publication further reinforces the motivation for individualized control by addressing variations in memory cell characteristics. It suggests that uniform data input/output is a desirable goal. A PHOSITA would understand that to achieve uniformity, especially when dealing with multi-bit-per-cell memories (as mentioned in the '835 patent), it is necessary to compensate for differing cell states. This provides a strong reason to implement the per-cell (or per-data-line) control of write parameters as claimed in the '835 patent. Claim 7 of the '835 patent, which specifically addresses multi-bit cells where the state of one bit affects the writing of another, is a direct application of this principle.

Conclusion on Obviousness

The claims of US Patent 8,400,835 appear to be obvious under 35 U.S.C. § 103. The primary motivation to address write speed variations in non-volatile memories was well-established in the prior art, as exemplified by the '494 publication. This reference teaches the concept of adjusting drain voltage to compensate for such variations.

A person of ordinary skill in the art, seeking to apply this concept to the simultaneous writing of multiple cells, would have been motivated to implement a per-data-line control mechanism. The specific implementation using M switch control circuits to manage M x N switches is a predictable design choice utilizing standard electronic components and circuit design principles to achieve the desired granular control over voltage levels and application periods. The motivation to combine these known elements stems from the desire to improve the performance, reliability, and efficiency of the memory writing process, a constant driver of innovation in the semiconductor industry. The further teachings of the '897 publication regarding the need to handle variations in cell characteristics would have further guided a PHOSITA toward such a solution.