Prior art — US Patent 8368201

To identify the most relevant prior art for US patent 8368201, I will examine the patent citations listed within the patent itself. Since the patent states its priority date is January 31, 2002, I will consider prior art references that have a publication or filing date before this date, as per 35 U.S.C. § 102 (pre-AIA, given the priority date).

Here's an analysis of the cited prior art:

Most Relevant Prior Art for US Patent 8368201

The following patents are cited as prior art in US patent 8368201:

US4246595A: Electronics circuit device and method of making the same
- Full Citation: US4246595A
- Publication Date: January 20, 1981
- Filing Date: March 8, 1977
- Brief Description: This patent describes an electronic circuit device and its manufacturing method, where circuit components are embedded within an insulating substrate. The components are placed in recesses or holes, and then the substrate is formed around them.
- Potential Anticipation (35 U.S.C. § 102): US4246595A could potentially anticipate aspects of Claim 1, specifically the concept of "at least one component within the baseboard" and a "hardened insulating polymer layer" formed around it, especially if the "baseboard" is interpreted broadly to encompass an insulating substrate into which components are embedded. The patent's focus on embedding components in an insulating substrate and forming the circuit around them aligns with the general concept of the base and component integration in US8368201.
US4783695A: Multichip integrated circuit packaging configuration and method
- Full Citation: US4783695A
- Publication Date: November 8, 1988
- Filing Date: September 26, 1986
- Brief Description: This patent details a multichip integrated circuit packaging configuration and a method for its fabrication. It involves placing multiple unpackaged semiconductor dice into cavities in a substrate and then encapsulating them.
- Potential Anticipation (35 U.S.C. § 102): This reference is relevant to the "at least one component within the baseboard" feature of Claim 1, particularly if "component" is understood as an unpackaged semiconductor die. The concept of placing components into cavities and encapsulating them within a base could potentially anticipate the embedding aspect.
US4894115A: Laser beam scanning method for forming via holes in polymer materials
- Full Citation: US4894115A
- Publication Date: January 16, 1990
- Filing Date: February 14, 1989
- Brief Description: This patent describes a method for forming via holes in polymer materials using a laser beam. While it doesn't directly address component embedding, it pertains to a manufacturing technique relevant to circuit boards.
- Potential Anticipation (35 U.S.C. § 102): This reference primarily relates to manufacturing processes (e.g., how holes could be made), rather than the structural elements of Claim 1. Therefore, it is less likely to anticipate Claim 1 directly but is important for understanding the technical landscape of forming holes in polymer layers.
US5102829A: Plastic pin grid array package
- Full Citation: US5102829A
- Publication Date: April 7, 1992
- Filing Date: July 22, 1991
- Brief Description: This patent discloses a plastic pin grid array package for integrated circuits, where the integrated circuit die is encapsulated within a plastic body.
- Potential Anticipation (35 U.S.C. § 102): Similar to US4783695A, this reference is relevant to the concept of encapsulating a component within a package. It could anticipate the "at least one component within the baseboard" and "hardened insulating polymer layer" aspects of Claim 1, especially concerning the packaging of semiconductor components.
JPH04283987A: Electronic circuit device and manufacture thereof
- Full Citation: JPH04283987A
- Publication Date: October 8, 1992
- Filing Date: March 13, 1991
- Brief Description: This Japanese patent application describes an electronic circuit device and its manufacturing method, where electronic components are mounted on a flexible substrate and then covered with a resin layer.
- Potential Anticipation (35 U.S.C. § 102): This reference could potentially anticipate elements of Claim 1, particularly the embedding of components ("at least one component within the baseboard") and the use of a "hardened insulating polymer layer" to cover them, especially given the flexibility aspect mentioned in the US8368201 description.
US5162613A: Integrated circuit interconnection technique
- Full Citation: US5162613A
- Publication Date: November 10, 1992
- Filing Date: July 1, 1991
- Brief Description: This patent describes a technique for interconnecting integrated circuits, focusing on creating electrical connections between layers.
- Potential Anticipation (35 U.S.C. § 102): This reference is most relevant to the "conductors within the hardened insulating polymer layer for forming electrical contacts" aspect of Claim 1, as it deals with interconnection techniques between circuit layers.
US5208188A: Process for making a multilayer lead frame assembly for an integrated circuit structure and multilayer integrated circuit die package formed by such process
- Full Citation: US5208188A
- Publication Date: May 4, 1993
- Filing Date: October 2, 1989
- Brief Description: This patent describes a process for making a multilayer lead frame assembly and a multilayer integrated circuit die package, involving embedding die within layers.
- Potential Anticipation (35 U.S.C. § 102): This reference is highly relevant to the "at least one component within the baseboard" and the overall structure described in Claim 1, particularly its focus on embedding integrated circuit dice within a multilayer structure.
US5216806A: Method of forming a chip package and package interconnects
- Full Citation: US5216806A
- Publication Date: June 8, 1993
- Filing Date: September 1, 1992
- Brief Description: This patent describes a method for forming a chip package and its interconnects, including embedding a chip and forming connections.
- Potential Anticipation (35 U.S.C. § 102): This patent directly addresses the formation of a chip package with interconnects, which aligns with several elements of Claim 1, including the embedded component, insulating layer, and conductors for electrical contacts.
US5227338A: Three-dimensional memory card structure with internal direct chip attachment
- Full Citation: US5227338A
- Publication Date: July 13, 1993
- Filing Date: April 30, 1990
- Brief Description: This patent describes a three-dimensional memory card structure where chips are directly attached internally within the structure.
- Potential Anticipation (35 U.S.C. § 102): This is highly relevant to the "at least one component within the baseboard" feature of Claim 1, especially in the context of creating a compact, multi-layered electronic module. The "internal direct chip attachment" directly relates to embedding components.
US5248852A: Resin circuit substrate and manufacturing method therefor
- Full Citation: US5248852A
- Publication Date: September 28, 1993
- Filing Date: October 20, 1989
- Brief Description: This patent describes a resin circuit substrate and a method for its manufacture, where components are integrated within the resin substrate.
- Potential Anticipation (35 U.S.C. § 102): This reference is relevant to the "baseboard" being a circuit board and "at least one component within the baseboard," as it describes components integrated into a resin substrate. The "hardened insulating polymer layer" could also be anticipated by the resin substrate.
US5250843A: Multichip integrated circuit modules
- Full Citation: US5250843A
- Publication Date: October 5, 1993
- Filing Date: March 27, 1991
- Brief Description: This patent describes multichip integrated circuit modules where multiple chips are packaged together.
- Potential Anticipation (35 U.S.C. § 102): Similar to other multichip packaging references, this patent could anticipate the "at least one component within the baseboard" and the general concept of embedding multiple components within a module.
US5306670A: Multi-chip integrated circuit module and method for fabrication thereof
- Full Citation: US5306670A
- Publication Date: April 26, 1994
- Filing Date: February 9, 1993
- Brief Description: This patent describes a multi-chip integrated circuit module and its fabrication method, where chips are embedded within the module.
- Potential Anticipation (35 U.S.C. § 102): This is highly relevant as it describes both a multi-chip module and a method of fabrication that involves embedding chips, directly anticipating the "at least one component within the baseboard" and the overall electronic module structure of Claim 1.
US5353195A: Integral power and ground structure for multi-chip modules
- Full Citation: US5353195A
- Publication Date: October 4, 1994
- Filing Date: July 9, 1993
- Brief Description: This patent focuses on integral power and ground structures for multi-chip modules, which implies embedded or integrated chips.
- Potential Anticipation (35 U.S.C. § 102): While focusing on power/ground, the underlying structure would inherently involve "at least one component within the baseboard" and "conductive patterns" on layers, making it relevant to Claim 1.
US5497033A: Embedded substrate for integrated circuit modules
- Full Citation: US5497033A
- Publication Date: March 5, 1996
- Filing Date: February 8, 1993
- Brief Description: This patent describes an embedded substrate specifically designed for integrated circuit modules.
- Potential Anticipation (35 U.S.C. § 102): This reference is very closely aligned with the subject matter of Claim 1, directly discussing an "embedded substrate" for integrated circuit modules, which strongly anticipates the "baseboard," "at least one component within the baseboard," and potentially the "hardened insulating polymer layer" and "conductive patterns."
US5637919A: Perimeter independent precision locating member
- Full Citation: US5637919A
- Publication Date: June 10, 1997
- Filing Date: July 28, 1993
- Brief Description: This patent describes a precision locating member for components, which could be used in assembly processes.
- Potential Anticipation (35 U.S.C. § 102): This reference primarily relates to alignment or assembly techniques, which are part of the method described in US8368201 but do not directly anticipate the structural features of Claim 1.
US5870289A: Chip connection structure having direct through-hole connections through adhesive film and wiring substrate
- Full Citation: US5870289A
- Publication Date: February 9, 1999
- Filing Date: December 15, 1994
- Brief Description: This patent describes a chip connection structure with direct through-hole connections through an adhesive film and a wiring substrate.
- Potential Anticipation (35 U.S.C. § 102): This reference is highly relevant to the "conductors within the hardened insulating polymer layer for forming electrical contacts" and the general embedding of components, as it specifically mentions through-hole connections and an adhesive film (which could be a polymer layer) in conjunction with a wiring substrate.
US5943216A: Apparatus for providing a two-sided, cavity, inverted-mounted component circuit board
- Full Citation: US5943216A
- Publication Date: August 24, 1999
- Filing Date: June 3, 1997
- Brief Description: This patent describes an apparatus for a two-sided, cavity, inverted-mounted component circuit board.
- Potential Anticipation (35 U.S.C. § 102): This reference is relevant to the "baseboard" and "at least one component within the baseboard" features, especially if the component is mounted in a cavity. The "inverted-mounted" aspect could relate to the component's first surface being against the polymer layer.
US5970321A: Method of fabricating a microelectronic package having polymer ESD protection
- Full Citation: US5970321A
- Publication Date: October 19, 1999
- Filing Date: January 31, 1996
- Brief Description: This patent describes a method of fabricating a microelectronic package with polymer ESD protection.
- Potential Anticipation (35 U.S.C. § 102): This reference focuses on a microelectronic package and uses a polymer for ESD protection, which aligns with the "hardened insulating polymer layer" and "at least one component within the baseboard" of Claim 1.
US6015722A: Method for assembling an integrated circuit chip package having an underfill material between a chip and a substrate
- Full Citation: US6015722A
- Publication Date: January 18, 2000
- Filing Date: October 14, 1997
- Brief Description: This patent describes a method for assembling an integrated circuit chip package that includes an underfill material between a chip and a substrate.
- Potential Anticipation (35 U.S.C. § 102): This reference is relevant to the connection of components to a substrate, particularly the idea of an intermediate material (like an underfill) which could be analogous to the polymer layer in Claim 1, even if its primary purpose is different.
US6038133A: Circuit component built-in module and method for producing the same
- Full Citation: US6038133A
- Publication Date: March 14, 2000
- Filing Date: November 25, 1997
- Brief Description: This patent describes a circuit component built-in module and a method for producing it, where components are integrated into the module.
- Potential Anticipation (35 U.S.C. § 102): This patent directly addresses the concept of a "built-in module" with integrated components, making it highly relevant to the entire structure of Claim 1, including the "baseboard," "at least one component within the baseboard," and the overall electronic module.
US6100108A: Method of fabricating electronic circuit device
- Full Citation: US6100108A
- Publication Date: August 8, 2000
- Filing Date: February 17, 1997
- Brief Description: This patent describes a method of fabricating an electronic circuit device.
- Potential Anticipation (35 U.S.C. § 102): Without more specific details from the search result, it's hard to precisely pinpoint which claims are anticipated. However, a general method for fabricating an electronic circuit device could potentially encompass aspects of embedding components and forming connections, relevant to Claim 1.
US6131269A: Circuit isolation technique for RF and millimeter-wave modules
- Full Citation: US6131269A
- Publication Date: October 17, 2000
- Filing Date: May 18, 1998
- Brief Description: This patent describes a circuit isolation technique, likely involving shielding, which could relate to the electromagnetic protection mentioned in US8368201's description.
- Potential Anticipation (35 U.S.C. § 102): While US8368201 describes electromagnetic protection in its detailed description, Claim 1 itself does not explicitly include shielding as a required element. Therefore, this reference is less likely to directly anticipate Claim 1.
JP2000311229A: IC card and manufacturing method thereof
- Full Citation: JP2000311229A
- Publication Date: November 7, 2000
- Filing Date: April 27, 1999
- Brief Description: This Japanese patent describes an IC card and its manufacturing method, where an IC chip is embedded.
- Potential Anticipation (35 U.S.C. § 102): This reference is highly relevant as it describes embedding an IC chip, which is a type of component, in an IC card, which could be considered a "base" similar to a circuit board. This could anticipate "at least one component within the baseboard" and the general module structure.
US6154366A: Structures and processes for fabricating moisture resistant chip-on-flex packages
- Full Citation: US6154366A
- Publication Date: November 28, 2000
- Filing Date: November 23, 1999
- Brief Description: This patent describes structures and processes for fabricating moisture-resistant chip-on-flex packages.
- Potential Anticipation (35 U.S.C. § 102): This patent is relevant due to "chip-on-flex" packages, which involve a component (chip) on a flexible base, covered by a protective layer. This directly relates to the "at least one component within the baseboard" and "hardened insulating polymer layer" of Claim 1, especially considering the mention of flexible circuit boards in the US8368201 description.
JP2001053447A: Component built-in multilayer wiring board and method of manufacturing the same
- Full Citation: JP2001053447A
- Publication Date: February 23, 2001
- Filing Date: August 5, 1999
- Brief Description: This Japanese patent describes a component-built-in multilayer wiring board and its manufacturing method.
- Potential Anticipation (35 U.S.C. § 102): This is highly relevant as it describes a "component built-in multilayer wiring board," directly anticipating the "baseboard," "at least one component within the baseboard," and the overall electronic module structure of Claim 1.
US6271469B1: Direct build-up layer on an encapsulated die package
- Full Citation: US6271469B1
- Publication Date: August 7, 2001
- Filing Date: November 12, 1999
- Brief Description: This patent describes a direct build-up layer on an encapsulated die package, indicating embedded or integrated components.
- Potential Anticipation (35 U.S.C. § 102): This reference is relevant to the "at least one component within the baseboard" and the formation of layers, potentially anticipating the "hardened insulating polymer layer" and "conductive patterns" over encapsulated components.
US6284564B1: HDI chip attachment method for reduced processing
- Full Citation: US6284564B1
- Publication Date: September 4, 2001
- Filing Date: September 20, 1999
- Brief Description: This patent describes a High Density Interconnect (HDI) chip attachment method for reduced processing.
- Potential Anticipation (35 U.S.C. § 102): This reference relates to chip attachment, which implies embedding or integrating a component, and the interconnects necessary for electrical contacts, making it relevant to the "at least one component within the baseboard" and "conductors within the hardened insulating polymer layer" aspects of Claim 1.
US6292366B1: Printed circuit board with embedded integrated circuit
- Full Citation: US6292366B1
- Publication Date: September 18, 2001
- Filing Date: June 26, 2000
- Brief Description: This patent describes a printed circuit board with an embedded integrated circuit.
- Potential Anticipation (35 U.S.C. § 102): This is exceptionally relevant as it directly describes a "printed circuit board with embedded integrated circuit," essentially encompassing the core features of Claim 1: "baseboard" (PCB), "at least one component within the baseboard" (embedded IC), and the implied presence of "hardened insulating polymer layer" and "conductive patterns" in a PCB structure.
JP2001274034A: Electronic component package
- Full Citation: JP2001274034A
- Publication Date: October 5, 2001
- Filing Date: January 20, 2000
- Brief Description: This Japanese patent describes an electronic component package.
- Potential Anticipation (35 U.S.C. § 102): General electronic component packages often involve embedding or encapsulating components, making this potentially relevant to the "at least one component within the baseboard" and "hardened insulating polymer layer" features of Claim 1.
US6324067B1: Printed wiring board and assembly of the same
- Full Citation: US6324067B1
- Publication Date: November 27, 2001
- Filing Date: November 16, 1995
- Brief Description: This patent describes a printed wiring board and its assembly.
- Potential Anticipation (35 U.S.C. § 102): This reference, dealing with printed wiring boards, would implicitly cover the "baseboard" and "conductive patterns." If it describes components embedded within the board, it could anticipate other aspects of Claim 1.
JP2001345560A: Wiring board, and its manufacturing method, and electronic component
- Full Citation: JP2001345560A
- Publication Date: December 14, 2001
- Filing Date: February 9, 2000
- Brief Description: This Japanese patent describes a wiring board, its manufacturing method, and an electronic component.
- Potential Anticipation (35 U.S.C. § 102): Similar to JP2001053447A and US6324067B1, this reference's focus on a "wiring board" and "electronic component" can be relevant to the "baseboard" and "at least one component within the baseboard" of Claim 1.
US20010054758A1: Three-dimensional memory stacking using anisotropic epoxy interconnections
- Full Citation: US20010054758A1
- Publication Date: December 27, 2001
- Filing Date: June 21, 2000
- Brief Description: This patent application describes three-dimensional memory stacking using anisotropic epoxy interconnections.
- Potential Anticipation (35 U.S.C. § 102): This reference is highly relevant to the concept of stacking components and forming interconnections with an epoxy (polymer) material. It could anticipate "at least one component within the baseboard," "hardened insulating polymer layer," and "conductors within the hardened insulating polymer layer" in the context of a three-dimensional module.
JP2002016327A: Wiring board and method of manufacturing the same
- Full Citation: JP2002016327A
- Publication Date: January 18, 2002
- Filing Date: April 24, 2000
- Brief Description: This Japanese patent describes a wiring board and a method of manufacturing it.
- Potential Anticipation (35 U.S.C. § 102): Similar to other wiring board patents, this would be relevant to the "baseboard" and "conductive patterns" of Claim 1. If it includes embedded components, it would be even more directly anticipatory.
US20020020898A1: Microelectronic substrates with integrated devices
- Full Citation: US20020020898A1
- Publication Date: February 21, 2002
- Filing Date: August 16, 2000
- Brief Description: This patent application describes microelectronic substrates with integrated devices.
- Potential Anticipation (35 U.S.C. § 102): This reference is directly relevant to "microelectronic substrates" (baseboard) with "integrated devices" (components within the baseboard), making it highly anticipatory of Claim 1. The integration implies insulating layers and conductive patterns for connections.
US6350633B1: Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint
- Full Citation: US6350633B1
- Publication Date: February 26, 2002
- Filing Date: August 22, 2000
- Brief Description: This patent describes a semiconductor chip assembly with simultaneously electroplated contact terminals and connection joints.
- Potential Anticipation (35 U.S.C. § 102): This reference is relevant to the "conductors within the hardened insulating polymer layer for forming electrical contacts" aspect of Claim 1, particularly concerning the formation of electrical contacts to a component.
US6396148B1: Electroless metal connection structures and methods
- Full Citation: US6396148B1
- Publication Date: May 28, 2002
- Filing Date: February 10, 2000
- Brief Description: This patent describes electroless metal connection structures and methods.
- Potential Anticipation (35 U.S.C. § 102): This reference focuses on methods of forming conductive connections, which could be relevant to the "conductive patterns" and "conductors within the hardened insulating polymer layer" of Claim 1.
US20020063342A1: Pre-bond encapsulation of area array terminated chip and wafer scale packages
- Full Citation: US20020063342A1
- Publication Date: May 30, 2002
- Filing Date: August 9, 1999
- Brief Description: This patent application describes pre-bond encapsulation of chip and wafer scale packages.
- Potential Anticipation (35 U.S.C. § 102): This reference is relevant to encapsulating components ("at least one component within the baseboard") using a material that could be a "hardened insulating polymer layer" as described in Claim 1.
JP2002158307A: Semiconductor device and manufacturing method thereof
- Full Citation: JP2002158307A
- Publication Date: May 31, 2002
- Filing Date: November 22, 2000
- Brief Description: This Japanese patent describes a semiconductor device and its manufacturing method.
- Potential Anticipation (35 U.S.C. § 102): A general semiconductor device patent, depending on its specific details, could anticipate the "at least one component within the baseboard" and associated structures of Claim 1.
US20020117743A1: Component built-in module and method for producing the same
- Full Citation: US20020117743A1
- Publication Date: August 29, 2002
- Filing Date: December 27, 2000
- Brief Description: This patent application describes a component built-in module and a method for producing it.
- Potential Anticipation (35 U.S.C. § 102): This is highly relevant as it describes a "component built-in module," directly anticipating the "baseboard," "at least one component within the baseboard," and the overall electronic module structure of Claim 1.
US20020127770A1: Die support structure
- Full Citation: US20020127770A1
- Publication Date: September 12, 2002
- Filing Date: March 9, 2001
- Brief Description: This patent application describes a die support structure.
- Potential Anticipation (35 U.S.C. § 102): A die support structure would inherently be part of the "baseboard" and would support "at least one component within the baseboard," making it relevant to Claim 1.
US20020132096A1: Wiring board
- Full Citation: US20020132096A1
- Publication Date: September 19, 2002
- Filing Date: December 25, 2000
- Brief Description: This patent application describes a wiring board.
- Potential Anticipation (35 U.S.C. § 102): Similar to other wiring board patents, this would be relevant to the "baseboard" and "conductive patterns" of Claim 1.
US6475877B1: Method for aligning die to interconnect metal on flex substrate
- Full Citation: US6475877B1
- Publication Date: November 5, 2002
- Filing Date: December 22, 1999
- Brief Description: This patent describes a method for aligning a die to interconnect metal on a flexible substrate.
- Potential Anticipation (35 U.S.C. § 102): While this is a method patent, the underlying structure it describes would include a component (die) on a substrate (baseboard) with interconnects (conductive patterns and conductors), and a flexible substrate is mentioned as a possible embodiment in US8368201. This could be relevant to the structural features of Claim 1.
US6489685B2: Component built-in module and method of manufacturing the same
- Full Citation: US6489685B2
- Publication Date: December 3, 2002
- Filing Date: January 19, 2001
- Brief Description: This patent describes a component built-in module and a method of manufacturing it.
- Potential Anticipation (35 U.S.C. § 102): This is highly relevant as it describes a "component built-in module," directly anticipating the "baseboard," "at least one component within the baseboard," and the overall electronic module structure of Claim 1.
US20020185303A1: Wiring circuit board and method for producing same
- Full Citation: US20020185303A1
- Publication Date: December 12, 2002
- Filing Date: March 12, 2001
- Brief Description: This patent application describes a wiring circuit board and a method for producing it.
- Potential Anticipation (35 U.S.C. § 102): Similar to other wiring board patents, this would be relevant to the "baseboard" and "conductive patterns" of Claim 1.
US6495394B1: Chip package and method for manufacturing the same
- Full Citation: US6495394B1
- Publication Date: December 17, 2002
- Filing Date: February 16, 1999
- Brief Description: This patent describes a chip package and a method for manufacturing it.
- Potential Anticipation (35 U.S.C. § 102): This reference directly describes a "chip package," which would inherently include a "component" (chip) and a surrounding structure, potentially anticipating the "hardened insulating polymer layer" and other aspects of Claim 1.
JP2003037205A: Multilayer substrate with built-in IC chip and method of manufacturing the same
- Full Citation: JP2003037205A
- Publication Date: February 7, 2003
- Filing Date: July 23, 2001
- Brief Description: This Japanese patent describes a multilayer substrate with a built-in IC chip and a method for manufacturing it.
- Potential Anticipation (35 U.S.C. § 102): This is highly relevant as it describes a "multilayer substrate with built-in IC chip," directly anticipating the "baseboard," "at least one component within the baseboard," and the overall electronic module structure of Claim 1. Its publication date is after the priority date of US8368201, but its filing date is before.
US6521530B2: Composite interposer and method for producing a composite interposer
- Full Citation: US6521530B2
- Publication Date: February 18, 2003
- Filing Date: November 13, 1998
- Brief Description: This patent describes a composite interposer and a method for producing it.
- Potential Anticipation (35 U.S.C. § 102): An interposer serves as an intermediate connection layer, which would include "conductive patterns" and potentially insulating layers, relevant to Claim 1's features regarding electrical connections. Its publication date is after the priority date of US8368201, but its filing date is before.
US6537848B2: Super thin/super thermal ball grid array package
- Full Citation: US6537848B2
- Publication Date: March 25, 2003
- Filing Date: May 30, 2001
- Brief Description: This patent describes a super thin/super thermal ball grid array package.
- Potential Anticipation (35 U.S.C. § 102): While focused on thermal management and thinness, this patent describes a package (electronic module) with a component (BGA), which implies embedded components and insulating layers, making it relevant to Claim 1. Its publication date is after the priority date of US8368201, but its filing date is before.
US6538210B2: Circuit component built-in module, radio device having the same, and method for producing the same
- Full Citation: US6538210B2
- Publication Date: March 25, 2003
- Filing Date: December 20, 1999
- Brief Description: This patent describes a circuit component built-in module and a method for producing it.
- Potential Anticipation (35 U.S.C. § 102): This is highly relevant as it describes a "circuit component built-in module," directly anticipating the "baseboard," "at least one component within the baseboard," and the overall electronic module structure of Claim 1. Its publication date is after the priority date of US8368201, but its filing date is before.
US20030068852A1: Protective film for the fabrication of direct build-up layers on an encapsulated die package
- Full Citation: US20030068852A1
- Publication Date: April 10, 2003
- Filing Date: September 13, 2000
- Brief Description: This patent application describes a protective film for the fabrication of direct build-up layers on an encapsulated die package.
- Potential Anticipation (35 U.S.C. § 102): This reference directly discusses encapsulated die packages and protective films, aligning with the "at least one component within the baseboard" and "hardened insulating polymer layer" of Claim 1. Its publication date is after the priority date of US8368201, but its filing date is before.
US6562657B1: Semiconductor chip assembly with simultaneously electrolessly plated contact terminal and connection joint
- Full Citation: US6562657B1
- Publication Date: May 13, 2003
- Filing Date: August 22, 2000
- Brief Description: This patent describes a semiconductor chip assembly with simultaneously electrolessly plated contact terminals and connection joints.
- Potential Anticipation (35 U.S.C. § 102): This reference is relevant to the "conductors within the hardened insulating polymer layer for forming electrical contacts" aspect of Claim 1, particularly concerning the formation of electrical contacts to a component. Its publication date is after the priority date of US8368201, but its filing date is before.
US20030090883A1: Component built-in module and method for producing the same
- Full Citation: US20030090883A1
- Publication Date: May 15, 2003
- Filing Date: October 18, 2001
- Brief Description: This patent application describes a component built-in module and a method for producing it.
- Potential Anticipation (35 U.S.C. § 102): This is highly relevant as it describes a "component built-in module," directly anticipating the "baseboard," "at least one component within the baseboard," and the overall electronic module structure of Claim 1. Its publication date is after the priority date of US8368201, but its filing date is before.
US20030100142A1: Semiconductor package and method for fabricating the same
- Full Citation: US20030100142A1
- Publication Date: May 29, 2003
- Filing Date: May 7, 1999
- Brief Description: This patent application describes a semiconductor package and a method for fabricating the same.
- Potential Anticipation (35 U.S.C. § 102): This reference describes a semiconductor package, which would encompass a component (semiconductor) and a surrounding structure, potentially anticipating the "hardened insulating polymer layer" and other aspects of Claim 1. Its publication date is after the priority date of US8368201, but its filing date is before.
US20030137045A1: Circuit component built-in module and method of manufacturing the same
- Full Citation: US20030137045A1
- Publication Date: July 24, 2003
- Filing Date: January 23, 2002
- Brief Description: This patent application describes a circuit component built-in module and a method of manufacturing the same.
- Potential Anticipation (35 U.S.C. § 102): This is highly relevant as it describes a "circuit component built-in module," directly anticipating the "baseboard," "at least one component within the baseboard," and the overall electronic module structure of Claim 1. Its publication date and filing date are after the priority date of US8368201.
US6607943B1: Low profile ball grid array package
- Full Citation: US6607943B1
- Publication Date: August 19, 2003
- Filing Date: February 24, 1998
- Brief Description: This patent describes a low profile ball grid array package.
- Potential Anticipation (35 U.S.C. § 102): A BGA package is an electronic module containing a component. This would be relevant to the "at least one component within the baseboard" and the overall package structure of Claim 1. Its publication date is after the priority date of US8368201, but its filing date is before.
US6710458B2: Tape for chip on film and semiconductor therewith
- Full Citation: US6710458B2
- Publication Date: March 23, 2004
- Filing Date: October 13, 2000
- Brief Description: This patent describes a tape for chip-on-film applications and associated semiconductors.
- Potential Anticipation (35 U.S.C. § 102): "Chip on film" technology involves a component on a flexible film, similar to the flexible circuit board mentioned in US8368201. This would be relevant to the "baseboard," "at least one component within the baseboard," and "hardened insulating polymer layer" of Claim 1. Its publication date is after the priority date of US8368201, but its filing date is before.
US6790712B2: Semiconductor device and method for fabricating the same
- Full Citation: US6790712B2
- Publication Date: September 14, 2004
- Filing Date: March 21, 2001
- Brief Description: This patent describes a semiconductor device and a method for fabricating the same.
- Potential Anticipation (35 U.S.C. § 102): A general semiconductor device patent, depending on its specific details, could anticipate the "at least one component within the baseboard" and associated structures of Claim 1. Its publication date is after the priority date of US8368201, but its filing date is before.
US6979596B2: Method of fabricating a tape having apertures under a lead frame for conventional IC packages
- Full Citation: US6979596B2
- Publication Date: December 27, 2005
- Filing Date: March 19, 1996
- Brief Description: This patent describes a method of fabricating a tape with apertures under a lead frame for IC packages.
- Potential Anticipation (35 U.S.C. § 102): This reference relates to IC packages and apertures, which could be relevant to the structural arrangement of components and electrical connections within a package, relevant to Claim 1. Its publication date is after the priority date of US8368201, but its filing date is before.
US20050285244A1: Method of embedding semiconductor element in carrier and embedded structure thereof
- Full Citation: US20050285244A1
- Publication Date: December 29, 2005
- Filing Date: June 29, 2004
- Brief Description: This patent application describes a method of embedding a semiconductor element in a carrier and the resulting embedded structure.
- Potential Anticipation (35 U.S.C. § 102): This is highly relevant as it describes embedding a semiconductor element in a carrier (baseboard) and the resulting embedded structure. This directly anticipates many aspects of Claim 1, including the component within the baseboard and the overall structure. Its publication date and filing date are after the priority date of US8368201.
US20060105500A1: Process for fabricating chip embedded package structure
- Full Citation: US20060105500A1
- Publication Date: May 18, 2006
- Filing Date: May 11, 2004
- Brief Description: This patent application describes a process for fabricating a chip embedded package structure.
- Potential Anticipation (35 U.S.C. § 102): This is highly relevant as it describes a "chip embedded package structure," directly anticipating the "baseboard," "at least one component within the baseboard," and the overall electronic module structure of Claim 1. Its publication date and filing date are after the priority date of US8368201.
JP2002202025A: Injector integrated module
- Full Citation: JP2002202025A
- Publication Date: July 19, 2002
- Filing Date: November 6, 2000
- Brief Description: This Japanese patent describes an injector integrated module.
- Potential Anticipation (35 U.S.C. § 102): This reference is relevant to the general concept of an "electronic module" containing integrated components, but more specific details would be needed to assess anticipation of particular elements of Claim 1. Its publication date is after the priority date of US8368201, but its filing date is before.
RU2001132099A: METHOD FOR PRODUCING MICROPLATES
- Full Citation: RU2001132099A
- Publication Date: July 20, 2003
- Filing Date: November 29, 2001
- Brief Description: This Russian patent describes a method for producing microplates.
- Potential Anticipation (35 U.S.C. § 102): Without more specific details about the microplates, it's difficult to assess direct anticipation. However, "microplates" could be considered a type of base or substrate for electronic components. Its publication date and filing date are after the priority date of US8368201.

Summary of Most Relevant Prior Art for Claim 1 (by filing/priority date before US8368201's priority date of 2002-01-31):

Based on the analysis, several references stand out as highly relevant for potentially anticipating Claim 1 of US8368201 due to their clear descriptions of embedding components within a base or substrate, forming insulating layers, and creating electrical connections. The most notable among these are:

US6292366B1 (Filing Date: June 26, 2000): Printed circuit board with embedded integrated circuit. This patent directly describes a "printed circuit board with embedded integrated circuit," which aligns almost entirely with the core elements of Claim 1.
JP2001053447A (Filing Date: August 5, 1999): Component built-in multilayer wiring board and method of manufacturing the same. This also directly describes a "component built-in multilayer wiring board," strongly anticipating the elements of Claim 1.
US5497033A (Filing Date: February 8, 1993): Embedded substrate for integrated circuit modules. This patent is highly relevant due to its focus on an "embedded substrate for integrated circuit modules."
US5306670A (Filing Date: February 9, 1993): Multi-chip integrated circuit module and method for fabrication thereof. This patent describes a multi-chip module with embedded chips.
US20010054758A1 (Filing Date: June 21, 2000): Three-dimensional memory stacking using anisotropic epoxy interconnections. This reference highlights component stacking and epoxy (polymer) interconnections, anticipating multiple aspects of Claim 1 in a 3D context.
US6038133A (Filing Date: November 25, 1997): Circuit component built-in module and method for producing the same. This directly addresses the concept of a "built-in module" with integrated components.
US20020020898A1 (Filing Date: August 16, 2000): Microelectronic substrates with integrated devices. This describes microelectronic substrates with integrated devices.
US5870289A (Filing Date: December 15, 1994): Chip connection structure having direct through-hole connections through adhesive film and wiring substrate. This is very relevant to the interconnection elements within the polymer layer.

These patents and applications, filed or published before the priority date of US8368201, disclose similar structural arrangements involving embedded components, insulating layers, and conductive patterns, which are the fundamental features of Claim 1.