Obviousness

To analyze the obviousness of US patent 8368201 under 35 U.S.C. § 103, we will consider the claims of the patent and relevant prior art references. The authoritative priority date for US8368201 is January 31, 2002.

Independent Claim 1 of US8368201 defines an electronic module comprising:

1. A baseboard having a first surface and a second surface;
2. A hardened insulating polymer layer on the second surface of the baseboard;
3. At least one component within the baseboard, the component having contact areas on a first surface of the component, said first surface of the component being against the hardened insulating polymer layer;
4. Conductive patterns on the hardened insulating polymer layer; and
5. Conductors within the hardened insulating polymer layer for forming electrical contacts between at least some of the conductive patterns and at least some of the contact areas of the component.

The following prior art references, published before the priority date of US8368201, are particularly relevant for an obviousness analysis:

• US5870289A (Hitachi, Ltd.) published on February 9, 1999, titled "Chip connection structure having direct through-hole connections through adhesive film and wiring substrate".
• US6292366B1 (Intel Corporation) published on September 18, 2001, titled "Printed circuit board with embedded integrated circuit".

Obviousness Analysis: Combination of US5870289A and US6292366B1

A person having ordinary skill in the art (POSA) in circuit board manufacturing, at the time of the invention of US8368201 (i.e., before January 31, 2002), would have been motivated to combine the teachings of US5870289A and US6292366B1 to arrive at the subject matter of Claim 1 of US8368201.

Motivation for Combination:
US5870289A specifically discloses a method and structure for embedding an IC chip in a wiring substrate and making through-hole connections through an adhesive film. This reference provides a detailed approach to physically integrating a component into a base and establishing initial electrical connections. US6292366B1, on the other hand, describes a printed circuit board with an embedded integrated circuit, and more broadly teaches that an embedded IC package is completed by forming "a series of dielectric layers, via holes, and metal layers using conventional PCB fabrication techniques." A POSA, seeking to create a fully functional electronic module with an embedded component, would naturally look to combine the specific embedding and initial connection techniques of US5870289A with the general, well-known build-up processes for forming complete circuit board packages, as taught by US6292366B1. The motivation would be to utilize the advantages of embedded components while ensuring comprehensive electrical connectivity and package completion.

Analysis of Claim Elements:

1. A baseboard having a first surface and a second surface:

   • US5870289A teaches a "wiring substrate 1" with a recess 2 for mounting an IC chip. Any such substrate inherently has distinct surfaces. This element would be obvious to a POSA.

2. A hardened insulating polymer layer on the second surface of the baseboard:

   • US5870289A discloses an "adhesive film 4" used to mount the IC chip 3 in the recess 2 of the wiring substrate 1. The electrodes 3a of the IC chip are positioned against this film. This adhesive film, upon curing (a standard process for adhesives), would become a hardened insulating polymer layer. When a component is inserted into a through-hole in a baseboard, the film at the bottom of that hole, against which the component sits, can be considered as being "on the second surface" in the context of the overall board structure.

3. At least one component within the baseboard, the component having contact areas on a first surface of the component, said first surface of the component being against the hardened insulating polymer layer:

   • US5870289A explicitly shows an "IC chip 3" mounted in a "recess 2" of a "wiring substrate 1". The IC chip has "electrodes 3a" (contact areas) which are positioned against the "adhesive film 4". This directly teaches a component within the baseboard, with its contact areas on a first surface being against the hardened insulating polymer layer.

4. Conductive patterns on the hardened insulating polymer layer:

   • US5870289A shows "wiring patterns 5" formed on the wiring substrate 1. While these patterns are shown on the main substrate surface and not explicitly directly on the surface of the adhesive film 4 in all illustrations, US6292366B1 teaches that an embedded IC package is completed by forming "metal layers" (i.e., conductive patterns) on "dielectric layers" (i.e., insulating polymer layers) using conventional PCB fabrication techniques. A POSA would understand that to complete the module and connect to the embedded component, conductive patterns would need to be formed on or in electrical communication with the insulating polymer layer (adhesive film 4 of US5870289A) or subsequent dielectric layers built upon it. Combining these teachings would lead a POSA to form conductive patterns on the hardened insulating polymer layer to create a functional module.

5. Conductors within the hardened insulating polymer layer for forming electrical contacts between at least some of the conductive patterns and at least some of the contact areas of the component:

   • US5870289A clearly teaches "Through-holes 6" formed in the "adhesive film 4" and the "wiring substrate 1" at positions corresponding to the "electrodes 3a" of the IC chip 3. These through-holes 6 are then filled with "conductive material 7", which connects the chip's electrodes 3a to the "wiring patterns 5" on the substrate. These filled through-holes (conductive material 7) directly constitute the "conductors within the hardened insulating polymer layer" for forming electrical contacts between the conductive patterns and the component's contact areas.

Therefore, the combination of US5870289A and US6292366B1 would have rendered Claim 1 of US8368201 obvious to a person having ordinary skill in the art at the time of the invention.