Patent 8198686
Derivative works
Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.
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Derivative works
Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.
Defensive Disclosure: US Patent 8,198,686 Derivative Variations
This document outlines derivative variations of the semiconductor device and manufacturing methods described in US Patent 8,198,686. These disclosures aim to expand the existing prior art, rendering future incremental advancements by competitors obvious or non-novel, and thereby enhancing defensive intellectual property strategy.
Derivative Variations for Core Claims (Claim 1, Claim 11, Claim 12)
The following derivatives build upon the foundational concepts of dual-metal gate MISFETs and their fabrication, as taught in US Patent 8,198,686, particularly focusing on Claim 1 (the semiconductor device) and Claims 11/12 (the manufacturing methods).
1. Material & Component Substitution
Derivative 1.1: High-Mobility III-V Channel with Germanium Source/Drain
Enabling Description:
This variation of the semiconductor device (Claim 1) features a first MIS transistor and a second MIS transistor fabricated on a semiconductor substrate. Instead of a silicon substrate, the channel regions for both transistors are formed from a high-mobility III-V compound semiconductor, such as InGaAs, epitaxially grown on a silicon or III-V buffer layer. The source/drain regions for both n-type and p-type MISFETs are formed using epitaxially grown Germanium (Ge) layers, possibly doped with n-type (e.g., P, As) or p-type (e.g., Ga, In) impurities, to further enhance carrier mobility and reduce series resistance. The first and second gate insulating films (Claim 1) would consist of high-k dielectrics like Al2O3 or ZrO2, which are compatible with III-V interfaces, deposited via Atomic Layer Deposition (ALD). The gate electrodes would utilize specific metal materials: for n-type MISFETs, a metal or metal nitride with a work function tuned for InGaAs (e.g., TiN, TaN, or HfAl), and for p-type MISFETs, a metal with a higher work function (e.g., Ru, Pt, or W). The insulating film covering side surfaces and active regions remains a silicon nitride or silicon oxide, deposited via plasma-enhanced CVD (PECVD).
graph TD
subgraph Semiconductor Device (Claim 1)
SUB[Substrate (Si/III-V Buffer)] --> EPI[Epitaxial InGaAs Channel]
EPI --> S1D1[Ge Source/Drain (N-type)]
EPI --> S2D2[Ge Source/Drain (P-type)]
S1D1 --> FIGF1[First Gate Insulating Film (Al2O3/ZrO2)]
FIGF1 --> FGE1[First Gate Electrode (n-type metal/metal nitride)]
S2D2 --> SIGF2[Second Gate Insulating Film (Al2O3/ZrO2)]
SIGF2 --> SGE2[Second Gate Electrode (p-type metal)]
FGE1 -- covered by --> IF[Insulating Film (SiN/SiO2)]
SGE2 -- covered by --> IF
IF -- not on --> FGE1_TOP[Top Surface of First Gate]
IF -- not on --> SGE2_TOP[Top Surface of Second Gate]
end
Derivative 1.2: Metal Oxide/Nitride Multilayer Gate Electrodes with Ferroelectric Gate Dielectric
Enabling Description:
This derivative (Claim 1) focuses on advanced gate stack engineering. The first and second gate insulating films are replaced with a ferroelectric material, such as HfZrO (HZO) or BaTiO3, offering potential for negative capacitance FETs and improved subthreshold swing. The manufacturing method (Claim 12) would involve depositing this ferroelectric film. The first and second metal films (Claim 1) are replaced with multilayer metal oxide or nitride stacks for precise work function tuning. For example, the n-type gate electrode (corresponding to the second metal film in Claim 1) could be a stack of La2O3/TiN/TaN, while the p-type gate electrode (corresponding to the first metal film and conductive film in Claim 1) could be RuO2/TiN/W. The individual layers within these gate electrodes would be ultrathin (< 5 nm) and deposited using ALD or physical vapor deposition (PVD) to achieve desired effective work functions and enable dual work function tuning on the same chip. The external insulating film (Claim 1, covering sides) could be an optimized stress liner, such as highly-strained SiN, applied at specific temperatures to induce beneficial channel stress.
graph TD
subgraph Semiconductor Device (Claim 1)
SUB[Semiconductor Substrate] --> FGT[First Gate (N-MISFET)]
SUB --> SGT[Second Gate (P-MISFET)]
FGT --> FGIF[Ferroelectric Gate Insulating Film (HZO)]
FGIF --> FGE_STACK[First Gate Electrode Stack (La2O3/TiN/TaN)]
SGT --> SGIF[Ferroelectric Gate Insulating Film (HZO)]
SGIF --> SGE_STACK[Second Gate Electrode Stack (RuO2/TiN/W)]
FGE_STACK -- Side Surfaces Covered by --> SIL[Stress Insulating Layer]
SGE_STACK -- Side Surfaces Covered by --> SIL
SIL -- Not on Top --> FGE_TOP[Top of First Gate Electrode]
SIL -- Not on Top --> SGE_TOP[Top of Second Gate Electrode]
end
Derivative 1.3: Graphene or 2D Material Channels with Ionic Liquid Gates
Enabling Description:
This extreme material substitution (Claim 1) envisions the MISFETs utilizing 2D materials like graphene, MoS2, or WSe2 as the channel material, grown or transferred onto a suitable insulating substrate (e.g., SiO2/Si or sapphire). The gate insulating film could be an ultra-thin hexagonal boron nitride (hBN) layer. For further tuning and low-voltage operation, the gate electrode material (both first and second metal films) could incorporate ionic liquids, where an electric double layer forms at the interface, providing very high capacitance. This would drastically change the 'metal' material in the claims to an electrically conductive ionic compound, potentially within a solid polymer electrolyte. The manufacturing method (Claim 11) would involve advanced transfer techniques for 2D materials and specialized deposition or printing methods for ionic liquid components, followed by encapsulation. The "insulating film" in this context could be a protective polymer layer.
graph TD
subgraph Semiconductor Device (Claim 1)
SUB[Insulating Substrate (SiO2/Sapphire)] --> CHANNEL[2D Material Channel (Graphene/MoS2)]
CHANNEL --> N_ILG[N-type Ionic Liquid Gate]
CHANNEL --> P_ILG[P-type Ionic Liquid Gate]
N_ILG -- separated by --> hBN_N[hBN Gate Insulator]
P_ILG -- separated by --> hBN_P[hBN Gate Insulator]
N_ILG -- encapsulated by --> POLY_ENCAP[Polymer Encapsulation Layer]
P_ILG -- encapsulated by --> POLY_ENCAP
POLY_ENCAP -- not on --> N_ILG_TOP[Top Surface of N-ILG]
POLY_ENCAP -- not on --> P_ILG_TOP[Top Surface of P-ILG]
end
2. Operational Parameter Expansion
Derivative 2.1: Cryogenic Operation for Quantum Computing Interfaces
Enabling Description:
This derivative (Claim 1) details MISFETs specifically designed for operation at cryogenic temperatures (e.g., 4K or mK) for interfacing with quantum bits. The semiconductor substrate could be silicon-on-insulator (SOI) to minimize parasitic capacitance and heat leakage, with active regions engineered for low-temperature performance. The gate insulating films (Claim 1) would be chosen for minimal trap density and stable dielectric properties at extreme cold, such as high-purity HfO2 or Al2O3. The dual-metal gate electrodes (Claim 1) would use superconductors or low-resistivity metals at these temperatures (e.g., Niobium Titanium nitride (NbTiN) for n-type and doped polysilicon with a superconducting cap for p-type, or even exotic work-function materials like YBCO for high-Tc superconductivity). The manufacturing process (Claim 11) would emphasize ultra-clean processing to prevent defects that cause charge trapping at low temperatures, and materials must be selected to avoid phase transitions or thermal expansion mismatches when cooled. The insulating film covering the sides must also maintain structural integrity and insulating properties at cryogenic temperatures.
graph TD
subgraph Cryogenic Device (Claim 1)
SUB[SOI Substrate] --> N_MIS_C[N-Type MISFET @ Cryo Temp]
SUB --> P_MIS_C[P-Type MISFET @ Cryo Temp]
N_MIS_C --> N_FIF_C[First Gate Insulating Film (High-Purity Al2O3)]
N_FIF_C --> N_FGE_C[First Gate Electrode (NbTiN)]
P_MIS_C --> P_SIF_C[Second Gate Insulating Film (High-Purity Al2O3)]
P_SIF_C --> P_SGE_C[Second Gate Electrode (Doped Poly-Si + Superconducting Cap)]
N_FGE_C -- sidewall covered by --> CRYO_INS[Cryogenic Insulating Film]
P_SGE_C -- sidewall covered by --> CRYO_INS
CRYO_INS -- not on top --> N_FGE_C_TOP
CRYO_INS -- not on top --> P_SGE_C_TOP
end
Derivative 2.2: High-Voltage, High-Frequency Power MISFETs
Enabling Description:
This derivative (Claim 1) scales the technology for high-power, high-frequency applications, specifically focusing on wide bandgap (WBG) semiconductors like Silicon Carbide (SiC) or Gallium Nitride (GaN). The semiconductor substrate would be SiC or GaN, which inherently supports higher breakdown voltages and operating frequencies. The active regions (Claim 1) are defined in these WBG materials. The gate insulating films (Claim 1) would be specialized high-k dielectrics with excellent interface quality and breakdown strength on SiC/GaN, such as AlN/GaN stack or Al2O3 on SiC. The gate electrodes (first and second metal films, Claim 1) would be designed for high thermal stability and appropriate work functions on WBG materials (e.g., TiN, W for n-type; Ni, Pt for p-type). The manufacturing method (Claim 11/12) would incorporate specialized epitaxy, high-temperature annealing steps (up to 1500°C for SiC activation), and dry etching techniques compatible with WBG materials. The surrounding insulating film must be robust against high electric fields and high operating temperatures.
graph TD
subgraph High-Power RF Device (Claim 1)
WBG_SUB[SiC/GaN Substrate] --> N_MIS_HV[N-Type HV MISFET]
WBG_SUB --> P_MIS_HV[P-Type HV MISFET]
N_MIS_HV --> N_FIF_HV[First Gate Insulating Film (AlN/Al2O3)]
N_FIF_HV --> N_FGE_HV[First Gate Electrode (TiN/W)]
P_MIS_HV --> P_SIF_HV[Second Gate Insulating Film (AlN/Al2O3)]
P_SIF_HV --> P_SGE_HV[Second Gate Electrode (Ni/Pt)]
N_FGE_HV -- sidewall covered by --> HV_ENCAP[High-Voltage Insulating Film]
P_SGE_HV -- sidewall covered by --> HV_ENCAP
HV_ENCAP -- not on top --> N_FGE_HV_TOP
HV_ENCAP -- not on top --> P_SGE_HV_TOP
end
3. Cross-Domain Application
Derivative 3.1: Biosensing Platform with Integrated Dual-Gate FETs
Enabling Description:
This variation applies the semiconductor device (Claim 1) as a label-free biosensor. The first active region is functionalized with a biomolecule receptor (e.g., antibody, DNA probe) while the second active region serves as a reference or is functionalized with a different receptor. The gate insulating films (Claim 1) are exposed to a liquid sample, acting as solution-gate dielectrics. The dual-metal gate electrodes are buried or side-gated, and their precise work function control (as enabled by the manufacturing method of Claim 11) is used to establish baseline threshold voltages. Changes in the surface charge due to biomolecule binding on the functionalized active region cause a shift in the threshold voltage of the corresponding MISFET, which is then detected. The "insulating film" (Claim 1) covering the side surfaces of the gate electrodes would be a biocompatible passivation layer (e.g., parylene or specialized oxides/nitrides) to isolate the gate metals from the liquid environment while leaving the active channel exposed. The overall structure allows for differential sensing against the reference channel.
graph TD
subgraph Biosensor Device (Claim 1)
SUB[Si Substrate] --> N_MIS_BIO[N-Type MISFET (Sensing)]
SUB --> P_MIS_BIO[P-Type MISFET (Reference)]
N_MIS_BIO --> N_GIF_BIO[Gate Insulating Film (Exposed to Sample)]
N_GIF_BIO --> N_GE_BIO[Gate Electrode (Buried, Tuned Work Function)]
P_MIS_BIO --> P_GIF_BIO[Gate Insulating Film (Exposed to Sample)]
P_GIF_BIO --> P_GE_BIO[Gate Electrode (Buried, Tuned Work Function)]
N_GE_BIO -- encapsulated by --> BIO_PASS[Biocompatible Passivation Layer]
P_GE_BIO -- encapsulated by --> BIO_PASS
BIO_PASS -- on sides, not on channel --> N_CHANNEL_EXP[Exposed Sensing Channel]
BIO_PASS -- on sides, not on channel --> P_CHANNEL_EXP[Exposed Reference Channel]
N_GIF_BIO -- functionalized with --> RECEPTOR[Biomolecule Receptor]
end
Derivative 3.2: Radiation-Hardened Integrated Circuits for Space Applications
Enabling Description:
This derivative leverages the robust gate electrode formation and isolation of US Patent 8,198,686 for integrated circuits intended for space and high-radiation environments. The semiconductor substrate would be a silicon-on-insulator (SOI) wafer with a thick buried oxide (BOX) layer to provide enhanced isolation against single-event upsets (SEUs) and total ionizing dose (TID) effects. The gate insulating films (Claim 1) would use radiation-hardened dielectrics such as specially treated SiO2 or Al2O3, known for their low interface trap density and charge trapping under radiation exposure. The dual-metal gate electrodes (Claim 1) would be designed with materials highly resistant to radiation-induced shifts in work function or material degradation (e.g., Pt, W, or TiN with specific grain structures). The insulating film covering the side surfaces and active regions would be a thick, dense Si3N4 layer, providing additional shielding and structural integrity against mechanical stress during launch and thermal cycling in space. The manufacturing method (Claim 11) would incorporate specific steps like pre- and post-radiation annealing, and material choices would focus on inherent radiation tolerance.
graph TD
subgraph Rad-Hard IC (Claim 1)
SOI_SUB[SOI Substrate with Thick BOX] --> N_MIS_RH[N-Type Rad-Hard MISFET]
SOI_SUB --> P_MIS_RH[P-Type Rad-Hard MISFET]
N_MIS_RH --> N_GIF_RH[First Gate Insulating Film (Rad-Hard SiO2/Al2O3)]
N_GIF_RH --> N_FGE_RH[First Gate Electrode (Pt/W/TiN)]
P_MIS_RH --> P_GIF_RH[Second Gate Insulating Film (Rad-Hard SiO2/Al2O3)]
P_GIF_RH --> P_SGE_RH[Second Gate Electrode (Pt/W/TiN)]
N_FGE_RH -- side covered by --> RH_INS[Radiation-Hardened Insulating Film (Dense Si3N4)]
P_SGE_RH -- side covered by --> RH_INS
RH_INS -- not on top --> N_FGE_RH_TOP
RH_INS -- not on top --> P_SGE_RH_TOP
end
4. Integration with Emerging Tech
Derivative 4.1: AI-Optimized Adaptive Gate Work Function Control (Post-Fabrication)
Enabling Description:
This derivative integrates AI into the manufacturing method (Claim 11/12) for post-fabrication optimization of gate work functions. After the initial formation of the dual-metal gates, an additional, extremely thin "tuning layer" (e.g., a few atomic layers of a specific metal or metal oxide) is deposited over the exposed gate electrodes (Claim 1), effectively becoming part of the "second metal film" or "conductive film." AI algorithms, analyzing real-time electrical performance data from test structures on the wafer, would then dictate precise, localized annealing or plasma treatments (e.g., ion implantation at very low doses, or laser annealing) to subtly alter the work function of this tuning layer. This process allows for fine-grained adjustment of threshold voltages across the wafer, compensating for process variations or tailoring performance for specific application bins. The manufacturing method (Claim 11) would add a step (f) where the AI-driven tuning is performed on the exposed gate electrodes before final passivation.
sequenceDiagram
participant FAB as Fabrication Line
participant AI as AI Optimization System
participant WAFER as Semiconductor Wafer
FAB->>WAFER: Form Gate Stacks (Claims 11/12 steps a-e)
FAB->>WAFER: Deposit Ultra-thin Tuning Layer (post-Claim 11/12)
WAFER->>FAB: Electrical Test Data
FAB->>AI: Send Test Data for Analysis
AI->>AI: Analyze performance, identify VT drift
AI->>AI: Calculate optimal localized tuning parameters
AI->>FAB: Send Tuning Parameters (e.g., laser pulse, dose)
FAB->>WAFER: Apply Localized Post-Fab Treatment
WAFER->>FAB: Re-test (optional)
FAB->>WAFER: Final Passivation
Derivative 4.2: IoT-Enabled Environmental Sensor with Integrated Power Management
Enabling Description:
This derivative adapts the semiconductor device (Claim 1) for deployment in distributed IoT environmental sensing nodes. The dual-metal gate MISFETs are designed for ultra-low power consumption, perhaps by optimizing the gate stack materials (first and second metal films, Claim 1) for lower leakage currents and reduced operating voltages, possibly using extreme high-k dielectrics. The manufacturing method (Claim 11) ensures tight control over channel doping and gate length to achieve minimal off-state current. Crucially, the power management unit (PMU) for the IoT sensor, including rectifiers and voltage regulators, is integrated onto the same chip using additional MISFETs derived from the same fabrication flow. The "insulating film" (Claim 1) around the gate electrodes is optimized not only for isolation but also for thermal dissipation in self-contained, potentially hermetically sealed, IoT packages. The device includes a small, integrated microcontroller and RF transceiver for transmitting sensor data (e.g., temperature, humidity, gas concentration) to a network.
graph TD
subgraph IoT Sensor Node (Claim 1)
SUB[Si Substrate] --> PMU_FETS[Integrated Power Management MISFETs]
SUB --> SENS_FETS[Sensing Array MISFETs]
SUB --> RF_FETS[RF Transceiver MISFETs]
SUB --> MCU_FETS[Microcontroller Logic MISFETs]
PMU_FETS -- utilize --> DUAL_GATES[Dual-Metal Gates (Ultra-Low Power Optimized)]
SENS_FETS -- utilize --> DUAL_GATES
RF_FETS -- utilize --> DUAL_GATES
MCU_FETS -- utilize --> DUAL_GATES
DUAL_GATES -- encapsulated by --> ENV_INS[Environmental Sealing Insulating Film]
ENV_INS -- provides --> THERMAL_DISSIPATION[Thermal Dissipation]
SENS_FETS -- provide data to --> MCU_FETS
MCU_FETS -- transmits via --> RF_FETS
end
5. The "Inverse" or Failure Mode
Derivative 5.1: Self-Healing Gate Dielectric for Enhanced Reliability
Enabling Description:
This inverse mode derivative (Claim 1) focuses on a "fail-safe" or "self-healing" mechanism for the gate dielectric. The first and second gate insulating films are composed of a multi-layer stack where one or more layers are engineered to undergo a self-repairing process in response to localized dielectric breakdown. For example, a middle layer could contain embedded nanoparticles that, upon breakdown, migrate or fuse to re-insulate the damaged area, or a reversible phase change material could be incorporated. The manufacturing method (Claim 11/12) would involve precise deposition techniques for these multi-layer dielectrics, possibly involving atomic layer deposition (ALD) of complex oxides or nitrides with specific dopants. The dual-metal gate electrodes (first and second metal films) would be selected for their chemical compatibility with the self-healing layers, ensuring that the repair mechanism does not adversely affect work function. The surrounding insulating film would maintain its integrity during any localized healing event.
stateDiagram-v2
[*] --> Healthy
Healthy --> Stress[Electrical Stress/Defect]
Stress --> Local_Breakdown[Localized Dielectric Breakdown]
Local_Breakdown --> Self_Repair[Self-Repairing Layer Activation]
Self_Repair --> Heal_Complete[Healing Complete]
Heal_Complete --> Healthy
Self_Repair --> Permanent_Failure[Permanent Failure (if repair fails)]
Permanent_Failure --> [*]
Derivative 5.2: Inherently Current-Limiting MISFETs for Overload Protection
Enabling Description:
This derivative focuses on designing the MISFETs (Claim 1) to inherently limit current during an overload event, preventing catastrophic failure or damage to other circuit components. This is achieved by engineering the channel region (active regions) and gate structure such that under excessive drain current or voltage conditions, a controlled, reversible degradation or characteristic shift occurs. For instance, the gate stack (gate insulating film, first/second metal films) could incorporate a material that exhibits a controlled, self-limiting increase in resistance or a reversible punch-through characteristic under extreme bias, effectively increasing the channel resistance and limiting current flow. The manufacturing method (Claim 11/12) would precisely control the stoichiometry or crystal structure of specific layers within the gate stack or channel. This could involve using amorphous or nanocrystalline materials in the gate electrode or gate dielectric that have predictable, non-catastrophic responses to overstress. The external insulating film plays a role in isolating the device and managing localized heat generated during current limiting.
flowchart TD
A[Normal Operation] --> B{Overload Event Detected?};
B -- Yes --> C[Channel Current Exceeds Threshold];
C --> D[Gate Stack Material Response (e.g., Resistivity Increase)];
D --> E[Self-Limiting Current Flow];
E --> F{Overload Resolved?};
F -- Yes --> G[Material Reverts to Normal State];
G --> A;
F -- No --> H[Sustained Current Limiting];
H --> I[Safe Shutdown/System Intervention];
B -- No --> A;
Combination Prior Art Scenarios
Here are at least three scenarios combining US Patent 8,198,686 with existing open-source standards to create prior art.
1. Integration with RISC-V Open-Source Instruction Set Architecture (ISA) for Low-Power Microcontrollers
Enabling Description:
The dual-metal gate MISFET technology described in US Patent 8,198,686, enabling high-precision gate electrodes and reduced isolation region width, can be directly applied to the manufacturing of energy-efficient RISC-V based microcontrollers. Specifically, the n-type and p-type MISFETs with optimized work functions, as fabricated by the method in Claim 11, would form the core logic cells and memory arrays of a RISC-V processor. The miniaturization achieved by the patent's techniques (e.g., reduced isolation region width Wnp, as discussed in the patent's detailed description) directly translates to smaller die sizes for RISC-V cores. The ability to precisely control the work function of the gate electrodes is critical for tailoring the threshold voltages of the different transistors (n-type and p-type) within the RISC-V core, allowing for operation at ultra-low voltages and minimizing static power consumption, a key design goal for many RISC-V implementations. The open-source nature of RISC-V enables widespread adoption and further optimization of such silicon implementations.
Combination Prior Art: US8198686B2 combined with the RISC-V ISA (e.g., RV32I base integer instruction set).
URL: https://riscv.org/
2. CMOS Image Sensor Pixels utilizing Dual-Metal Gate Transistors for Enhanced Readout
Enabling Description:
The advanced dual-metal gate MISFET structures of US Patent 8,198,686 can be integrated into the pixel architecture of Complementary Metal-Oxide-Semiconductor (CMOS) image sensors, which often follow industry-standard pixel designs and interfaces. The precise control over threshold voltages offered by the different metal gate materials (e.g., the second metal film for n-type and first metal film plus conductive film for p-type in Claim 1) can be utilized for optimizing the performance of the in-pixel transistors, such as the transfer gate, reset gate, source follower, and row select transistors. For example, a finely tuned n-type MISFET (using the second metal film) as a transfer gate can improve charge transfer efficiency and reduce lag. The reduced isolation region width (Claim 1) allows for higher pixel density and smaller pixel pitch, leading to higher resolution image sensors. This application is particularly relevant for standard CMOS image sensor designs adhering to common interfaces and data protocols for readout.
Combination Prior Art: US8198686B2 combined with IEEE 1857.1 (Standard for Interfacing a Sensor to a Digital System) or common CMOS image sensor pixel architectures (e.g., 4T active pixel sensor).
URL: https://standards.ieee.org/standard/1857_1-2016.html
3. High-Performance Computing (HPC) Interconnect Transistors with FinFET-like Dual-Metal Gates
Enabling Description:
The methods for forming high-precision gate electrodes with reduced isolation regions, as described in US Patent 8,198,686 (Claims 11 and 12), can be adapted to fabricate advanced FinFET or Gate-All-Around (GAA) structures essential for high-performance computing (HPC) interconnects. While the patent explicitly discusses lateral single-gate IGFETs, the core principle of replacing dummy gates with precisely tuned dual-metal gates can be extended to multi-gate devices. For HPC applications, especially in processors adhering to open standards for interconnects (like PCIe or CXL), the ability to tightly control the work function of both n-type and p-type transistors (Claim 1) is crucial for achieving high switching speeds and minimizing latency. The 'first recess' and 'second recess' formation steps (Claim 11, step d) and the subsequent metal filling (Claim 11, step e) could be directly applied to the trenches around a fin structure, allowing for separate work function metals for n-FinFETs and p-FinFETs. The overall miniaturization enables denser integration of logic for faster data transfer within HPC systems.
Combination Prior Art: US8198686B2 combined with the PCI Express (PCIe) standard (e.g., PCIe 5.0 or 6.0) or Compute Express Link (CXL) standard, which define physical layer electrical and timing requirements.
URL: https://pcisig.com/specifications/pcie
URL: https://www.computeexpresslink.org/
Citations:
https://riscv.org/
https://standards.ieee.org/standard/1857_1-2016.html
https://pcisig.com/specifications/pcie
https://www.computeexpresslink.org/
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