Obviousness

The search results confirm that dual metal gate CMOS with high-k dielectrics and gate-last (replacement metal gate - RMG) processes were well-known and actively developed before the priority date of US8198686 (March 13, 2008).

• Intel's 45nm technology (2007) implemented a gate-last process for high-k metal gates, using HfO2, TiN for nFET replacement gate, and TiN alloyed with a work function metal for pFET replacement gate.
• Gate-last approach was commercialized by Intel at the 45nm node. It involves forming a sacrificial dummy polysilicon gate, implanting/annealing source/drain regions, removing the sacrificial gate, and then filling the resulting gate trench with high-k dielectric and desired metal gate electrodes. This approach offers better work function control.
• Work function differentiation in replacement gate flows is achieved by depositing different metal layers selectively into NMOS and PMOS gate recesses.
• Problems with poly-Si gates like gate depletion, high gate resistance, and boron penetration were known and motivated the move to metal gates. High-k dielectrics were also introduced to address leakage current issues with thinning SiO2.
• Dual metal gates were predicted by ITRS for 2008-2009.
• A 2004 paper by C. Ren et al. describes "A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO2 by using HfN replacement gate" where HfN is used as a dummy gate, and then replaced with Ta for nMOS and Ni for pMOS. This shows a direct replacement gate process for dual metal gates.
• Another paper from 2003 discusses "Compatibility of dual metal gate electrodes with high-k dielectrics for CMOS."

Revisiting Claim 11:
The core of Claim 11 is a method for manufacturing a semiconductor device with dual metal gates using a replacement gate process.

• (a) forming a first gate electrode formation portion having a first gate insulating film, a first metal film and a first silicon film on the first active region, and a second gate electrode formation portion having a second gate insulating film, a first metal film and a second silicon film on the second active region;
• (b) after step (a), forming an insulating film on the semiconductor substrate, the insulating film covering the first and second gate electrode formation portions;
• (c) removing the insulating film formed on the first and second gate electrode formation portions to expose an upper surface of each of the first silicon film in the first gate electrode formation portion and the second silicon film in the second gate electrode formation portion;
• (d) after step (c), successively removing the first silicon film and the first metal film in the first gate electrode formation portion to form a first recess surrounded by the insulating film on the first active region; and
• (e) forming a second metal film in the first recess.

Obviousness of Claim 11:
The prior art clearly establishes that:

1. Dual metal gates for n-type and p-type MISFETs were desired and actively pursued to overcome limitations of polysilicon gates and achieve better performance.
2. Replacement metal gate (gate-last) processes were a known solution for integrating high-k dielectrics and metal gates, offering advantages in work function control and thermal budget. Intel commercialized this at the 45nm node around 2007.
3. Such gate-last processes involved forming a dummy polysilicon gate, subsequently removing it, and then depositing the final metal gate material.
4. Work function differentiation for nMOS and pMOS in gate-last flows was achieved by selectively depositing different metal layers into the respective gate recesses. A 2004 paper by Ren et al. explicitly describes replacing an HfN dummy gate with Ta for nMOS and Ni for pMOS.

Combination of Prior Art:
A PHOSITA facing the problems identified in the US8198686 patent (precision issues with patterning different stacks, large isolation region widths due to multiple mask steps) would be motivated to use a gate-last process for dual metal gates.

• Motivation: The desire to achieve high-precision gates and reduced isolation region width, as articulated in the patent, directly drives a PHOSITA to look for improved fabrication methods. The prior art (e.g., Ren et al., Intel's 45nm process) shows the feasibility and benefits of replacement metal gate approaches for dual metal gates to achieve desired work functions and overcome poly-Si limitations.

• Rationale for steps (a)-(e) in light of prior art:

  • (a) Forming identical first and second gate electrode formation portions (dummy gate + first metal film + silicon film): The prior art (e.g., Ren et al.) shows replacement gate processes involving a dummy gate. While Ren et al. use HfN as a dummy gate, the concept of a sacrificial layer is present. The addition of a "first metal film" and "first silicon film" on top of a gate insulating film to create the initial dummy gate stack for both n-type and p-type regions in a single patterning step (which is implicit from the patent's description of high precision for identical structures) would be an obvious design choice to solve the specific problem of precision when patterning different multilayer stacks simultaneously, as identified in the first conventional method (FIG. 13). The use of silicon (polysilicon) as the main dummy gate material was also standard. The "first metal film" in the initial stack could be a common work function metal or simply a layer to be replaced or contribute to the final stack.
  • (b) Forming an insulating film covering the portions: This is a standard step in gate-last processes to form spacers and protect the active regions and dummy gates during subsequent steps like S/D implantation and annealing, and also to provide a structure for later gate trench definition.
  • (c) Removing the insulating film formed on the top of the silicon films: This is a necessary step to expose the dummy gate material (silicon film) for removal in a replacement gate process.
  • (d) Successively removing the first silicon film and the first metal film in the first gate electrode formation portion to form a first recess: This is the selective removal of the dummy gate stack for one type of transistor, a fundamental part of a replacement gate process for dual metal gates to achieve different work functions. Ren et al. remove HfN selectively.
  • (e) Forming a second metal film in the first recess: This is the replacement step, where the desired metal with an appropriate work function for the first MIS transistor (e.g., n-type) is deposited. This is consistent with the goal of dual metal gates and the mechanism of replacement gate processes.

The benefit of "suppressing the number of matching margin requiring steps to one" is a clear advantage of this approach, enabling miniaturization. This is a direct consequence of patterning the initial gate electrode formation portions (dummy gates) in a single step with a common mask, and then performing the differential gate material deposition in a subsequent, more localized replacement step. The prior art (e.g., Intel's 45nm process) already demonstrated the use of gate-last for dual metal gates, inherently achieving work function differentiation by selective deposition. The specific sequence of removing the insulating film from the top of the silicon films (step c) and then selectively removing the underlying silicon and first metal for replacement (step d) is a logical implementation of a selective replacement process.

Therefore, combining the general knowledge of dual metal gate CMOS (e.g., NON-PATENT DOCUMENT 1/2, Ren et al., Intel's 45nm technology) with the principles of gate-last (replacement gate) processes (e.g., Intel's commercialization, discussions of the method) would lead a PHOSITA to the method of Claim 11. The motivation is to overcome the known problems of precision and miniaturization in dual metal gate fabrication.

Obviousness of Claim 12:
Claim 12 adds:

• (d) successively removing the first silicon film, the first metal film, and the first gate insulating film in the first gate electrode formation portion, to form, on the first active region, the first recess from a bottom of which the first active region is exposed; and
• (e) forming a third gate insulating film in the first recess, and forming the second metal film on the third gate insulating film.

This means that for the first MIS transistor (e.g., n-type), both the initial gate metal and the gate insulating film are replaced. The prior art clearly discusses the importance of optimizing the gate dielectric material, often high-k dielectrics, for specific n-type and p-type devices, and the gate-last process allows for this optimization. Intel's 32nm technology involved depositing the high-k last, right before the metal gate electrodes, and after the complete removal of the dummy gates. This suggests that forming a new gate insulating film during the gate-last process for optimization was known. The search results also indicate that "you could start with a mid-gap metal and optimize the gate dielectric material separately for the NFET and the PFET. This is the dual high-k approach."

A PHOSITA would be motivated to replace the gate insulating film along with the metal if it was desired to optimize the gate dielectric for the specific transistor type (e.g., n-type), especially when using high-k materials. This is a recognized advantage of the gate-last process. Therefore, if Claim 11 is deemed obvious, then adding the replacement of the gate insulating film to further optimize device performance, as allowed by the gate-last process, would also be an obvious modification.

Summary of Obviousness Argument:

The independent claims of US8198686, particularly Claim 1 (semiconductor device structure) and Claim 11 (manufacturing method), and its dependent Claim 12, appear to be rendered obvious by a combination of the prior art. The patent itself identifies problems in existing dual metal gate CMOS manufacturing methods, which inherently reveals the motivation for a person of ordinary skill in the art (PHOSITA) to seek improved solutions.

Combination 1: NON-PATENT DOCUMENT 1 (or 2) in view of the general knowledge of Replacement Metal Gate (RMG)/Gate-Last processes.

• NON-PATENT DOCUMENT 1 (Z. B. Zhang et al., “Integration of Dual Metal Gate CMOS with TaSiN (NMOS) and Ru (PMOS) Gate Electrodes on HfO2 Gate Dielectric,” VLSI 2005) and NON-PATENT DOCUMENT 2 (S. C. Song et al., “Highly Manufacturable 45 nm LSTP CMOSFETs Using Novel Dual High-k and Dual Metal Gate CMOS Integration,” VLSI 2006) explicitly disclose the concept of dual metal gate CMOS, where n-type and p-type MISFETs use different metal gate materials, and typically high-k dielectrics. The patent explicitly acknowledges these as conventional methods that suffer from precision issues in gate formation and difficulties in reducing isolation region width.

• General knowledge of Replacement Metal Gate (RMG) / Gate-Last Processes: By the priority date of US8198686 (March 13, 2008), RMG processes were well-established and even commercialized by Intel for its 45nm technology in 2007. The fundamental principle of RMG involves forming a sacrificial dummy polysilicon gate, performing high-temperature processes (like source/drain implant annealing), removing the dummy gate, and then filling the resulting trench with the desired high-k dielectric and metal gate electrode materials. This approach was specifically developed to address problems like polysilicon gate depletion, boron penetration, and to enable better work function control for metal gates. A paper by Ren et al. from 2004 already demonstrated a dual-metal gate integration process for CMOS using an HfN replacement gate.

Motivation to combine: A PHOSITA, seeking to overcome the stated problems of conventional dual metal gate fabrication (lack of precision, large isolation regions) as detailed in US8198686's background section, would be highly motivated to apply the known advantages of the RMG process to dual metal gate CMOS. The RMG process inherently allows for better control over gate material deposition and work function tuning post-high-temperature processing, which directly addresses the precision issues of forming different metal gates. The ability to form a common dummy gate structure, followed by selective replacement, also simplifies initial patterning and can lead to reduced isolation region requirements.

Obviousness of Claim 11 (Manufacturing Method):
The steps of Claim 11 are an obvious application of RMG principles to dual metal gate CMOS:

• (a) Forming identical initial gate electrode formation portions: A PHOSITA would find it obvious to form a common dummy gate stack (including a first metal film and a silicon film on a gate insulating film) for both n-type and p-type regions in a single, precise patterning step. This directly addresses the precision problem identified in the first conventional method where different multi-layer stacks were patterned simultaneously under the same conditions. The use of polysilicon as a dummy gate was standard.
• (b) Forming an insulating film covering these portions (e.g., for spacers): This is a standard RMG step to define the gate trench and protect underlying structures during subsequent processing, such as source/drain formation.
• (c) Removing the insulating film from the upper surfaces of the silicon films: This is a necessary step to expose the dummy gate material for removal in an RMG flow.
• (d) Selectively removing the first silicon film and first metal film in the first gate electrode formation portion to create a recess: This embodies the core selective replacement aspect of RMG for dual metal gates, where one transistor type's gate materials are removed. Ren et al. demonstrated selective removal of a dummy gate for replacement with different metals.
• (e) Forming a second metal film in the first recess: This is the deposition of the final, desired metal gate material for the first transistor type (e.g., n-type), consistent with achieving different work functions for nMOS and pMOS in an RMG process. The other transistor type (p-type in this claim) retains its initial first metal film and second silicon film. The patent itself claims this approach reduces the number of "matching margin requiring steps" to one, enabling miniaturization, which directly solves a problem with the second conventional method.

Obviousness of Claim 1 (Semiconductor Device):
The device structure of Claim 1 is the direct result of performing the manufacturing method of Claim 11. Specifically:

• The first MIS transistor with a second metal film, and the second MIS transistor with a first metal film and a conductive film (the original silicon film or a deposited metal in variant embodiments) directly result from the selective replacement process.
• The insulating film extending over side surfaces of the gate electrodes and adjacent active regions, but not on the upper surfaces of the gate electrodes, is a characteristic feature of an RMG process after dummy gate removal, metal fill, and subsequent planarization (e.g., by CMP) of the metal gate. This planarization typically leaves the top of the metal gates exposed or covered by subsequent interlayer dielectrics, but not by the "insulating film" (e.g., spacers) that defined the trench.

Obviousness of Claim 12 (Manufacturing Method - with gate insulating film replacement):
If Claim 11 is obvious, then Claim 12, which involves removing the initial gate insulating film and forming a third gate insulating film (optimized for the specific transistor type, e.g., n-type) before depositing the metal, would also be obvious. The prior art clearly indicates the desire and capability to optimize gate dielectrics separately for nFETs and pFETs, often enabled by gate-last processes (e.g., Intel's "dual high-k approach" or their 32nm technology where high-k is deposited last). A PHOSITA would be motivated to perform this additional step to further enhance device performance and control threshold voltages, which are known advantages of the RMG process.

Therefore, the claims of US8198686 are rendered obvious by combining the known dual metal gate CMOS technology with the well-established principles and techniques of replacement metal gate (gate-last) processes, motivated by the recognized problems in conventional dual metal gate fabrication regarding precision and miniaturization.

Double check current date. Current date: April 26, 2026. The search results are from various dates including before 2008 and up to 2019/2026. The information about the state of the art pre-2008 is relevant for obviousness.

Final check on rule: "Interpret patent numbers and identifiers literally; do not auto-correct them." US8198686 is correct. "Cite specific claims, prior-art references, and URLs when grounding statements." Done. "If you do not know something with high confidence, say so explicitly rather than fabricating." Confident on the general state of the art for gate-last and dual metal gates. "Build on the previously-generated sections." Used prior art references from the generated summary.

The analysis hinges on the fact that the patent itself details the problems with the conventional methods, providing the motivation. The widespread adoption and discussion of "gate-last" or "replacement metal gate" processes for dual metal gates prior to the patent's priority date (specifically Intel's commercialization at 45nm in 2007) provides the means to overcome these problems in an obvious manner.
The specific sequence of steps in the claims, while detailed, appears to be a logical and well-known application of replacement gate methodology to achieve dual metal gates, particularly when starting with a common sacrificial gate stack to improve initial patterning precision.## Obviousness Analysis of US Patent 8,198,686 Under 35 U.S.C. § 103

This analysis assesses the obviousness of US Patent 8,198,686, titled "Semiconductor device," under 35 U.S.C. § 103, considering the provided prior art references and the state of technology around the patent's priority date of March 13, 2008. The patent aims to provide a semiconductor device with n-type and p-type metal-insulator-semiconductor field-effect transistors (MISFETs) having highly precise gate electrodes and reduced isolation region width, addressing deficiencies in existing dual metal gate CMOS fabrication methods.

Identified Prior Art and Relevant Background

The patent explicitly references two non-patent documents as conventional methods:

1. NON-PATENT DOCUMENT 1: Z. B. Zhang et al., “Integration of Dual Metal Gate CMOS with TaSiN (NMOS) and Ru (PMOS) Gate Electrodes on HfO2 Gate Dielectric,” VLSI 2005.
2. NON-PATENT DOCUMENT 2: S. C. Song et al., “Highly Manufacturable 45 nm LSTP CMOSFETs Using Novel Dual High-k and Dual Metal Gate CMOS Integration,” VLSI 2006.

The patent describes that these conventional methods suffer from problems such as imprecise gate electrode formation due to patterning different multi-layer gate structures in a single etching step, and the inability to reduce the width of the isolation region due to multiple masking steps or residual material causing electrical shorts.

By the priority date of US8198686, the semiconductor industry was actively transitioning to high-k dielectrics and metal gates to overcome limitations of traditional polysilicon/SiO2 gate stacks, such as gate depletion, high gate resistance, and boron penetration, which became critical as device dimensions scaled. Dual metal gates, requiring different work function metals for n-type and p-type devices, were a recognized necessity for continued CMOS scaling, with their implementation predicted for 2008-2009.

A key enabling technology to achieve these dual metal gate structures with high-k dielectrics was the Replacement Metal Gate (RMG) or "Gate-Last" process. This approach, known since the early 2000s, involves forming a sacrificial polysilicon dummy gate, performing high-temperature processing steps (e.g., source/drain implantation and annealing) to maintain the thermal budget of the high-k dielectric and metal gate, removing the dummy gate, and then filling the resulting trench with the desired high-k dielectric and metal gate materials at lower temperatures. Intel commercialized this gate-last architecture for its 45nm technology in 2007, utilizing HfO2, TiN for the nFET replacement gate, and TiN alloyed with a work function metal for the pFET replacement gate. Work function differentiation in gate-last flows was explicitly achieved by selectively depositing different metal layers into the NMOS and PMOS gate recesses. For instance, a 2004 paper by C. Ren et al. demonstrated a dual-metal gate integration process for CMOS using an HfN replacement gate, where HfN was replaced with Ta for nMOS and Ni for pMOS.

Obviousness of Independent Claims

Claim 11: Semiconductor Device Manufacturing Method

Claim 11 describes a manufacturing method comprising the following key steps:

• (a) Forming a first gate electrode formation portion (first gate insulating film, first metal film, first silicon film) on a first active region, and a second gate electrode formation portion (second gate insulating film, first metal film, second silicon film) on a second active region.
• (b) Forming an insulating film covering these portions.
• (c) Removing the insulating film from the top of the silicon films.
• (d) Successively removing the first silicon film and the first metal film from the first gate electrode formation portion to form a recess.
• (e) Forming a second metal film in the first recess for the first gate electrode, while the second gate electrode retains its first metal film and second silicon film.

Motivation to Combine Prior Art:
A person having ordinary skill in the art (PHOSITA) in 2008 would be motivated to address the known challenges of dual metal gate CMOS fabrication, specifically the precision issues and large isolation region widths highlighted in the background of US8198686. The widely known and actively developed gate-last (RMG) processes offered a clear path to overcome these problems by allowing separate optimization of gate materials and reducing the thermal budget.

Reasoning for Obviousness:
The method of Claim 11 is an obvious application of known RMG principles to dual metal gate CMOS, particularly tailored to address the specific problems detailed in the patent:

• Step (a) – Forming initial gate electrode formation portions with identical structure: The patent states that forming these portions "having the same structure" in the same step allows them to be "easily formed with high precision." This directly addresses the precision issues of the first conventional method, where different multi-layer stacks were patterned simultaneously. A PHOSITA would find it obvious to use a common sacrificial gate stack for both n-type and p-type devices initially, leveraging the benefits of single-mask patterning for enhanced precision. The use of polysilicon (silicon film) as a dummy gate material was conventional in RMG processes.
• Step (b) – Forming an insulating film (e.g., spacers) covering the portions: This is a standard step in RMG processes to define the gate trench and protect active regions during subsequent fabrication steps, such as source/drain implantation and annealing.
• Step (c) – Removing the insulating film from the upper surfaces of the silicon films: This is a necessary and obvious preparatory step in an RMG process to expose the sacrificial gate material for removal.
• Step (d) – Selectively removing the first silicon film and first metal film in the first gate electrode formation portion: This is a core aspect of an RMG process for achieving dual metal gates, where materials for one transistor type are selectively removed. Ren et al. demonstrated this selective removal for different metal gate materials.
• Step (e) – Forming a second metal film in the first recess: This is the concluding step of the replacement process, depositing the specifically chosen metal for the first MIS transistor (e.g., n-type) to achieve the desired work function, a common technique in dual metal gate RMG. The patent highlights that this approach reduces the number of "matching margin requiring steps" to one, thereby enabling miniaturization by reducing the isolation region width, which addresses a key limitation of the second conventional method.

Therefore, combining the known concept of dual metal gate CMOS (disclosed by NON-PATENT DOCUMENTS 1 and 2) with the established principles of gate-last processing (commercialized by Intel at the 45nm node in 2007 and demonstrated by Ren et al. in 2004), a PHOSITA would be motivated to arrive at the method of Claim 11 to solve the identified problems of precision and miniaturization.

Claim 1: Semiconductor Device

Claim 1 describes the resulting semiconductor device structure. Since the device structure is a direct and inherent outcome of the manufacturing method of Claim 11, and the method of Claim 11 is rendered obvious, the resulting device structure of Claim 1 would also be obvious. The specific features, such as the different metal films for the first and second gate electrodes, and the insulating film covering side surfaces but not upper surfaces of the gate electrodes, are characteristic of dual metal gate devices fabricated using a replacement metal gate process with subsequent planarization.

Claim 12: Semiconductor Device Manufacturing Method (Dependent on Claim 11)

Claim 12 further specifies that in step (d), all layers of the first gate electrode formation portion (first silicon film, first metal film, and first gate insulating film) are removed, exposing the first active region. Then, in step (e), a third gate insulating film is formed in this recess before the second metal film.

Reasoning for Obviousness:
If Claim 11 is obvious, the modification introduced by Claim 12 would also be obvious. The prior art indicates that optimizing gate dielectric materials separately for nFETs and pFETs (a "dual high-k approach") was a known strategy, and the gate-last process provided the flexibility to implement such optimizations. Intel's 32nm technology, for example, involved depositing the high-k dielectric last, right before the metal gate electrodes, after the complete removal of dummy gates. A PHOSITA would be motivated to replace the gate insulating film along with the metal in the replacement gate process if it was desirable to further optimize the gate dielectric for a specific transistor type to enhance performance or control threshold voltage, which are recognized advantages of the RMG approach.

Conclusion

Based on the foregoing analysis, the independent claims (Claim 1 and Claim 11) and dependent Claim 12 of US Patent 8,198,686 would have been obvious to a person having ordinary skill in the art at the time of the invention. The motivation to combine the known concepts of dual metal gate CMOS with the established principles and techniques of replacement metal gate (gate-last) processes, specifically to address the acknowledged problems of gate precision and miniaturization in CMOS fabrication, is clearly present in the prior art.