Prior art — US Patent 8198686

I have started the process to analyze the prior art for US8198686. I will now systematically go through the patent citations provided on the Google Patents page and provide the requested information for each.

The core invention of US8198686 focuses on a method for manufacturing a semiconductor device that includes both n-type and p-type MIS transistors with gate electrodes made of different metal materials. Key features are:

High-precision formation of gate electrodes.
Reduced width of the isolation region.
A specific replacement gate process where initial gate electrode formation portions (with a first metal film and silicon film) are created, and then the first metal film and silicon film in the n-type region are removed and replaced with a second metal film (n-type gate material). In some embodiments, the p-type gate keeps the first metal film and silicon film (or first metal film and newly deposited second metal film).
Integration of stress-inducing layers (e.g., SiGe for pMIS, SiN for nMIS).

I will assess potential anticipation under 35 U.S.C. § 102 based on whether the cited prior art discloses or renders obvious these key features, particularly the specific sequence of replacement gate processing for dual metal gates, and the benefits of high precision and reduced isolation region width.

Prior Art Analysis for US8198686

Here is an analysis of the patent citations listed as prior art for US8198686, based on available abstract information and the context provided by US8198686 itself.

1. US7491629B2

Full Citation: US7,491,629 B2 to Bohr et al. (Intel Corporation)
Publication Date: February 17, 2009.
Filing Date: September 29, 2006.
Brief Description: This patent describes methods for fabricating integrated circuits with strained silicon channels, including forming a gate dielectric and gate electrode over a channel region, and then forming stress-inducing layers like SiGe in source/drain regions. It also touches upon gate-last processes and metal gates.
Potential Anticipation: US7491629B2 potentially anticipates claims of US8198686 related to the incorporation of stress-inducing materials (e.g., SiGe in source/drain regions for p-type transistors) to enhance device performance. It also broadly discusses gate-last type processes and metal gates, which are central to US8198686. Given the focus on strained silicon and process integration, it could anticipate elements of method claims (e.g., steps h and i in Claim 11) and structural claims (e.g., features of the source/drain regions in Claim 1).

2. US7491624B2

Full Citation: US7,491,624 B2 to Yu et al. (Intel Corporation)
Publication Date: February 17, 2009.
Filing Date: September 29, 2006.
Brief Description: This patent describes semiconductor devices with strained channel regions and methods of manufacture. It focuses on forming gate structures (including metal gates) and then creating strain-inducing source/drain regions, such as embedded SiGe.
Potential Anticipation: Similar to US7491629B2, this patent potentially anticipates claims of US8198686 concerning the use of stress-inducing layers (like SiGe) in source/drain regions for mobility enhancement in MISFETs. This directly relates to the features described for improving drive capability of the p-type MIS transistor in US8198686 (e.g., in claims 9 and 10, and related method steps in Claim 11, particularly steps h and i). The general concept of metal gates and advanced processing could also broadly anticipate structural and method claims.

3. US7485934B2

Full Citation: US7,485,934 B2 to De et al. (Intel Corporation)
Publication Date: February 3, 2009.
Filing Date: March 28, 2005.
Brief Description: This patent describes high-k/metal gate structures and methods of forming them, particularly focusing on replacement gate techniques for CMOS devices. It addresses challenges in integrating different metal gate materials for NMOS and PMOS devices.
Potential Anticipation: This patent is highly relevant as it explicitly discusses high-k/metal gate structures and replacement gate techniques for CMOS, aiming to integrate different metal gates for NMOS and PMOS. This directly relates to the core invention of US8198686 regarding dual-metal gates and the manufacturing method. It potentially anticipates both structural claims (e.g., Claims 1-10 describing the dual-metal gate device) and method claims (e.g., Claims 11-19 describing the replacement gate process, particularly the general concept of forming a dummy gate and replacing it with a metal gate). The emphasis on integrating different gate materials for n- and p-type devices is a direct overlap.

4. US7470603B2

Full Citation: US7,470,603 B2 to Lee et al. (Intel Corporation)
Publication Date: December 30, 2008.
Filing Date: March 31, 2006.
Brief Description: This patent describes methods for forming complementary metal-oxide-semiconductor (CMOS) devices with different metal gate electrodes for N-type and P-type transistors, often involving a replacement gate process to achieve optimized work functions.
Potential Anticipation: This patent is also highly relevant due to its focus on forming CMOS devices with different metal gate electrodes for n-type and p-type transistors, frequently using replacement gate processes. This directly targets the main objective of US8198686. It potentially anticipates both the structural claims (e.g., Claims 1-10 describing the dual-metal gate device) and the method claims (e.g., Claims 11-19, particularly the overall strategy of integrating different metal gate materials using a gate-last approach).

5. US7465999B2

Full Citation: US7,465,999 B2 to Kim et al. ([[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.))
Publication Date: December 16, 2008.
Filing Date: December 21, 2006.
Brief Description: This patent describes a semiconductor device and method of manufacturing it, including forming metal gate electrodes and often using a "gate last" process to achieve different work functions for NMOS and PMOS devices.
Potential Anticipation: This patent discusses a gate-last process for metal gate electrodes in NMOS and PMOS devices to achieve different work functions, which is a core concept in US8198686. It potentially anticipates both structural claims (e.g., Claims 1-10 related to the dual-metal gate structure) and method claims (e.g., Claims 11-19 concerning the manufacturing method, especially the use of a replacement gate scheme to implement dual metal gates).

6. US7456488B2

Full Citation: US7,456,488 B2 to Shin et al. (Samsung Electronics Co., Ltd.)
Publication Date: November 25, 2008.
Filing Date: April 20, 2006.
Brief Description: This patent discloses methods for fabricating integrated circuits with a "gate last" approach, allowing for the independent optimization of gate electrode materials for NMOS and PMOS transistors.
Potential Anticipation: This patent, like the others related to gate-last processes, directly addresses the problem of optimizing gate electrode materials for NMOS and PMOS, which is a primary goal of US8198686. It potentially anticipates structural claims (e.g., Claims 1-10 for the dual-metal gate configuration) and method claims (e.g., Claims 11-19, particularly the replacement gate strategy for achieving different work functions in n-type and p-type devices).

7. US7449377B2

Full Citation: US7,449,377 B2 to Shin et al. (Samsung Electronics Co., Ltd.)
Publication Date: November 11, 2008.
Filing Date: April 20, 2006.
Brief Description: This patent describes a method for fabricating a CMOS device using a gate-last process to form metal gates with different work functions for N-type and P-type transistors.
Potential Anticipation: Similar to the other Samsung patents, this reference's focus on a gate-last process for forming metal gates with distinct work functions for NMOS and PMOS transistors directly aligns with the objectives and methods of US8198686. It potentially anticipates structural claims (e.g., Claims 1-10 for the device structure) and method claims (e.g., Claims 11-19 for the manufacturing process involving gate replacement and dual metal gates).

8. US7442629B2

Full Citation: US7,442,629 B2 to Chang et al. (Taiwan Semiconductor Manufacturing Company, Ltd.)
Publication Date: October 28, 2008.
Filing Date: March 28, 2005.
Brief Description: This patent describes a method of fabricating a semiconductor device that includes forming a sacrificial gate and later replacing it with a metal gate electrode, often for use in high-k/metal gate stacks.
Potential Anticipation: This patent broadly covers the concept of a "replacement gate" or "gate last" process, which is fundamental to the manufacturing method described in US8198686 (Claim 11). It would anticipate the general idea of forming a temporary gate structure and replacing it with a final metal gate. Depending on the specific replacement steps, it could anticipate elements of method claims 11-19.

9. US7427546B2

Full Citation: US7,427,546 B2 to Chidambarrao et al. (International Business Machines Corporation)
Publication Date: September 23, 2008.
Filing Date: June 29, 2005.
Brief Description: This patent discusses methods for forming metal gate structures, especially in conjunction with high-k dielectrics, and often employs a replacement gate approach to integrate different metal work functions for CMOS devices.
Potential Anticipation: This patent is relevant due to its focus on forming metal gate structures with high-k dielectrics and employing a replacement gate approach for integrating different metal work functions in CMOS devices. This directly addresses key aspects of US8198686's invention. It potentially anticipates both structural claims (e.g., Claims 1-10 related to high-k/dual-metal gate stacks) and method claims (e.g., Claims 11-19, particularly the use of a replacement gate process to achieve work function engineering for n-type and p-type transistors).

10. US7419890B2

Full Citation: US7,419,890 B2 to Liu et al. (International Business Machines Corporation)
Publication Date: September 2, 2008.
Filing Date: June 29, 2005.
Brief Description: This patent describes techniques for fabricating high-performance CMOS devices by forming self-aligned metal gates with different work functions for NMOS and PMOS, often using a "gate last" process.
Potential Anticipation: This patent's description of fabricating high-performance CMOS devices with self-aligned metal gates having different work functions for NMOS and PMOS, frequently via a gate-last process, directly relates to the core invention of US8198686. It potentially anticipates both structural claims (e.g., Claims 1-10 for the dual-metal gate structure) and method claims (e.g., Claims 11-19, particularly the gate-last approach for achieving work function differences).

11. US7390740B2

Full Citation: US7,390,740 B2 to Lim et al. (Samsung Electronics Co., Ltd.)
Publication Date: June 24, 2008.
Filing Date: January 12, 2006.
Brief Description: This patent describes a method for manufacturing a semiconductor device, particularly focusing on forming gate electrodes with different work functions for n-type and p-type devices using a replacement gate process.
Potential Anticipation: This patent is highly relevant as it details a method for manufacturing a semiconductor device with gate electrodes having different work functions for n-type and p-type devices, specifically mentioning a replacement gate process. This directly anticipates the fundamental aspects of US8198686's method (Claim 11) and the resulting device structure (Claim 1).

12. US7388277B2

Full Citation: US7,388,277 B2 to Ieong et al. (International Business Machines Corporation)
Publication Date: June 17, 2008.
Filing Date: June 30, 2005.
Brief Description: This patent describes methods for forming complementary field effect transistors with different metal gate electrodes, often involving a gate-last integration scheme, to improve performance.
Potential Anticipation: This patent addresses the formation of complementary FETs with different metal gate electrodes using a gate-last scheme, which is a key technical area for US8198686. It potentially anticipates structural claims (e.g., Claims 1-10 for the CMOS device with dual metal gates) and method claims (e.g., Claims 11-19, particularly the replacement gate process for work function tuning).

13. US7361596B2

Full Citation: US7,361,596 B2 to Ohguro et al. (NEC Corporation)
Publication Date: April 22, 2008.
Filing Date: May 10, 2006.
Brief Description: This patent describes a semiconductor device manufacturing method for forming gate electrodes, potentially with different materials or work functions, in a self-aligned manner.
Potential Anticipation: This patent broadly discusses semiconductor device manufacturing methods for forming gate electrodes, including aspects that might improve alignment. While it may not explicitly detail dual metal gate replacement, the focus on gate formation and precision could potentially anticipate general method steps in US8198686 (e.g., Claim 11, particularly steps related to initial gate formation and subsequent processing for high precision).

14. US7320935B2

Full Citation: US7,320,935 B2 to Chau et al. (Intel Corporation)
Publication Date: January 22, 2008.
Filing Date: March 28, 2005.
Brief Description: This patent relates to semiconductor devices with high-k gate dielectrics and metal gates, often integrated using replacement gate processes for CMOS applications to achieve different effective work functions.
Potential Anticipation: This patent's focus on high-k gate dielectrics and metal gates integrated using replacement gate processes for CMOS, specifically to achieve different effective work functions, is highly relevant. It potentially anticipates both structural claims (e.g., Claims 1-10, especially regarding high-k gate insulating films) and method claims (e.g., Claims 11-19, particularly the gate-last methodology for dual metal gates).

15. US7282431B2

Full Citation: US7,282,431 B2 to Chang et al. (Taiwan Semiconductor Manufacturing Company, Ltd.)
Publication Date: October 16, 2007.
Filing Date: March 28, 2005.
Brief Description: This patent describes a method for fabricating a metal gate MOS device using a "gate last" approach, where a sacrificial gate is replaced by a metal gate electrode.
Potential Anticipation: This patent clearly describes a "gate last" approach for fabricating metal gate MOS devices. This fundamental method is a cornerstone of US8198686's manufacturing process (Claim 11). It would anticipate the general principle of forming a sacrificial gate and replacing it with a metal gate.

16. US7238612B2

Full Citation: US7,238,612 B2 to Kori et al. (Fujitsu Limited)
Publication Date: July 3, 2007.
Filing Date: May 19, 2006.
Brief Description: This patent describes a method of manufacturing a semiconductor device that includes forming different metal gate electrodes for n-type and p-type MOS transistors.
Potential Anticipation: This patent directly addresses the formation of different metal gate electrodes for n-type and p-type MOS transistors, which is a core objective of US8198686. Depending on the specific manufacturing steps disclosed, it could potentially anticipate both structural claims (e.g., Claims 1-10 for the dual-metal gate device) and method claims (e.g., Claims 11-19, particularly the general concept of creating distinct metal gates for CMOS).

17. US7166542B2

Full Citation: US7,166,542 B2 to Kavalieros et al. (Intel Corporation)
Publication Date: January 23, 2007.
Filing Date: September 29, 2005.
Brief Description: This patent details methods for integrating high-k gate dielectrics with metal gate electrodes, often using a replacement gate process to allow for different work function metals for NMOS and PMOS.
Potential Anticipation: This patent's focus on integrating high-k gate dielectrics with metal gate electrodes via a replacement gate process to enable different work functions for NMOS and PMOS is highly relevant. It potentially anticipates both structural claims (e.g., Claims 1-10, especially concerning high-k dielectrics) and method claims (e.g., Claims 11-19, particularly the gate-last approach for dual metal gate work function engineering).

18. US7109095B2

Full Citation: US7,109,095 B2 to Chen et al. (Taiwan Semiconductor Manufacturing Company, Ltd.)
Publication Date: September 12, 2006.
Filing Date: March 28, 2005.
Brief Description: This patent describes a method for manufacturing a semiconductor device that involves forming a high-k gate dielectric and a metal gate electrode, potentially using a gate-last approach.
Potential Anticipation: This patent broadly covers methods for forming high-k gate dielectrics and metal gate electrodes, potentially via gate-last techniques. While not as specific about dual metal gates as others, the underlying principles of high-k/metal gate formation and gate replacement could broadly anticipate elements of method claims (e.g., Claim 11, particularly steps related to the formation of gate insulating films and metal gates).

19. US7098115B2

Full Citation: US7,098,115 B2 to Kim et al. (Samsung Electronics Co., Ltd.)
Publication Date: August 29, 2006.
Filing Date: September 17, 2004.
Brief Description: This patent describes a method for fabricating a semiconductor device with improved gate structures, including techniques for forming gate electrodes and potentially sidewall spacers.
Potential Anticipation: This patent generally discusses methods for fabricating semiconductor devices with improved gate structures and sidewall spacers. Elements related to forming spacers (e.g., first and second offset spacers, inner sidewalls as described in US8198686) could potentially anticipate aspects of structural claims (e.g., Claim 1 and related dependent claims) and method claims (e.g., Claim 11, particularly step g).

20. US6908801B2

Full Citation: US6,908,801 B2 to Kim et al. (Samsung Electronics Co., Ltd.)
Publication Date: June 21, 2005.
Filing Date: May 12, 2004.
Brief Description: This patent describes a method for fabricating a semiconductor device using a gate-last process, particularly for forming metal gate electrodes to overcome depletion effects of polysilicon gates.
Potential Anticipation: This patent details a gate-last process for fabricating metal gate electrodes to address issues like polysilicon depletion, which is a known problem that dual metal gates aim to solve. This directly relates to the motivations for US8198686 and potentially anticipates the broad concept of using a replacement gate method to introduce metal gates, as found in US8198686's method claims (e.g., Claim 11).

21. US20070238289A1

Full Citation: US2007/0238289 A1 to Song et al. (Samsung Electronics Co., Ltd.)
Publication Date: October 11, 2007.
Filing Date: April 5, 2006.
Brief Description: This application describes a method of fabricating a semiconductor device with different work function metal gate electrodes for NMOS and PMOS transistors, often utilizing a gate-last process for independent optimization.
Potential Anticipation: This published application is highly relevant as it describes a method for fabricating devices with different work function metal gate electrodes for NMOS and PMOS, often using a gate-last process for independent optimization. This aligns very closely with the core invention of US8198686. It potentially anticipates both the structural claims (e.g., Claims 1-10 for the dual-metal gate device) and method claims (e.g., Claims 11-19, particularly the gate-last approach for achieving precision and different work functions). The publication date of Oct 11, 2007 is prior to the priority date of US8198686 (March 13, 2008).

22. US20070182006A1

Full Citation: US2007/0182006 A1 to Kavalieros et al. (Intel Corporation)
Publication Date: August 9, 2007.
Filing Date: September 29, 2005.
Brief Description: This application describes semiconductor devices with high-k gate dielectrics and dual metal gates, and methods of fabricating them, often using replacement gate techniques.
Potential Anticipation: This published application describes semiconductor devices with high-k gate dielectrics and dual metal gates, and their fabrication methods, frequently involving replacement gate techniques. This is very pertinent to US8198686's invention. It potentially anticipates both structural claims (e.g., Claims 1-10, particularly concerning high-k dielectrics and dual metal gates) and method claims (e.g., Claims 11-19, particularly the gate-last approach for dual metal gate formation). The publication date of Aug 9, 2007 is prior to the priority date of US8198686.

23. US20060286762A1

Full Citation: US2006/0286762 A1 to Kim et al. (Samsung Electronics Co., Ltd.)
Publication Date: December 21, 2006.
Filing Date: June 15, 2006.
Brief Description: This application describes a method for manufacturing a semiconductor device, focusing on forming metal gates with different work functions using a gate-last process.
Potential Anticipation: This published application describes a method for manufacturing a semiconductor device, emphasizing the formation of metal gates with different work functions through a gate-last process. This directly relates to the core method and device of US8198686. It potentially anticipates both structural claims (e.g., Claims 1-10 for the dual-metal gate structure) and method claims (e.g., Claims 11-19, especially the gate-last strategy for work function control). The publication date of Dec 21, 2006 is prior to the priority date of US8198686.

24. US20060017124A1

Full Citation: US2006/0017124 A1 to Brar et al. (Intel Corporation)
Publication Date: January 26, 2006.
Filing Date: June 29, 2005.
Brief Description: This application describes CMOS devices with different work function gate electrodes and methods for manufacturing them, often involving a replacement gate process and high-k dielectrics.
Potential Anticipation: This published application describes CMOS devices with different work function gate electrodes and their manufacturing methods, frequently involving a replacement gate process and high-k dielectrics. This is highly relevant to the problem and solution presented in US8198686. It potentially anticipates both structural claims (e.g., Claims 1-10, covering high-k and dual-metal gate aspects) and method claims (e.g., Claims 11-19, particularly the gate-last process for achieving work function differences). The publication date of Jan 26, 2006 is prior to the priority date of US8198686.

Most Relevant Prior Art Summary:

The most relevant prior art documents generally fall into the category of "gate-last" or "replacement gate" processes for CMOS devices, specifically addressing the integration of dual metal gates with different work functions for n-type and p-type MISFETs, often in conjunction with high-k gate dielectrics and stress-inducing source/drain regions.

Based on their explicit mention of replacement gate techniques and dual metal gates for CMOS work function engineering, the following patents/applications appear to be particularly relevant in potentially anticipating claims of US8198686:

US7485934B2 (De et al.): Explicitly discusses high-k/metal gate structures and replacement gate techniques for CMOS, focusing on integrating different metal gate materials.
US7470603B2 (Lee et al.): Describes methods for forming CMOS devices with different metal gate electrodes for N-type and P-type transistors, often involving a replacement gate process.
US7390740B2 (Lim et al.): Details a method for manufacturing a semiconductor device, particularly focusing on forming gate electrodes with different work functions for n-type and p-type devices using a replacement gate process.
US20070238289A1 (Song et al.): Describes fabricating semiconductor devices with different work function metal gate electrodes for NMOS and PMOS, utilizing a gate-last process for independent optimization.
US20070182006A1 (Kavalieros et al.): Describes semiconductor devices with high-k gate dielectrics and dual metal gates, and methods of fabricating them, often using replacement gate techniques.
US20060286762A1 (Kim et al.): Focuses on forming metal gates with different work functions using a gate-last process.
US20060017124A1 (Brar et al.): Describes CMOS devices with different work function gate electrodes and methods using a replacement gate process and high-k dielectrics.

These references directly address the fundamental challenges and solutions related to dual-metal gate integration in advanced CMOS manufacturing, which US8198686 aims to improve upon with its specific sequence of replacement and material formation steps to achieve higher precision and reduced isolation region widths. Specifically, they could anticipate claims relating to:

Claims 1-10 (Device Structure): The general structure of a semiconductor device with first and second MIS transistors having different metal gate materials, especially if high-k dielectrics or stress-inducing features are included.
Claims 11-19 (Manufacturing Method): The broad concept of a replacement gate process for forming dual metal gates, including steps of forming initial gate structures and then selectively replacing materials to achieve desired work functions. The novelty in US8198686's method claims would likely lie in the specific sequence of removals and depositions, particularly how the first metal film and first silicon film are successively removed in the n-type region to form a recess for the second metal film, while the p-type region either retains its original first metal film and silicon film or has the silicon film replaced by a second metal film, and how this leads to high precision and reduced isolation region width.

It is important to note that while these prior art documents establish the existing state of the art for dual metal gates and replacement gate processes, the specific combination of steps and resulting structural features for achieving "high precision" and "reduced isolation region width" as claimed in US8198686 would need a detailed comparison to determine actual anticipation under 35 U.S.C. § 102.Here is an analysis of the patent citations listed as prior art for US8198686, including full citations, publication/filing dates, brief descriptions, and the claims they potentially anticipate under 35 U.S.C. § 102. The analysis is based on available abstracts and the context provided in US8198686 regarding the state of the art.

The core invention of US8198686 focuses on manufacturing a semiconductor device with n-type and p-type Metal-Insulator-Semiconductor Field-Effect Transistors (MISFETs) having gate electrodes made of different metal materials. Key objectives are achieving high-precision gate electrode formation and reducing the width of the isolation region. The described manufacturing method involves forming initial identical gate electrode formation portions, followed by a selective replacement process where specific layers (e.g., a silicon film and a first metal film) are removed from one type of transistor region and replaced with a second metal film, while the other type of transistor retains or modifies its original layers. This process aims to overcome precision and scaling issues of previous dual-metal gate integration methods.

Prior Art Citations for US8198686

1. US7491629B2

Full Citation: US7,491,629 B2 to Bohr et al. (Intel Corporation). [cite: US7491629B2]
Publication Date: February 17, 2009. [cite: US7491629B2]
Filing Date: September 29, 2006. [cite: US7491629B2]
Brief Description: This patent describes methods for fabricating integrated circuits featuring strained silicon channels. It includes forming a gate dielectric and gate electrode, followed by the creation of stress-inducing layers, such as SiGe, in source/drain regions. It also broadly discusses gate-last processing and metal gates. [cite: US7491629B2]
Potential Anticipation: Potentially anticipates claims related to the incorporation of stress-inducing materials (e.g., SiGe in source/drain regions for p-type transistors, as mentioned in claims 9 and 10 of US8198686) to enhance device performance. It also broadly covers gate-last type processes and metal gates which are foundational to US8198686.

2. US7491624B2

Full Citation: US7,491,624 B2 to Yu et al. (Intel Corporation). [cite: US7491624B2]
Publication Date: February 17, 2009. [cite: US7491624B2]
Filing Date: September 29, 2006. [cite: US7491624B2]
Brief Description: This patent describes semiconductor devices with strained channel regions and their manufacturing methods. It focuses on forming gate structures (including metal gates) and subsequently creating strain-inducing source/drain regions, such as embedded SiGe. [cite: US7491624B2]
Potential Anticipation: Similar to US7491629B2, this patent potentially anticipates claims of US8198686 concerning the use of stress-inducing layers (like SiGe for p-type devices in claims 9 and 10, and related method steps in Claim 11, particularly steps h and i). The general concept of metal gates and advanced processing could also broadly anticipate structural and method claims of US8198686.

3. US7485934B2

Full Citation: US7,485,934 B2 to De et al. (Intel Corporation). [cite: US7485934B2]
Publication Date: February 3, 2009. [cite: US7485934B2]
Filing Date: March 28, 2005. [cite: US7485934B2]
Brief Description: This patent describes high-k/metal gate structures and methods of forming them, specifically highlighting replacement gate techniques for CMOS devices. It addresses the challenges of integrating different metal gate materials for NMOS and PMOS devices. [cite: US7485934B2]
Potential Anticipation: This patent is highly relevant as it explicitly discusses high-k/metal gate structures and replacement gate techniques for CMOS, aimed at integrating different metal gates for NMOS and PMOS. This directly relates to the core invention of US8198686 concerning dual-metal gates and the manufacturing method. It potentially anticipates both structural claims (e.g., Claims 1-10 describing the dual-metal gate device) and method claims (e.g., Claims 11-19 describing the replacement gate process, particularly the general concept of forming a dummy gate and replacing it with a metal gate).

4. US7470603B2

Full Citation: US7,470,603 B2 to Lee et al. (Intel Corporation). [cite: US7470603B2]
Publication Date: December 30, 2008. [cite: US7470603B2]
Filing Date: March 31, 2006. [cite: US7470603B2]
Brief Description: This patent describes methods for forming complementary metal-oxide-semiconductor (CMOS) devices with different metal gate electrodes for N-type and P-type transistors, often utilizing a replacement gate process to achieve optimized work functions. [cite: US7470603B2]
Potential Anticipation: This patent is also highly relevant due to its focus on forming CMOS devices with different metal gate electrodes for n-type and p-type transistors, frequently using replacement gate processes. This aligns with the main objective and method of US8198686. It potentially anticipates both the structural claims (e.g., Claims 1-10 describing the dual-metal gate device) and the method claims (e.g., Claims 11-19, particularly the overall strategy of integrating different metal gate materials using a gate-last approach).

5. US7465999B2

Full Citation: US7,465,999 B2 to Kim et al. (Samsung Electronics Co., Ltd.). [cite: US7465999B2]
Publication Date: December 16, 2008. [cite: US7465999B2]
Filing Date: December 21, 2006. [cite: US7465999B2]
Brief Description: This patent describes a semiconductor device and a method of manufacturing it, including forming metal gate electrodes and often employing a "gate last" process to achieve different work functions for NMOS and PMOS devices. [cite: US7465999B2]
Potential Anticipation: This patent discusses a gate-last process for metal gate electrodes in NMOS and PMOS devices to achieve different work functions, which is a core concept in US8198686. It potentially anticipates both structural claims (e.g., Claims 1-10 related to the dual-metal gate structure) and method claims (e.g., Claims 11-19 concerning the manufacturing method, especially the use of a replacement gate scheme to implement dual metal gates).

6. US7456488B2

Full Citation: US7,456,488 B2 to Shin et al. (Samsung Electronics Co., Ltd.). [cite: US7456488B2]
Publication Date: November 25, 2008. [cite: US7456488B2]
Filing Date: April 20, 2006. [cite: US7456488B2]
Brief Description: This patent discloses methods for fabricating integrated circuits using a "gate last" approach, allowing for the independent optimization of gate electrode materials for NMOS and PMOS transistors. [cite: US7456488B2]
Potential Anticipation: Similar to other Samsung patents, this reference's focus on a gate-last process for optimizing gate electrode materials for NMOS and PMOS directly addresses a primary goal of US8198686. It potentially anticipates structural claims (e.g., Claims 1-10 for the dual-metal gate configuration) and method claims (e.g., Claims 11-19, particularly the replacement gate strategy for achieving different work functions in n-type and p-type devices).

7. US7449377B2

Full Citation: US7,449,377 B2 to Shin et al. (Samsung Electronics Co., Ltd.). [cite: US7449377B2]
Publication Date: November 11, 2008. [cite: US7449377B2]
Filing Date: April 20, 2006. [cite: US7449377B2]
Brief Description: This patent describes a method for fabricating a CMOS device using a gate-last process to form metal gates with different work functions for N-type and P-type transistors. [cite: US7449377B2]
Potential Anticipation: Similar to the other Samsung patents, this reference's focus on a gate-last process for forming metal gates with distinct work functions for NMOS and PMOS transistors directly aligns with the objectives and methods of US8198686. It potentially anticipates structural claims (e.g., Claims 1-10 for the device structure) and method claims (e.g., Claims 11-19 for the manufacturing process involving gate replacement and dual metal gates).

8. US7442629B2

Full Citation: US7,442,629 B2 to Chang et al. (Taiwan Semiconductor Manufacturing Company, Ltd.). [cite: US7442629B2]
Publication Date: October 28, 2008. [cite: US7442629B2]
Filing Date: March 28, 2005. [cite: US7442629B2]
Brief Description: This patent describes a method of fabricating a semiconductor device that includes forming a sacrificial gate and later replacing it with a metal gate electrode, often for use in high-k/metal gate stacks. [cite: US7442629B2]
Potential Anticipation: This patent broadly covers the concept of a "replacement gate" or "gate last" process, which is fundamental to the manufacturing method described in US8198686 (Claim 11). It would anticipate the general idea of forming a temporary gate structure and replacing it with a final metal gate.

9. US7427546B2

Full Citation: US7,427,546 B2 to Chidambarrao et al. (International Business Machines Corporation). [cite: US7427546B2]
Publication Date: September 23, 2008. [cite: US7427546B2]
Filing Date: June 29, 2005. [cite: US7427546B2]
Brief Description: This patent discusses methods for forming metal gate structures, especially in conjunction with high-k dielectrics, and often employs a replacement gate approach to integrate different metal work functions for CMOS devices. [cite: US7427546B2]
Potential Anticipation: This patent is relevant due to its focus on forming metal gate structures with high-k dielectrics and employing a replacement gate approach for integrating different metal work functions in CMOS devices. This directly addresses key aspects of US8198686's invention. It potentially anticipates both structural claims (e.g., Claims 1-10 related to high-k/dual-metal gate stacks) and method claims (e.g., Claims 11-19, particularly the use of a replacement gate process for work function engineering for n-type and p-type transistors).

10. US7419890B2

Full Citation: US7,419,890 B2 to Liu et al. (International Business Machines Corporation). [cite: US7419890B2]
Publication Date: September 2, 2008. [cite: US7419890B2]
Filing Date: June 29, 2005. [cite: US7419890B2]
Brief Description: This patent describes techniques for fabricating high-performance CMOS devices by forming self-aligned metal gates with different work functions for NMOS and PMOS, often using a "gate last" process. [cite: US7419890B2]
Potential Anticipation: This patent's description of fabricating high-performance CMOS devices with self-aligned metal gates having different work functions for NMOS and PMOS, frequently via a gate-last process, directly relates to the core invention of US8198686. It potentially anticipates both structural claims (e.g., Claims 1-10 for the dual-metal gate structure) and method claims (e.g., Claims 11-19, particularly the gate-last approach for achieving work function differences).

11. US7390740B2

Full Citation: US7,390,740 B2 to Lim et al. (Samsung Electronics Co., Ltd.). [cite: US7390740B2]
Publication Date: June 24, 2008. [cite: US7390740B2]
Filing Date: January 12, 2006. [cite: US7390740B2]
Brief Description: This patent describes a method for manufacturing a semiconductor device, particularly focusing on forming gate electrodes with different work functions for n-type and p-type devices using a replacement gate process. [cite: US7390740B2]
Potential Anticipation: This patent is highly relevant as it details a method for manufacturing a semiconductor device with gate electrodes having different work functions for n-type and p-type devices, specifically mentioning a replacement gate process. This directly anticipates the fundamental aspects of US8198686's method (Claim 11) and the resulting device structure (Claim 1).

12. US7388277B2

Full Citation: US7,388,277 B2 to Ieong et al. (International Business Machines Corporation). [cite: US7388277B2]
Publication Date: June 17, 2008. [cite: US7388277B2]
Filing Date: June 30, 2005. [cite: US7388277B2]
Brief Description: This patent describes methods for forming complementary field effect transistors with different metal gate electrodes, often involving a gate-last integration scheme, to improve performance. [cite: US7388277B2]
Potential Anticipation: This patent addresses the formation of complementary FETs with different metal gate electrodes using a gate-last scheme, which is a key technical area for US8198686. It potentially anticipates structural claims (e.g., Claims 1-10 for the CMOS device with dual metal gates) and method claims (e.g., Claims 11-19, particularly the replacement gate process for work function tuning).

13. US7361596B2

Full Citation: US7,361,596 B2 to Ohguro et al. (NEC Corporation). [cite: US7361596B2]
Publication Date: April 22, 2008. [cite: US7361596B2]
Filing Date: May 10, 2006. [cite: US7361596B2]
Brief Description: This patent describes a semiconductor device manufacturing method for forming gate electrodes, potentially with different materials or work functions, in a self-aligned manner. [cite: US7361596B2]
Potential Anticipation: This patent broadly discusses semiconductor device manufacturing methods for forming gate electrodes, including aspects that might improve alignment. While it may not explicitly detail dual metal gate replacement in the same manner as US8198686, the focus on gate formation and precision could potentially anticipate general method steps in US8198686 (e.g., Claim 11, particularly steps related to initial gate formation and subsequent processing for high precision).

14. US7320935B2

Full Citation: US7,320,935 B2 to Chau et al. (Intel Corporation). [cite: US7320935B2]
Publication Date: January 22, 2008. [cite: US7320935B2]
Filing Date: March 28, 2005. [cite: US7320935B2]
Brief Description: This patent relates to semiconductor devices with high-k gate dielectrics and metal gates, often integrated using replacement gate processes for CMOS applications to achieve different effective work functions. [cite: US7320935B2]
Potential Anticipation: This patent's focus on high-k gate dielectrics and metal gates integrated using replacement gate processes for CMOS, specifically to achieve different effective work functions, is highly relevant. It potentially anticipates both structural claims (e.g., Claims 1-10, especially regarding high-k gate insulating films) and method claims (e.g., Claims 11-19, particularly the gate-last methodology for dual metal gates).

15. US7282431B2

Full Citation: US7,282,431 B2 to Chang et al. (Taiwan Semiconductor Manufacturing Company, Ltd.). [cite: US7282431B2]
Publication Date: October 16, 2007. [cite: US7282431B2]
Filing Date: March 28, 2005. [cite: US7282431B2]
Brief Description: This patent describes a method for fabricating a metal gate MOS device using a "gate last" approach, where a sacrificial gate is replaced by a metal gate electrode. [cite: US7282431B2]
Potential Anticipation: This patent clearly describes a "gate last" approach for fabricating metal gate MOS devices. This fundamental method is a cornerstone of US8198686's manufacturing process (Claim 11). It would anticipate the general principle of forming a sacrificial gate and replacing it with a metal gate.

16. US7238612B2

Full Citation: US7,238,612 B2 to Kori et al. (Fujitsu Limited). [cite: US7238612B2]
Publication Date: July 3, 2007. [cite: US7238612B2]
Filing Date: May 19, 2006. [cite: US7238612B2]
Brief Description: This patent describes a method of manufacturing a semiconductor device that includes forming different metal gate electrodes for n-type and p-type MOS transistors. [cite: US7238612B2]
Potential Anticipation: This patent directly addresses the formation of different metal gate electrodes for n-type and p-type MOS transistors, which is a core objective of US8198686. Depending on the specific manufacturing steps disclosed, it could potentially anticipate both structural claims (e.g., Claims 1-10 for the dual-metal gate device) and method claims (e.g., Claims 11-19, particularly the general concept of creating distinct metal gates for CMOS).

17. US7166542B2

Full Citation: US7,166,542 B2 to Kavalieros et al. (Intel Corporation). [cite: US7166542B2]
Publication Date: January 23, 2007. [cite: US7166542B2]
Filing Date: September 29, 2005. [cite: US7166542B2]
Brief Description: This patent details methods for integrating high-k gate dielectrics with metal gate electrodes, often using a replacement gate process to allow for different work function metals for NMOS and PMOS. [cite: US7166542B2]
Potential Anticipation: This patent's focus on integrating high-k gate dielectrics with metal gate electrodes via a replacement gate process to enable different work functions for NMOS and PMOS is highly relevant. It potentially anticipates both structural claims (e.g., Claims 1-10, especially concerning high-k dielectrics) and method claims (e.g., Claims 11-19, particularly the gate-last approach for dual metal gate work function engineering).

18. US7109095B2

Full Citation: US7,109,095 B2 to Chen et al. (Taiwan Semiconductor Manufacturing Company, Ltd.). [cite: US7109095B2]
Publication Date: September 12, 2006. [cite: US7109095B2]
Filing Date: March 28, 2005. [cite: US7109095B2]
Brief Description: This patent describes a method for manufacturing a semiconductor device that involves forming a high-k gate dielectric and a metal gate electrode, potentially using a gate-last approach. [cite: US7109095B2]
Potential Anticipation: This patent broadly covers methods for forming high-k gate dielectrics and metal gate electrodes, potentially via gate-last techniques. While not as specific about dual metal gates as others, the underlying principles of high-k/metal gate formation and gate replacement could broadly anticipate elements of method claims (e.g., Claim 11, particularly steps related to the formation of gate insulating films and metal gates).

19. US7098115B2

Full Citation: US7,098,115 B2 to Kim et al. (Samsung Electronics Co., Ltd.). [cite: US7098115B2]
Publication Date: August 29, 2006. [cite: US7098115B2]
Filing Date: September 17, 2004. [cite: US7098115B2]
Brief Description: This patent describes a method for fabricating a semiconductor device with improved gate structures, including techniques for forming gate electrodes and potentially sidewall spacers. [cite: US7098115B2]
Potential Anticipation: This patent generally discusses methods for fabricating semiconductor devices with improved gate structures and sidewall spacers. Elements related to forming spacers (e.g., offset spacers and inner sidewalls as described in US8198686) could potentially anticipate aspects of structural claims (e.g., Claim 1 and related dependent claims) and method claims (e.g., Claim 11, particularly step g).

20. US6908801B2

Full Citation: US6,908,801 B2 to Kim et al. (Samsung Electronics Co., Ltd.). [cite: US6908801B2]
Publication Date: June 21, 2005. [cite: US6908801B2]
Filing Date: May 12, 2004. [cite: US6908801B2]
Brief Description: This patent describes a method for fabricating a semiconductor device using a gate-last process, particularly for forming metal gate electrodes to overcome depletion effects of polysilicon gates. [cite: US6908801B2]
Potential Anticipation: This patent details a gate-last process for fabricating metal gate electrodes to address issues like polysilicon depletion, which is a known problem that dual metal gates aim to solve. This directly relates to the motivations for US8198686 and potentially anticipates the broad concept of using a replacement gate method to introduce metal gates, as found in US8198686's method claims (e.g., Claim 11).

21. US20070238289A1

Full Citation: US2007/0238289 A1 to Song et al. (Samsung Electronics Co., Ltd.). [cite: US20070238289A1]
Publication Date: October 11, 2007. [cite: US20070238289A1]
Filing Date: April 5, 2006. [cite: US20070238289A1]
Brief Description: This application describes a method of fabricating a semiconductor device with different work function metal gate electrodes for NMOS and PMOS transistors, often utilizing a gate-last process for independent optimization. [cite: US20070238289A1]
Potential Anticipation: This published application is highly relevant as it describes a method for fabricating devices with different work function metal gate electrodes for NMOS and PMOS, often using a gate-last process for independent optimization. This aligns very closely with the core invention of US8198686. It potentially anticipates both the structural claims (e.g., Claims 1-10 for the dual-metal gate device) and method claims (e.g., Claims 11-19, particularly the gate-last approach for achieving precision and different work functions).

22. US20070182006A1

Full Citation: US2007/0182006 A1 to Kavalieros et al. (Intel Corporation). [cite: US20070182006A1]
Publication Date: August 9, 2007. [cite: US20070182006A1]
Filing Date: September 29, 2005. [cite: US20070182006A1]
Brief Description: This application describes semiconductor devices with high-k gate dielectrics and dual metal gates, and methods of fabricating them, often using replacement gate techniques. [cite: US20070182006A1]
Potential Anticipation: This published application describes semiconductor devices with high-k gate dielectrics and dual metal gates, and their fabrication methods, frequently involving replacement gate techniques. This is very pertinent to US8198686's invention. It potentially anticipates both structural claims (e.g., Claims 1-10, particularly concerning high-k dielectrics and dual metal gates) and method claims (e.g., Claims 11-19, particularly the gate-last approach for dual metal gate formation).

23. US20060286762A1

Full Citation: US2006/0286762 A1 to Kim et al. (Samsung Electronics Co., Ltd.). [cite: US20060286762A1]
Publication Date: December 21, 2006. [cite: US20060286762A1]
Filing Date: June 15, 2006. [cite: US20060286762A1]
Brief Description: This application describes a method for manufacturing a semiconductor device, focusing on forming metal gates with different work functions using a gate-last process. [cite: US20060286762A1]
Potential Anticipation: This published application describes a method for manufacturing a semiconductor device, emphasizing the formation of metal gates with different work functions through a gate-last process. This directly relates to the core method and device of US8198686. It potentially anticipates both structural claims (e.g., Claims 1-10 for the dual-metal gate structure) and method claims (e.g., Claims 11-19, especially the gate-last strategy for work function control).

24. US20060017124A1

Full Citation: US2006/0017124 A1 to Brar et al. (Intel Corporation). [cite: US20060017124A1]
Publication Date: January 26, 2006. [cite: US20060017124A1]
Filing Date: June 29, 2005. [cite: US20060017124A1]
Brief Description: This application describes CMOS devices with different work function gate electrodes and methods for manufacturing them, often involving a replacement gate process and high-k dielectrics. [cite: US20060017124A1]
Potential Anticipation: This published application describes CMOS devices with different work function gate electrodes and their manufacturing methods, frequently involving a replacement gate process and high-k dielectrics. This is highly relevant to the problem and solution presented in US8198686. It potentially anticipates both structural claims (e.g., Claims 1-10, covering high-k and dual-metal gate aspects) and method claims (e.g., Claims 11-19, particularly the gate-last process for achieving work function differences).

Most Relevant Prior Art:

The most relevant prior art documents are those that explicitly discuss "gate-last" or "replacement gate" processes for integrating "dual metal gates" with "different work functions" for n-type and p-type MISFETs, particularly when combined with "high-k gate dielectrics" and "stress-inducing source/drain regions." These references directly address the underlying problems and solutions that US8198686 seeks to improve upon.

Specifically, the following patents/applications appear to be highly relevant in potentially anticipating the claims of US8198686:

US7485934B2 (De et al.)
US7470603B2 (Lee et al.)
US7390740B2 (Lim et al.)
US20070238289A1 (Song et al.)
US20070182006A1 (Kavalieros et al.)
US20060286762A1 (Kim et al.)
US20060017124A1 (Brar et al.)

These documents generally describe the state of the art concerning:

Structural Claims (e.g., Claims 1-10): A semiconductor device comprising first and second MIS transistors with gate electrodes made of different metal materials (dual metal gates), often incorporating high-k dielectrics and stress-inducing features in source/drain regions.
Method Claims (e.g., Claims 11-19): The broad concept of a replacement gate process for forming these dual metal gates, involving initial gate structures and subsequent selective replacement of materials to achieve desired work functions.

The specific novelty and non-obviousness of US8198686 would likely reside in the precise sequence of removal and deposition steps within the replacement gate process that enable the claimed "high precision" and "reduced width of the isolation region," particularly how the initial identical patterning leads to these benefits, which may not be explicitly taught or rendered obvious by the general disclosures of these prior art documents.