Prior art

The most relevant prior art for US patent 8076194 are identified from the "Citations" section of the patent document itself. Each cited patent is analyzed below for its potential anticipation under 35 U.S.C. § 102.

Analysis of Cited Prior Art for US8076194

1. US6110787A

• Full Citation: US6110787A, "Method for fabricating a MOS device," Chartered Semiconductor Manufacturing Ltd., published August 29, 2000.
• Publication/Filing Date: Publication Date: 2000-08-29; Priority Date: 1999-09-07.
• Brief Description: This patent describes a method for fabricating a MOS device that involves forming a gate, creating recessed source/drain regions, and then forming spacers. The method aims to prevent unwanted dopant diffusion during subsequent high-temperature processes. It includes forming a protective layer over the gate and substrate before forming the recesses. However, it does not explicitly disclose forming an epitaxial layer whose top surface is above the original substrate surface, nor a spacer whose contact surface with the epitaxial layer is above the original substrate surface.
• Potential Anticipated Claim(s): US6110787A describes general steps like forming a gate, forming a protective layer, forming recesses, and forming spacers. However, it likely does not anticipate the key features of US8076194's independent claims 1 and 10, particularly the "raised" epitaxial layer and the elevated contact surface between the epitaxial layer and the spacer, as this is a distinguishing feature of 8076194 aimed at enhancing strain.

2. US6429084B1

• Full Citation: US6429084B1, "MOS transistors with raised sources and drains," International Business Machines Corporation, published August 6, 2002.
• Publication/Filing Date: Publication Date: 2002-08-06; Priority Date: 2001-06-20.
• Brief Description: This patent describes MOS transistors with raised source and drain structures formed by epitaxial growth. The raised portions are typically formed after gate patterning and may involve spacers. The invention focuses on reducing parasitic resistance and improving device performance by creating elevated source/drain areas. It mentions forming a protective layer (e.g., nitride liner) over the gate and substrate before forming the raised source/drain regions.
• Potential Anticipated Claim(s): This patent discloses forming raised epitaxial layers for source/drain regions, which aligns with the "epitaxial layer in the recess, wherein the top surface of the epitaxial layer is above the surface of the semiconductor substrate" feature of claim 1. It also involves forming spacers on the sidewalls of the gate. Therefore, it potentially anticipates aspects of claims 1 and 10 related to raised epitaxial layers and spacers. Further analysis would be needed to see if the specific configuration of the contact surface between the epitaxial layer and spacer being above the substrate is explicitly taught or inherently present.

3. US20040142545A1

• Full Citation: US20040142545A1, "Semiconductor with tensile strained substrate and method of making the same," Advanced Micro Devices, Inc., published July 22, 2004.
• Publication/Filing Date: Publication Date: 2004-07-22; Priority Date: 2003-01-17.
• Brief Description: This publication describes methods for forming semiconductor devices with tensile strained channels to improve carrier mobility. It involves creating a recess in a semiconductor substrate and epitaxially growing a material like SiGe, which induces tensile strain in an overlying silicon channel. The focus is on strain engineering for performance enhancement. It describes forming a gate and then an epitaxial layer, but the details on the relative height of the epitaxial layer to the substrate surface and the spacer's contact point might differ from US8076194.
• Potential Anticipated Claim(s): This reference teaches the concept of using epitaxially grown layers to induce strain and enhance carrier mobility, which is the underlying goal of US8076194. It involves forming recesses and epitaxial growth. However, it might not explicitly disclose the specific structural configurations claimed in US8076194, such as the epitaxial layer being raised above the substrate surface and the spacer's contact surface with it also being above the substrate surface.

4. US6774000B2

• Full Citation: US6774000B2, "Method of manufacture of MOSFET device with in-situ doped, raised source and drain structures," International Business Machines Corporation, published August 10, 2004.
• Publication/Filing Date: Publication Date: 2004-08-10; Priority Date: 2002-11-20.
• Brief Description: This patent describes a method for manufacturing MOSFET devices with in-situ doped, raised source and drain structures. It involves forming a gate, then forming recesses, and subsequently growing doped epitaxial layers that are raised above the original substrate surface. The in-situ doping allows for the formation of source/drain regions concurrently with epitaxial growth, potentially eliminating separate implantation steps. Spacers are also used.
• Potential Anticipated Claim(s): This patent directly teaches forming raised epitaxial layers for source/drain regions which are in-situ doped, and the use of spacers. This significantly overlaps with elements of claims 1 and 10 of US8076194, especially the "top surface of the epitaxial layer is above the surface of the semiconductor substrate." The explicit mention of in-situ doping also relates to the optional step described in US8076194 (e.g., in-situ doped ion epitaxial growth process for forming source/drain regions). It would be highly relevant for anticipating the 'raised epitaxial layer' and 'spacer' elements in combination.

5. US6815770B1

• Full Citation: US6815770B1, "MOS transistor having reduced source/drain extension sheet resistance," United Microelectronics Corp., published November 9, 2004.
• Publication/Filing Date: Publication Date: 2004-11-09; Priority Date: 2003-08-14.
• Brief Description: This patent focuses on reducing the source/drain extension sheet resistance in MOS transistors. It describes forming a gate, then forming an offset spacer, followed by lightly doped regions, and then forming a main spacer. Source/drain regions are subsequently formed. The primary objective is to optimize doping profiles and resistances. It involves spacers and source/drain formation but does not explicitly focus on raised epitaxial layers or strained channels as a primary means of improvement, nor the specific geometric relationship of the epitaxial layer and spacer to the substrate surface.
• Potential Anticipated Claim(s): While this patent describes forming gates, spacers, and lightly doped/source/drain regions (elements common to claims 1 and 10 of US8076194), it does not appear to teach the critical feature of forming an epitaxial layer in a recess where its top surface is above the semiconductor substrate, nor the subsequent spacer contact. Thus, it likely does not anticipate the core distinguishing features of US8076194.

6. US20040232513A1

• Full Citation: US20040232513A1, "Silicon strain engineering accomplished via use of specific shallow trench isolation fill materials," Taiwan Semiconductor Manufacturing Co., published November 25, 2004.
• Publication/Filing Date: Publication Date: 2004-11-25; Priority Date: 2003-05-23.
• Brief Description: This publication describes a method of silicon strain engineering using specific shallow trench isolation (STI) fill materials to induce strain in the device channel, thereby improving carrier mobility. It focuses on the materials used in isolation structures to create stress. While it relates to strain engineering in transistors, it does not deal with forming recesses adjacent to a gate and growing raised epitaxial layers for source/drain regions or the specific interaction with spacers as claimed in US8076194.
• Potential Anticipated Claim(s): This reference's focus on STI fill materials for strain engineering means it does not anticipate the specific method steps of forming a recess, a raised epitaxial layer, and a spacer contacting the raised layer as described in claims 1 and 10 of US8076194.

7. TW200509310A

• Full Citation: TW200509310A, "Field effect transistor having increased carrier mobility," Advanced Micro Devices Inc., published March 1, 2005.
• Publication/Filing Date: Publication Date: 2005-03-01; Priority Date: 2003-08-18.
• Brief Description: This Taiwanese patent application relates to field-effect transistors with increased carrier mobility through strain engineering. It describes forming recesses in the source/drain regions and epitaxially growing materials like SiGe or Si:C to induce strain in the channel. The technique is aimed at improving device performance. Similar to other strain engineering patents, it focuses on the materials and the induced strain but needs closer examination for the specific raised epitaxial layer and spacer configuration of US8076194.
• Potential Anticipated Claim(s): This reference generally covers strain engineering through epitaxial growth in source/drain regions. It may anticipate the broad concept of forming an epitaxial layer in recesses to induce strain. However, without further details on whether the epitaxial layer is raised above the substrate surface and the specific contact surface of the spacer, it is unlikely to anticipate the unique geometric features of US8076194's independent claims 1 and 10.

8. US20050156154A1

• Full Citation: US20050156154A1, "Protecting Silicon Germanium Sidewall with Silicon for Strained Silicon/Silicon Germanium MOSFETs," International Business Machines Corporation, published July 21, 2005.
• Publication/Filing Date: Publication Date: 2005-07-21; Priority Date: 2004-01-16.
• Brief Description: This publication discloses a method for protecting SiGe sidewalls with silicon in strained silicon/SiGe MOSFETs. This is primarily a processing technique to prevent damage or oxidation of SiGe regions during subsequent manufacturing steps, especially during spacer formation. It involves selective epitaxial growth of silicon on the SiGe. While it deals with SiGe and spacers in strained devices, its focus is on protection, not necessarily on forming a raised epitaxial layer and a contact surface above the substrate in the manner of US8076194.
• Potential Anticipated Claim(s): This reference focuses on protecting SiGe sidewalls with silicon. While it is in the context of strained MOSFETs and involves spacers, it does not appear to disclose the specific feature of the epitaxial layer being raised above the substrate surface such that the spacer's contact surface with it is also above the substrate. Therefore, it likely does not anticipate claims 1 or 10.

9. US20060024879A1

• Full Citation: US20060024879A1, "Selectively strained MOSFETs to improve drive current," Taiwan Semiconductor Manufacturing Co., Ltd., published February 2, 2006.
• Publication/Filing Date: Publication Date: 2006-02-02; Priority Date: 2004-07-31.
• Brief Description: This publication describes selectively strained MOSFETs where recesses are etched in the source/drain regions and filled with epitaxially grown SiGe or Si:C to induce compressive or tensile strain in the channel. This aims to improve drive current. It generally teaches forming recessed source/drain regions and filling them with stress-inducing epitaxial material.
• Potential Anticipated Claim(s): This reference generally covers the concept of creating strained channels by forming recesses and epitaxially growing stress-inducing materials. It likely anticipates the broad concept of forming recesses and epitaxial layers for strain. However, without explicit disclosure of the epitaxial layer being raised above the original substrate surface and the specific contact surface of the spacer also being above the substrate, it may not anticipate the specific geometric elements of claims 1 and 10 of US8076194.

10. US20060134873A1

• Full Citation: US20060134873A1, "Tailoring channel strain profile by recessed material composition control," Texas Instruments Incorporated, published June 22, 2006.
• Publication/Filing Date: Publication Date: 2006-06-22; Priority Date: 2004-12-22.
• Brief Description: This publication describes tailoring the channel strain profile in MOSFETs by controlling the composition of material in recessed source/drain regions. It involves forming recesses and epitaxially growing material, potentially with varying compositions, to optimize strain. It focuses on the ability to control strain via material composition.
• Potential Anticipated Claim(s): Similar to US20060024879A1, this reference teaches the use of epitaxially grown material in recesses for strain engineering. The anticipation of US8076194's claims would depend on whether it explicitly discloses the raised epitaxial layer feature and the specific spacer contact configuration claimed. It generally falls into the category of strain engineering using embedded stressors.

11. US20060211245A1

• Full Citation: US20060211245A1, "Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect," Advanced Micro Devices, Inc., published September 21, 2006.
• Publication/Filing Date: Publication Date: 2006-09-21; Priority Date: 2003-12-03.
• Brief Description: This publication discusses forming abrupt junctions in semiconductor devices using the dopant snowplow effect during silicide growth. The primary focus is on dopant activation and junction formation, not on creating strained channels via raised epitaxial layers or the specific geometry of spacers in relation to them.
• Potential Anticipated Claim(s): This reference primarily concerns dopant activation and junction formation during silicidation. It does not teach the core method steps of forming raised epitaxial layers or the specific spacer configuration of US8076194, and thus does not anticipate claims 1 or 10.

12. US20060226483A1

• Full Citation: US20060226483A1, "Method of fabricating strained channel devices," Agency For Science, Technology And Research, published October 12, 2006.
• Publication/Filing Date: Publication Date: 2006-10-12; Priority Date: 2005-04-06.
• Brief Description: This publication describes methods for fabricating strained channel devices, including forming recesses in the source/drain regions and then epitaxially growing stress-inducing materials like SiGe. The goal is to enhance carrier mobility. It addresses the general problem of achieving desired strain in the channel region.
• Potential Anticipated Claim(s): This reference, like others, teaches the general principle of using epitaxially grown stressors in recesses for strained channel devices. The question of anticipation for US8076194's claims 1 and 10 hinges on whether it explicitly discloses the raised nature of the epitaxial layer relative to the substrate surface and the resultant elevated contact surface of the spacer with this raised layer.

13. TW200636996A

• Full Citation: TW200636996A, "Structure and method for manufacturing strained FINFET," Ibm, published October 16, 2006.
• Publication/Filing Date: Publication Date: 2006-10-16; Priority Date: 2005-02-15.
• Brief Description: This Taiwanese patent describes a structure and method for manufacturing strained FinFETs. FinFETs have a different device architecture than planar MOSFETs, utilizing a fin-shaped channel. While it involves strain engineering and potentially epitaxial growth, the FinFET structure fundamentally differs from the planar MOS transistor fabrication described in US8076194.
• Potential Anticipated Claim(s): This reference is directed to FinFET technology, which is structurally distinct from the planar MOS transistors primarily addressed by US8076194. While both relate to strained devices, the specific fabrication steps for a FinFET, especially the geometry of source/drain regions and spacers relative to the fin, would likely not directly anticipate the claims of US8076194, which are focused on planar MOS structures with raised epitaxial layers.

14. US7195985B2

• Full Citation: US7195985B2, "CMOS transistor junction regions formed by a CVD etching and deposition sequence," Intel Corporation, published March 27, 2007.
• Publication/Filing Date: Publication Date: 2007-03-27; Priority Date: 2005-01-04.
• Brief Description: This patent describes forming CMOS transistor junction regions using a CVD etching and deposition sequence. This method aims to create precise junction profiles. It involves forming recesses and then depositing materials, which could include epitaxial growth. The patent primarily focuses on the CVD process for junction formation.
• Potential Anticipated Claim(s): This patent's focus is on CVD etching and deposition for junction formation. While it involves forming recesses and deposition, it is not explicitly focused on the raised aspect of the epitaxial layer and the elevated spacer contact as defined in US8076194's claims 1 and 10. Thus, it is unlikely to anticipate these specific features.

15. US20070298558A1

• Full Citation: US20070298558A1, "Method of fabricating semiconductor device and semiconductor device," Kabushiki Kaisha Toshiba, published December 27, 2007.
• Publication/Filing Date: Publication Date: 2007-12-27; Priority Date: 2006-06-22.
• Brief Description: This publication describes a method of fabricating a semiconductor device where a semiconductor layer, such as SiGe, is grown epitaxially in a recess and then covered with an insulating film. The goal is to apply strain to the channel. It describes a structure with a gate, recesses, and an epitaxially grown layer.
• Potential Anticipated Claim(s): This reference teaches forming an epitaxial layer in recesses for strain application. It may anticipate aspects related to forming recesses and epitaxial layers. However, the exact configuration of the epitaxial layer being raised above the substrate and the spacer's contact surface being above the substrate would need to be explicitly present to anticipate claims 1 and 10 of US8076194.

16. US20080006818A1

• Full Citation: US20080006818A1, "Structure and method to form multilayer embedded stressors," International Business Machines Corporation, published January 10, 2008.
• Publication/Filing Date: Publication Date: 2008-01-10; Priority Date: 2006-06-09.
• Brief Description: This publication describes structures and methods for forming multilayer embedded stressors in semiconductor devices. It involves forming recesses and growing multiple epitaxial layers with different lattice constants to create complex strain profiles. This is a more advanced approach to strain engineering.
• Potential Anticipated Claim(s): This reference describes sophisticated embedded stressors using multilayer epitaxial growth. While it deals with recesses and epitaxial layers for strain, the core innovation of US8076194 lies in the raised nature of the epitaxial layer and the specific spacer contact surface being above the substrate. This reference's focus is on the complexity of the stressor layers, not necessarily the specific geometric relationships claimed in US8076194.

17. US20080032468A1

• Full Citation: US20080032468A1, "Mos transistor and fabrication thereof," United Microelectronics Corp., published February 7, 2008.
• Publication/Filing Date: Publication Date: 2008-02-07; Priority Date: 2006-08-01.
• Brief Description: This publication describes a MOS transistor and its fabrication, including forming a gate and then source/drain regions. It may involve strain engineering techniques. This patent is from the same original assignee as US8076194, United Microelectronics Corp., suggesting related work. Further examination would be needed to see if it specifically discloses the raised epitaxial layer and elevated spacer contact.
• Potential Anticipated Claim(s): As a patent from the same original assignee, it's possible this reference contains similar or foundational concepts. It generally relates to MOS transistor fabrication. To anticipate claims 1 and 10 of US8076194, it would need to explicitly disclose the raised epitaxial layer and the spacer's contact surface with it being above the substrate surface. Without specific details, it's difficult to ascertain direct anticipation from the title/abstract alone.

18. US7381623B1

• Full Citation: US7381623B1, "Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance," International Business Machines Corporation, published June 3, 2008.
• Publication/Filing Date: Publication Date: 2008-06-03; Priority Date: 2007-01-17.
• Brief Description: This patent describes a pre-epitaxial disposable spacer integration scheme for enhanced device performance, utilizing very low-temperature selective epitaxy. This involves forming a disposable spacer, then epitaxial growth, and then removing the disposable spacer before forming the final spacer. The goal is to optimize the epitaxial growth process for strained devices. The timing of spacer formation relative to epitaxial growth is a key aspect.
• Potential Anticipated Claim(s): This patent describes a method where an epitaxial layer is formed before the final spacer, which is a key distinguishing feature of US8076194. It also focuses on enhanced device performance. This reference would be highly relevant for anticipating the sequence of forming the epitaxial layer before the spacer, and potentially aspects of the raised epitaxial layer and its interaction with a spacer, making it a strong candidate for anticipating claims 1 and 10 of US8076194.

19. US20080179636A1

• Full Citation: US20080179636A1, "N-fets with tensilely strained semiconductor channels, and method for fabricating same using buried pseudomorphic layers," International Business Machines Corporation, published July 31, 2008.
• Publication/Filing Date: Publication Date: 2008-07-31; Priority Date: 2007-01-27.
• Brief Description: This publication describes n-type field-effect transistors with tensilely strained semiconductor channels, fabricated using buried pseudomorphic layers. It focuses on achieving tensile strain for n-channel devices. The method involves forming trenches and growing specific materials to induce the desired strain.
• Potential Anticipated Claim(s): This reference relates to achieving tensile strain in nFETs using buried layers, a specific type of strain engineering. While it involves forming trenches and epitaxial growth, it is focused on buried layers for strain, which differs from the raised epitaxial layer configuration of US8076194's claims 1 and 10. Therefore, it is less likely to anticipate the specific structural features of US8076194.

20. US20080203449A1

• Full Citation: US20080203449A1, "Source/drain stressor and method therefor," Da Zhang, published August 28, 2008.
• Publication/Filing Date: Publication Date: 2008-08-28; Priority Date: 2007-02-28.
• Brief Description: This publication describes a source/drain stressor and a method for forming it. It involves forming a recess in the source/drain regions and growing a stressor material (e.g., SiGe) epitaxially. The goal is to induce strain in the channel. It generally teaches forming embedded stressors.
• Potential Anticipated Claim(s): This reference broadly covers forming embedded source/drain stressors using epitaxial growth in recesses. The anticipation of US8076194's claims 1 and 10 would hinge on whether it explicitly discloses the raised nature of the epitaxial layer and the specific contact surface of the spacer with the epitaxial layer being above the substrate surface.

21. US7745847B2

• Full Citation: US7745847B2, "Metal oxide semiconductor transistor," United Microelectronics Corp., published June 29, 2010.
• Publication/Filing Date: Publication Date: 2010-06-29; Priority Date: 2007-08-09.
• Brief Description: This patent is the parent application from which US8076194 is a divisional application. It describes a metal oxide semiconductor transistor structure comprising a gate, two raised epitaxial layers next to the gate, and a spacer formed on the sidewall of the gate and extending laterally upon a portion of the raised epitaxial layer. It also includes two doped regions. As a parent patent, it discloses the structure that the method claims of US8076194 aim to produce.
• Potential Anticipated Claim(s): As the parent application, US7745847B2 discloses the device structure that US8076194 claims a method of fabricating. Therefore, it will inherently disclose the structure resulting from the method claims, and potentially the steps if they are described. The claims of US8076194 (methods for fabricating the structure) would be anticipated by the disclosure of the parent patent if the method steps were also taught or rendered obvious by the parent. Given the explicit structural elements in its claims (e.g., "two raised epitaxial layers," "a spacer formed on the sidewall of the gate and extending laterally upon a portion of the raised epitaxial layer"), it directly describes the core structural outcomes of claims 1 and 10 of US8076194.

22. US7800182B2

• Full Citation: US7800182B2, "Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same," Infineon Technologies Ag, published September 21, 2010.
• Publication/Filing Date: Publication Date: 2010-09-21; Priority Date: 2006-11-20.
• Brief Description: This patent describes semiconductor devices, specifically pFETs, that include SiGe gate electrodes and embedded SiGe source/drain regions. The embedded SiGe is used to induce compressive strain in the channel to enhance hole mobility. The methods involve forming recesses for the SiGe source/drain regions.
• Potential Anticipated Claim(s): This patent teaches the use of embedded SiGe in source/drain regions for strain in pFETs, a concept relevant to US8076194. It also involves forming recesses. The extent of anticipation for claims 1 and 10 of US8076194 would depend on whether this patent explicitly discloses the epitaxial layer being raised above the substrate surface and the spacer's contact surface with it being above the substrate surface. It is a strong candidate for generally teaching embedded SiGe stressors.