Obviousness

Obviousness Analysis under 35 U.S.C. § 103 for US Patent 8076194

This analysis evaluates whether the claimed invention of US Patent 8076194 would have been obvious to a person having ordinary skill in the art (PHOSITA) at the time of the invention, in light of the prior art. The core inquiry under 35 U.S.C. § 103 asks whether the differences between the claimed invention and the prior art are such that the subject matter as a whole would have been obvious to a PHOSITA. This includes considering the scope and content of the prior art, the differences between the prior art and the claims, the level of ordinary skill in the art, and any secondary considerations of non-obviousness.

The key innovative aspects highlighted by US8076194 relate to a specific sequence of fabricating a MOS (and CMOS) transistor, particularly forming a raised epitaxial layer for source/drain regions before forming the permanent gate sidewall spacers, and utilizing a protective layer during recess etching. This approach aims to provide better control over strain in the channel, reduce micro-loading effects during etching, and prevent dopant diffusion.

Identification of Key Prior Art References

Based on the patent text and cited references, the following prior art is particularly relevant for an obviousness analysis:

• US7381623B1 (IBM): "Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance". This reference describes a method for forming raised source/drain (RSD) structures, which involves forming a gate, then a sacrificial spacer, then epitaxially growing source/drain regions, removing the sacrificial spacer, and finally forming a permanent spacer that covers portions of the epitaxially grown regions.
• US6429084B1 (IBM): "MOS transistors with raised sources and drains". This patent broadly teaches the concept of forming MOS transistors with raised source and drain regions through epitaxial growth.
• US20040142545A1 (Advanced Micro Devices, Inc.): "Semiconductor with tensile strained substrate and method of making the same". This reference, and others like US20060024879A1, illustrate the known technique of using strained materials to enhance carrier mobility in MOS transistors.
• General knowledge in the art: The routine use of protective layers (e.g., silicon nitride) during etching steps to prevent damage to underlying structures like gates and shallow trench isolations (STIs) is common practice in semiconductor manufacturing. Similarly, the extension of fabrication processes from single MOS transistors to complementary MOS (CMOS) structures by employing sequential masking and selective material deposition for N-type and P-type devices is also well-established.

Obviousness Analysis of Independent Claim 1

Independent Claim 1 describes a method of fabricating a MOS transistor, including:

1. Providing a semiconductor substrate.
2. Forming at least a gate on the semiconductor substrate.
3. Forming a protective layer on the semiconductor substrate, covering the surface of the gate.
4. Forming at least a recess within the semiconductor substrate adjacent to the gate.
5. Forming an epitaxial layer in the recess, where its top surface is above the semiconductor substrate surface.
6. Forming a spacer on the sidewall of the gate and on a portion of the epitaxial layer, where a contact surface of the epitaxial layer and the spacer is above the semiconductor substrate surface.

Combination: US7381623B1 in view of US6429084B1 and general knowledge in the art.

Mapping of Claim Elements to Prior Art:

• "providing a semiconductor substrate": Taught by US7381623B1 (e.g., substrate 110 in Fig. 1).
• "forming at least a gate on the semiconductor substrate": Taught by US7381623B1 (e.g., gate structure 120 in Fig. 2).
• "forming a protective layer on the semiconductor substrate, and the protective layer covering the surface of the gate": US7381623B1 discloses a nitride layer (122 in Fig. 2) formed over the gate electrode, which functions as a hardmask and protective layer during subsequent etching steps, including the etching of recesses (Fig. 3). This nitride layer protects the gate structure. While this protective layer in '623 is described as remaining, general knowledge in semiconductor processing teaches that temporary protective layers are routinely applied and removed as needed to protect structures during specific fabrication steps. A PHOSITA would recognize the benefits of using such a protective layer during recess etching to prevent damage to the gate and STI (as highlighted in US8076194) and would find it obvious to remove it if its function for subsequent steps is complete.
• "forming at least a recess within the semiconductor substrate adjacent to the gate": Taught by US7381623B1 (e.g., recesses 130 in Fig. 3).
• "forming an epitaxial layer in the recess, wherein the top surface of the epitaxial layer is above the surface of the semiconductor substrate": Taught by US7381623B1 (e.g., epitaxial S/D 132 in Fig. 4). US7381623B1 is directed to forming "raised source/drain (RSD) structures," and US6429084B1 also explicitly teaches "MOS transistors with raised sources and drains". A PHOSITA would understand that such "raised" structures inherently mean the top surface of the epitaxial layer is above the original semiconductor substrate surface.
• "forming a spacer on the sidewall of the gate and on a portion of the epitaxial layer wherein a contact surface of the epitaxial layer and the spacer is above the surface of the semiconductor substrate": US7381623B1 explicitly teaches forming a permanent spacer (142 in Fig. 5) on the sidewalls of the gate structure, which "covers portions of the S/D regions" (i.e., the already-formed epitaxial layers 132). Since the epitaxial layers are "raised," the contact surface between the permanent spacer and these raised epitaxial layers would necessarily be above the surface of the semiconductor substrate. This directly maps to the claim language.

Motivation to Combine/Modify:
A PHOSITA, seeking to develop high-performance MOS transistors with strained channels (a known technique for enhancing carrier mobility, as described in US20040142545A1) and raised source/drain structures, would be motivated to consider the methods disclosed in US7381623B1. US7381623B1 presents a fabrication sequence that places the formation of the epitaxial source/drain regions before the formation of the final, permanent gate sidewall spacers. This "pre-epitaxial" approach for the permanent spacer addresses the very problems cited by US8076194 as shortcomings of the prior art, such as limitations on the distance between the gate and epitaxial layer being determined by the spacer width. The use of a sacrificial spacer in '623 followed by its removal and then permanent spacer formation demonstrates a clear motivation to separate the definition of the epitaxial region from the final spacer width, thereby offering greater control and flexibility in device design.

Furthermore, the explicit use of a removable protective layer in US8076194 during recess etching, which is then removed before spacer formation, would be an obvious engineering choice for a PHOSITA. Such layers are conventionally used to protect critical features like gates and STI during aggressive etching steps, and their removal once their protective function is fulfilled is a routine process optimization. The benefits cited by '194 (reduced micro-loading, improved etch uniformity, reduced STI loss) are inherent advantages recognized by a PHOSITA when considering different processing sequences and protective measures.

Obviousness Analysis of Independent Claim 10

Independent Claim 10 extends the method of Claim 1 to a CMOS transistor fabrication, specifying distinct first and second conductive transistor areas, an isolation structure, and the sequential formation of a first protective layer, first recess, and first epitaxial layer for the first conductive area, followed by spacer formation. The second embodiment of US8076194 (FIG. 7-14) explicitly details this CMOS process.

Combination: US7381623B1 + US6429084B1 + general knowledge of CMOS fabrication and selective processing.

Mapping of Claim Elements to Prior Art:

• The foundational steps of forming gates, recesses, raised epitaxial layers, and then permanent spacers on the gate sidewalls and epitaxy are rendered obvious by US7381623B1 and US6429084B1, as discussed for Claim 1.
• "providing a semiconductor substrate having at least a first conductive transistor area for fabricating first conductive transistors and at least a second conductive transistor area for fabricating second conductive transistors, and an isolation structure between the first conductive transistor area and the second conductive transistor area": The concept of CMOS integration, including distinct transistor areas (e.g., PMOS and NMOS) and isolation structures like shallow trench isolations (STI), is a fundamental and long-established aspect of semiconductor device manufacturing. Numerous prior art references teach this, such as US7195985B2, which discusses "CMOS transistor junction regions".
• "forming a gate on the first conductive transistor area and on the second conductive transistor area respectively": Routine in CMOS fabrication.
• "forming a first protective layer on the semiconductor substrate, and the first protective layer covering the surface of each gate": As discussed for Claim 1, the use of a protective layer during recess etching is known, and its application across both transistor areas in a CMOS process would be an obvious extension.
• "forming at least a first recess within the semiconductor substrate adjacent to the gate in the first conductive transistor area; forming a first epitaxial layer in the first recess, wherein the top surface of the first epitaxial layer is above the surface of the semiconductor substrate": This is a direct application of the epitaxy-before-permanent-spacer raised source/drain technique (from US7381623B1 and US6429084B1) to a specific transistor type (e.g., PMOS with SiGe, as mentioned in '194) within a CMOS process. The sequential, masked processing to form features in one transistor area while protecting others is standard in CMOS.
• "forming a spacer on the sidewall of each gate and at least on a portion of the first epitaxial layer, wherein a contact surface of the first epitaxial layer and the spacer is above the surface of the semiconductor substrate": This is the application of the permanent spacer formation (from US7381623B1) to the CMOS context, covering the gate sidewalls and portions of the already-formed raised epitaxial layers in the respective transistor areas.

Motivation to Combine/Modify:
A PHOSITA would be motivated to apply the benefits of the raised epitaxial source/drain technology, particularly the improved control afforded by forming epitaxy before permanent spacers (as taught by US7381623B1), to CMOS devices. The challenges of optimizing carrier mobility in both PMOS (e.g., using SiGe) and NMOS (e.g., using SiC or tensile Si) devices are well-known in CMOS scaling (e.g., US20040142545A1). It would be obvious to a PHOSITA to adapt the method from US7381623B1 (or similar single-device methods) to a CMOS context by employing conventional masking and selective processing techniques to fabricate different types of epitaxial layers (e.g., SiGe for PMOS and SiC for NMOS) in their respective transistor areas. The sequential use of protective layers and etching/growth steps for different device types is a routine engineering adaptation for CMOS manufacturing.

Conclusion on Obviousness

The methods claimed in US Patent 8076194, as defined by independent claims 1 and 10, would likely be considered obvious to a PHOSITA in light of the combination of US7381623B1, US6429084B1, and general knowledge regarding semiconductor fabrication techniques, including CMOS processing and the use of protective layers. US7381623B1 specifically teaches a process flow that achieves the structural outcome of the '194 patent, where raised epitaxial source/drain regions are formed before the final gate sidewall spacers, and these spacers are then formed partially on the raised epitaxial layers. The motivations for such a sequence (e.g., greater control over epitaxy placement, strain engineering) were understood in the art, and the specific protective layer and its removal in '194 represent routine process optimizations.