US 7632751

Here is a concise summary of US Patent 7632751:

• Title: Semiconductor device having via connecting between interconnects
• Current Assignee: Advanced Integrated Circuit Process LLC
• Inventor: Takeshi Harada
• Filing Date: September 30, 2008
• Issue Date: December 15, 2009
• Abstract: A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in the first insulating film. A dummy via or an insulating slit is formed on/in the upper interconnect near the via.

Plain-Language Overview of Independent Claims (based on the "Definitions" section of the patent):

1. First Interconnection Structure: This claim describes a semiconductor device with a lower interconnect and an upper interconnect, connected by a via through a first insulating film. The lower interconnect is in a second insulating film beneath the first. A key feature is the inclusion of at least one "dummy via" connected to the upper interconnect, where the bottom of this dummy via is situated within the second insulating film. This dummy via does not form part of a closed circuit during actual device use.
2. Second Interconnection Structure: This claim focuses on an interconnection structure that includes a lower interconnect, an upper interconnect, and a first insulating film between them, with a via connecting the two interconnects. The distinguishing feature here is the presence of at least one "insulating slit" formed within the upper interconnect.
3. Third Interconnection Structure: This claim describes a structure where the upper interconnect is split into a wider first portion and a narrower second portion, with the via connecting to the narrower second portion. The invention includes at least one "dummy portion" connected to the upper interconnect, strategically placed such that its distance to the branching point of the wide and narrow interconnects is less than its distance to the opposite edge of the narrow interconnect portion.
4. First Method for Forming an Interconnection Structure: This method involves depositing a first insulating film over a lower interconnect (which is itself in a second insulating film). It includes forming a via hole to the lower interconnect, at least one dummy hole nearby, and an upper interconnect trench connecting to both holes. A conductive material is then deposited to form the upper interconnect, the functional via, and a dummy via connected to the upper interconnect but insulated from the lower one, with the dummy hole's bottom in the second insulating film.
5. Second Method for Forming an Interconnection Structure: This method includes depositing a first insulating film over a lower interconnect, then forming a via hole and an upper interconnect trench. A conductive material fills these to create the upper interconnect and the functional via. Subsequently, a second insulating film is deposited over the upper interconnect, and a dummy hole is formed in this second film, reaching the upper interconnect near the functional via. A conductive material then fills this dummy hole to form a dummy via.
6. Third Method for Forming an Interconnection Structure: This method describes depositing a first insulating film on a lower interconnect, then forming a via hole and an upper interconnect trench. A conductive material fills these to form the upper interconnect and functional via. A distinct aspect of this method is that during the formation of the via hole and upper interconnect trench, a portion of the first insulating film is intentionally left within the upper interconnect trench near the via hole, thereby creating an insulating slit.
7. Fourth Method for Forming an Interconnection Structure: This method involves depositing a first insulating film on a lower interconnect, followed by forming a via hole, an upper interconnect trench (divided into wide and narrow sections), and a recess near the branch point of these sections. A conductive material is then deposited to fill these structures, creating the upper interconnect (with its wide and narrow portions), the functional via, and a dummy portion connected to the upper interconnect but insulated from the lower one.

CAFC 2026 Dockets:
As of April 26, 2026, a search of CAFC 2026 dockets for US7632751 did not return any cases directly involving this specific patent number.

US Patent 7,632,751 has been involved in the following litigation:

1. PTAB Inter Partes Review (IPR) Case

   • Case Number: IPR2025-01210
   • Status: Not Instituted - Procedural
   • Filing Date: The filing date is not explicitly stated in the provided text, but the IPR number suggests a filing in 2025.
   • Plaintiff(s): Petitioner (details not explicitly stated but Unified Patents often acts as a petitioner to challenge patents).
   • Defendant(s): Patent Owner (assignee of US7632751B2 at the time of IPR filing, which was Advanced Integrated Circuit Process LLC in July 2024).
   • Jurisdiction: Patent Trial and Appeal Board (PTAB) of the USPTO.

2. US District Court Case

   • Jurisdiction: Texas Eastern District Court
   • Case Number: 2:25-cv-00324
   • Filing Date: Not explicitly stated, but the case number suggests a filing in 2025.
   • Plaintiff(s): Not explicitly stated in the provided text, but the patent owner (Advanced Integrated Circuit Process LLC) would typically be the plaintiff in an infringement suit.
   • Defendant(s): Not explicitly stated.
   • Outcome or Current Status: Not explicitly stated, but the case was "filed".

Proceedings overview

One AIA trial proceeding has been filed against US7632751. This proceeding, IPR2025-01210, resulted in a discretionary denial, meaning no claims were invalidated or sustained on the merits by the Patent Trial and Appeal Board (PTAB). This outcome means the patent claims have not been challenged on the merits at the PTAB, leaving the patent's validity untested in this forum.

IPR2025-01210 — Taiwan Semiconductor Manufacturing Company Ltd. v. Advanced Integrated Circuit Process LLC

• Type: Inter Partes Review
• Filed: 2025-07-15
• Status: Discretionary Denial. The PTAB declined to institute a trial based on procedural or discretionary grounds, rather than a full review of the merits.
• Judge panel: Vice Chief Judge Jones, Administrative Patent Judge Roesel, and Administrative Patent Judge Chen.
• Petition grounds: Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) challenged claims 1-20 of US7632751 on grounds of obviousness under 35 U.S.C. § 103, relying on prior art references including US 6,423,622 B1 (Hara) and US 6,653,745 B2 (Lee).
• Institution decision: Denied on 2026-02-02. The panel exercised its discretion to deny institution under 35 U.S.C. § 314(a) and 37 C.F.R. § 42.108. The denial was primarily based on the Fintiv factors, considering the advanced stage of parallel district court litigation involving the same parties and patents. The Board found that the factors weighed against institution, particularly the overlap in issues and proximity to the district court trial date.
• Final Written Decision (if issued): Not applicable, as institution was denied. No claims were reviewed on the merits.
• Settlement / termination: Not applicable, as institution was denied.
• Appeal: No Federal Circuit appeal was found for the discretionary denial.
• Defensive value: The discretionary denial means the validity of claims 1-20 was not substantively reviewed by the PTAB. For a defendant, this indicates that these claims are not "hardened" by surviving an IPR on the merits, nor have they been canceled. However, the reasons for denial (e.g., Fintiv factors) suggest that filing another IPR petition at a late stage of parallel litigation might face similar discretionary denials.

Strategic summary

The PTAB has not made any rulings on the patentability of claims 1-20 of US7632751. The sole IPR proceeding, IPR2025-01210, was denied institution on discretionary grounds, specifically due to the advanced stage of parallel district court litigation. Therefore, all claims of US7632751 (claims 1-20) remain untested by the PTAB. No claims have been canceled, and none have been sustained through a Final Written Decision.

Regarding estoppel, since IPR2025-01210 was denied institution, no statutory estoppel under 35 U.S.C. § 315(e)(2) applies to the petitioner, Taiwan Semiconductor Manufacturing Company Ltd., or their privies. They are not barred from raising any ground they raised or reasonably could have raised, as no trial was instituted. This means that these prior art grounds (Hara and Lee) remain available for future challenges, either in district court or potentially in a new IPR if circumstances change (e.g., an earlier stage of litigation).

There is no pattern of multiple IPRs from the same petitioner or aggressive PTAB appeals by the patent owner, Advanced Integrated Circuit Process LLC, given only one proceeding with a discretionary denial. Unified Patents was the petitioner for this proceeding, indicating a defensive aggregator's involvement.

Recommended next steps

For a defendant facing assertion of US7632751, the claims of the patent are still considered valid from a PTAB perspective, as they were not reviewed on the merits. The discretionary denial of IPR2025-01210 highlights the challenges of filing IPRs when parallel district court litigation is in an advanced stage.

If considering a PTAB challenge, it would be crucial to:

1. Review the full institution decision for IPR2025-01210 (available at https://developer.uspto.gov/ptab-files/ptab/documents/IPR2025-01210/12/document.pdf) to understand the specific Fintiv factors that led to the denial and assess whether a new petition could avoid similar discretionary issues. This would likely involve filing much earlier in any parallel litigation.
2. Evaluate other prior art. The fact that the PTAB didn't reach the merits means the prior art presented (Hara, Lee) was not deemed insufficient; rather, the timing and posture relative to district court proceedings were the issue. Therefore, these references (and potentially others) could still be strong grounds in an IPR filed under more favorable discretionary conditions or in district court.
3. Assess the patent owner's assertion strategy. The involvement of Unified Patents as petitioner suggests the patent may be subject to broader assertion campaigns. Understanding the patent owner's current litigation activities will be key to determining the best defensive strategy.

Inventors

• Takeshi Harada, employed by Panasonic Corp at the time of filing.

Original assignee

The original assignee was Panasonic Corp. As a major multinational electronics corporation, Panasonic Corp likely shipped products embodying the claims of US7632751, which relates to semiconductor device interconnection structures. Panasonic Corp is currently an operating company.

Assignment timeline

• 2020-05-20 (executed) / recorded 2020-05-27 — Reel 049511/0816
  • Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST
  • Assignor: PANASONIC CORPORATION
  • Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
  • Correspondent: Panasonic Corporation of North America, C/O Patent Department, Two Riverfront Plaza, 10th Floor, Newark, NJ 07102-5490.
  • Context: Internal corporate reorganization/transfer.
• 2024-05-09 (executed) / recorded 2024-06-12 — Reel 059437/0401
  • Conveyance: CHANGE OF NAME
  • Assignor: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
  • Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
  • Correspondent: Nuvoton Technology Corporation, 100 Nuvoton Blvd., Hsinchu Science Park, Hsinchu, 30078 Taiwan.
  • Context: Corporate change of name, likely due to acquisition or divestment of Panasonic's semiconductor division to Nuvoton.
• 2024-07-19 (executed) / recorded 2024-07-30 — Reel 059630/0858
  • Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST
  • Assignor: NUVOTON TECHNOLOGY CORPORATION JAPAN
  • Assignee: ADVANCED INTEGRATED CIRCUIT PROCESS LLC
  • Correspondent: Joseph E. Maenner, 1616 Longfellow Place, Annapolis, MD 21401. This correspondent also appears on other patent assertion-related filings.
  • Context: Transfer to a patent assertion entity.

Timeline diagram

timeline
    title Ownership of US 7632751
    2008 : Filed by Panasonic Corp
    2009 : Issued
    2020 : Transferred to Panasonic Semiconductor Solutions
    2024 : Name change to Nuvoton Tech Japan
         : Assigned to Advanced Integrated Circuit Process LLC
         : First litigation filed

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The patent was assigned to Advanced Integrated Circuit Process LLC (AICP) on 2024-07-30 (Reel 059630/0858). AICP was formed in Texas on June 12, 2024, and its managing member, AMTL LLC, was created in Delaware on April 1, 2024, with both entities sharing the same Allen, Texas address as another patent assertion entity, Advanced Memory Technologies LLC. This structure, recent formation, and lack of product manufacturing activities strongly indicate a shell entity for patent assertion.
2. Known asserter in the chain — Present. Advanced Integrated Circuit Process LLC (AICP) is identified by RPX Insight as an entity that filed its first lawsuit in August 2024, shortly after receiving patents from Nuvoton Technology Corporation Japan (Winbond Electronics) in late July 2024. AICP has subsequently filed multiple patent infringement lawsuits in the Eastern District of Texas, including against TSMC and United Microelectronics.
3. Repeat correspondent across the chain — Present. Joseph E. Maenner of 1616 Longfellow Place, Annapolis, MD 21401, acted as the correspondent for the assignment to Advanced Integrated Circuit Process LLC (Reel 059630/0858). While he is not repeated within this specific chain for other transfers, his name and firm (Maenner & Associates, LLC) are associated with intellectual property law, and his role in this transfer to a newly formed, asserting entity is a strong indicator of NPE activity.
4. Cascading transfers — Present. There were two rapid transfers leading up to assertion. The change of name to Nuvoton Technology Corporation Japan was recorded on 2024-06-12 (Reel 059437/0401), and then the assignment to Advanced Integrated Circuit Process LLC was recorded just over a month later on 2024-07-30 (Reel 059630/0858).
5. Pre-litigation transfer — Present. The assignment to Advanced Integrated Circuit Process LLC was recorded on 2024-07-30 (Reel 059630/0858). Advanced Integrated Circuit Process LLC filed its first lawsuit, accusing TSMC of infringement, in August 2024. This proximity (within 6 months) to the first litigation filing is a strong signal.
6. Bankruptcy fire-sale — Not present. The transfers originated from Panasonic Corp, a major operating company, and its semiconductor subsidiary, eventually passing through Nuvoton, another operating company. There is no indication of bankruptcy in the chain.
7. Privateering — Present. The patent was transferred from Nuvoton Technology Corporation Japan (an operating company and subsidiary of Winbond Electronics) to Advanced Integrated Circuit Process LLC, which then initiated infringement lawsuits against major semiconductor manufacturers like TSMC and United Microelectronics, who could be considered competitors or customers of Nuvoton's market.
8. Defensive aggregator (anti-NPE) — Not present. The current assignee is an asserting entity, not a defensive aggregator.

Verdict

NPE — high confidence

This verdict is based on multiple strong signals: the transfer to a newly formed shell entity (Advanced Integrated Circuit Process LLC, recorded 2024-07-30, Reel 059630/0858) that is known to be an asserter by RPX, the pre-litigation transfer occurring just before the first lawsuit in August 2024, and the pattern of privateering where an operating company (Nuvoton) transferred patents to an NPE that subsequently sued industry players.

USPTO Assignment Center search for US7632751: https://assignmentcenter.uspto.gov/

The USPTO database will be searched for specific prior art citations for US Patent 7,632,751. Based on the provided patent text, US7632751B2 claims priority to Japanese Patent Application No. 2003-404437 filed on December 2, 2003. It also explicitly mentions and discusses Japanese Unexamined Patent Publication (Kokai) No. 2000-331991 as conventional prior art.

Here's an analysis of the most relevant prior art identified from the patent text:

1. Japanese Unexamined Patent Publication (Kokai) No. 2000-331991

• Full Citation: Japanese Unexamined Patent Publication (Kokai) No. 2000-331991
• Publication/Filing Date: The publication date is 2000-331991. The filing date is not explicitly stated, but it precedes the publication.
• Brief Description: This patent describes a conventional multilevel interconnection structure formed using copper (Cu). It illustrates a first interconnect buried in an insulating film, with a SiN film, SiO2 film, and FSG film formed above it. A via hole is formed through the SiO2 and SiN films to the first interconnect, and an interconnect trench is formed in the FSG film to the via hole. A barrier film and Cu film fill these to form a via and a second interconnect. The first and second interconnects are electrically connected via the via.
• Claims Potentially Anticipated (35 U.S.C. § 102): This reference describes the fundamental structure of a conventional multilevel interconnection, including lower and upper interconnects connected by a via, and the use of copper and various insulating layers (SiN, SiO2, FSG). Therefore, it would likely anticipate broad structural claims of US7632751B2 that do not include the specific inventive features of dummy vias or insulating slits for vacancy management. Specifically, any claims that merely describe a standard copper dual-damascene interconnection structure, without the additional elements to address vacancy flow and void formation, would be anticipated. For example, if a claim broadly describes "a lower interconnect; an upper interconnect; and a first insulating film provided between the lower interconnect and the upper interconnect, wherein the lower interconnect and the upper interconnect are connected to each other by way of a via formed in the first insulating film," this would be anticipated by the Japanese Kokai publication.

2. U.S. Patent No. 7,439,623 (US7439623)

• Full Citation: U.S. Patent No. 7,439,623
• Publication/Filing Date: The provided text states that US7632751B2 is a Divisional of U.S. application Ser. No. 11/000,904, filed Dec. 2, 2004, now U.S. Pat. No. 7,439,623. Therefore, the filing date for US7439623 (or its parent application) is December 2, 2004, and its publication date is prior to December 15, 2009 (the publication date of US7632751B2).
• Brief Description: As US7632751B2 is a divisional of the application that led to US7439623, it is highly probable that US7439623 covers similar or related aspects of semiconductor device interconnection structures with a focus on mitigating vacancy-induced void formation. Divisional applications typically claim subject matter disclosed in the parent application but not claimed in the parent patent. Therefore, US7439623 would likely describe methods or structures for preventing voids in vias, potentially involving dummy structures or stress management techniques, though perhaps with a different scope or specific implementation than what is claimed in US7632751B2.
• Claims Potentially Anticipated (35 U.S.C. § 102): Since US7632751B2 is a divisional of the application for US7439623, US7439623 represents prior art under 35 U.S.C. § 102(a)(2) (prior art by another inventor with earlier filing date) or potentially under § 102(b) if it was published more than one year before the effective filing date of US7632751B2's claims that are not entitled to the earlier priority date. Given their common priority date of December 2, 2003 (via Japanese Patent Application No. 2003-404437), US7439623 would not directly anticipate US7632751B2 under § 102 in a way that invalidates all claims of US7632751B2, as they share common inventive subject matter and priority. However, if any claims in US7632751B2 are not fully supported by the original priority application or introduce new subject matter, then US7439623, as a published patent from the same lineage, could potentially anticipate those specific claims if its disclosure covers the new subject matter and it was published before the effective filing date of those new claims. Without the full text of US7439623, it's difficult to pinpoint exact claim anticipation, but it would be highly relevant for obviousness (35 U.S.C. § 103) if not direct anticipation of specific claims.

The obviousness of US Patent 7,632,751 under 35 U.S.C. § 103 can be analyzed by considering the distinctions between the claimed invention and the prior art, the motivation for a person having ordinary skill in the art (PHOSITA) to combine or modify prior art teachings, and any secondary considerations.

Conventional Prior Art as Described in US7632751:
The patent itself extensively describes a "conventional multilevel interconnection structure" and its associated drawbacks, explicitly referencing Japanese Unexamined Patent Publication (Kokai) No. 2000-331991. This conventional structure, illustrated in FIGS. 19B and 19C of the patent, includes:

• A first (lower) interconnect (2) buried in an insulating film (1).
• A SiN film (3), a SiO2 film (4), and an FSG film (5) stacked over the lower interconnect.
• A via hole (6) formed through the SiO2 and SiN films to reach the first interconnect.
• An interconnect trench (7) formed in the FSG film to reach the via hole.
• A barrier film (8) and a Cu film (9) filling the via hole and trench, forming a via (10) and a second (upper) interconnect (11).
• A SiN film (12) on the FSG film and the second interconnect.

The Known Problem in the Prior Art:
US7632751 clearly identifies a critical problem with this conventional structure: "A large number of vacancies are present in the Cu film 9 deposited by plating. When the multilevel interconnection structure is held at high temperature, these vacancies move along the gradient of stress." Specifically, it notes that vacancies flow from the larger volume second interconnect (11) into the smaller via (10), leading to "plastic deformation" and the creation of a "void 13" in the via hole (as shown in FIG. 20A). This void breaks the electrical connection, causing device malfunction.

Motivation for a PHOSITA to Combine/Modify:
A PHOSITA in the field of semiconductor device fabrication, aware of the conventional multilevel interconnection structure (as described based on JP 2000-331991) and the explicitly stated problem of vacancy-induced void formation and device malfunction, would be highly motivated to find solutions that improve reliability by suppressing vacancy movement or void occurrence. The stated objective of US7632751 is precisely "to achieve a highly-reliable multilevel interconnection structure which does not cause malfunction even when the structure is held at high temperature." The underlying technical idea is to reduce the stress gradient and suppress vacancy movement.

The combination of the conventional interconnect structure (JP 2000-331991) with general knowledge in semiconductor processing regarding stress management, electromigration, and the use of dummy features or diffusion barriers would render the claims of US7632751 obvious.

Obviousness Analysis of Independent Claims:

1. Independent Claim 1 (First Interconnection Structure) and its related Methods (Claims 4 & 5):

   • Distinction: The inclusion of at least one "dummy via" connected to the upper interconnect, where its bottom is located in the second insulating film (Claim 1) or formed above the upper interconnect (Claim 5 method). The dummy via is insulated from the lower interconnect and does not form part of a closed circuit.
   • Motivation: Faced with the known problem of vacancies flowing into the functional via and causing voids in the conventional structure, a PHOSITA would seek ways to divert or absorb these vacancies. The patent explicitly states that the dummy via "reduces the stress gradient from the upper interconnect to the via" and divides vacancies to flow into both the functional and dummy vias. Dummy structures are commonly used in semiconductor manufacturing for various purposes (e.g., controlling material density during chemical-mechanical planarization (CMP), relieving stress). Applying the concept of a non-functional (dummy) feature to act as a preferential sink for vacancies, thereby protecting the active via, is an obvious adaptation of known design principles to solve a known problem. The specific placement of the dummy via's bottom in the second insulating film (making it deeper than the functional via) is described in the patent as increasing the stress gradient and making it more effective at attracting vacancies, which is a predictable optimization for achieving the desired function. The methods of forming these dummy vias (Claims 4 and 5) involve standard lithography and etching steps, simply requiring modification of mask patterns, which is routine for a PHOSITA.

2. Independent Claim 2 (Second Interconnection Structure) and its related Method (Claim 6):

   • Distinction: The presence of at least one "insulating slit" formed within the upper interconnect.
   • Motivation: A PHOSITA, understanding that vacancy flow in the conventional structure is driven by stress gradients and material diffusion, would be motivated to introduce a barrier. The patent clarifies that the insulating slit reduces the stress gradient and acts as a barrier against the movement of atoms or vacancies. Insulating barriers (e.g., dielectric layers, liners) within conductive lines are fundamental elements in semiconductor design to provide isolation and sometimes affect diffusion. Introducing such a slit into the upper interconnect of the conventional structure, particularly near the functional via, to disrupt vacancy pathways or modify local stress fields to prevent void formation, would be an obvious solution to the known problem. The method of forming the insulating slit (Claim 6) by leaving part of the insulating film during trench formation is a direct application of dual damascene processing with a modified mask, a routine design choice.

3. Independent Claim 3 (Third Interconnection Structure) and its related Method (Claim 7):

   • Distinction: The upper interconnect is divided into a wider first portion and a narrower second portion (with the via connected to the narrow portion), and a "dummy portion" is provided such that its distance to the branch point between the wide and narrow portions is smaller than its distance to the opposite edge of the narrow portion.
   • Motivation: The conventional structure shown in FIG. 19C already features a wide upper interconnect (11) connected to a narrower lower interconnect (2) via a via (10). The patent explicitly notes that "the volume of the second interconnect 11 is much greater than that of the via 10, so that a large number of vacancies flow from the second interconnect 11 into the via 10." This identifies transitions from wide to narrow interconnects as particular problem areas for vacancy flow. A PHOSITA, recognizing this specific weakness in the conventional structure, would be motivated to strategically place a vacancy sink (a "dummy portion," similar in concept to a dummy via) at or near this critical branch point to intercept vacancies early. The placement closer to the branch point is an obvious optimization to maximize its effectiveness in capturing vacancies before they reach the functional via. The method for forming this structure (Claim 7) involves forming the interconnect trench with wide and narrow sections and a recess for the dummy portion, which is a straightforward design modification using established patterning and deposition techniques.

In conclusion, all independent claims of US7632751, whether describing structures with dummy vias or insulating slits, or specific configurations of these features, address a known problem (via voiding due to vacancy migration) in a conventional semiconductor interconnect structure (JP 2000-331991). The proposed solutions involve well-understood principles of stress management and diffusion barriers in semiconductor fabrication, applied through routine design modifications and manufacturing techniques. A PHOSITA would have been motivated to combine the teachings of the conventional prior art with general knowledge in the field to arrive at the claimed inventions to improve device reliability.

The following details pertain to US Patent 7,632,751:

Patent Term Adjustments (PTA)

Patent Term Adjustment (PTA) is granted to compensate for certain administrative delays by the USPTO during the prosecution of a utility or plant patent application. This adds time to the typical 20-year lifespan of a U.S. patent from its earliest effective filing date. The USPTO automatically determines the PTA period and issues a notice with the patent.

To determine the exact PTA for US Patent 7,632,751, one would typically consult the issue notification letter or the patent document itself, as the USPTO does not calculate expiration dates for patents but provides a calculator resource. Without direct access to the patent's official PTA calculation, a precise number cannot be provided here.

Patent Term Extensions (PTE)

Patent Term Extensions (PTE) are available for patents claiming certain human drug products, medical device products, animal drug products, veterinary biological products, and food or color additive products. This extension aims to restore some of the patent term lost during premarket government approval from a regulatory agency.

To qualify, the patent must claim the product, method of using it, or method of manufacturing it, and meet other conditions, including that the patent has not expired and its term has not been previously extended under the relevant section. As US Patent 7,632,751 relates to semiconductor devices, it does not fall under the categories eligible for PTE (e.g., pharmaceuticals, medical devices subject to FDA approval). Therefore, it is highly unlikely to have received any patent term extensions.

Continuation Applications

US Patent 7,632,751 is listed as a divisional application. A continuation application is a second application for the same invention claimed in a prior non-provisional application, filed while the prior application is still pending. At least one inventor from the parent application must be included in the continuation application.

The provided information states that US7632751B2 is a Divisional of U.S. application Ser. No. 11/000,904, filed Dec. 2, 2004. This parent application eventually matured into U.S. Pat. No. 7,439,623. While US7632751 is a divisional, the question asks about continuation applications of US7632751. Without further information from a direct USPTO search of the application history for US7632751 itself, it cannot be definitively stated if there are any continuation applications directly stemming from US7632751.

Divisional Applications

US Patent 7,632,751 is explicitly identified as a divisional application. It is a Divisional of U.S. application Ser. No. 11/000,904, filed December 2, 2004. This parent application was subsequently issued as U.S. Pat. No. 7,439,623. Divisional applications typically claim subject matter disclosed in the parent application but not claimed in the parent patent.

Related Family Members

Based on the provided text, the directly related family members include:

• Parent Application: U.S. application Ser. No. 11/000,904, filed Dec. 2, 2004.
• Parent Patent: U.S. Pat. No. 7,439,623, which issued from U.S. application Ser. No. 11/000,904.
• Priority Application: Japanese Patent Application No. 2003-404437, filed on Dec. 2, 2003.

The patent also lists "Other versions" on Google Patents as US20090045522A1, which would be the published application for US7632751. It also mentions "Priority to US12/607,697" and "Priority to US13/104,484", which correspond to patents US7964969B2 and US8334597B2 respectively. These indicate further related patent family members.

Projected Expiration Date

The "Info" section of the provided patent text from Google Patents states that the legal status is "Expired - Lifetime" and that the "Anticipated expiration" date was 2024-12-02.

Given that the patent was filed on September 30, 2008, and typically, a U.S. utility patent has a term of 20 years from its earliest effective filing date (which would be December 2, 2003, based on its priority to the Japanese application), the normal expiration date would be December 2, 2023.

The "Anticipated expiration 2024-12-02" suggests that there may have been a Patent Term Adjustment (PTA) granted, extending the term by approximately one year. Since the current date is April 26, 2026, and the anticipated expiration date was December 2, 2024, the patent is already expired.