US 7554357

I'll search for the specific patent number and any related litigation or docket activity.

Let me run a couple more targeted searches to check for any litigation or PTAB activity specifically involving this patent.

US 7,554,357 B2 — Summary

Sourcing note: The authoritative record here is the Google Patents full text supplied in the prompt (fetched 2026-09-27). I ran web searches for USPTO/CAFC records for this specific number. Those searches returned no CAFC 2026 docket and no district-court case naming 7,554,357. The only literal "7554357" hit in a court-adjacent result was an unrelated Lithuanian registry notice number (UAB "Nano linija," Pranešimo Nr. 7554357) — a different kind of identifier entirely and not this patent. I could not independently verify a live USPTO PatentCenter/Global Dossier status via search, so the bibliographic data below rests on the supplied full text.

Bibliographic data

Uncertainty flag: Google Patents labels the adjusted expiration "2026-10-19" — i.e., within weeks of today's date. Whether the patent has actually lapsed for fee non-payment, or been extended/adjusted, cannot be confirmed from the supplied record. Treat terminal-disclaimer/expiration status as unverified.

Abstract (as published)

"In one embodiment, a programmable logic device includes: a multiplexer adapted to select a compressed configuration bitstream from a plurality of external serial interface memories; a serial interface processor adapted to command the bitstream selection by the multiplexer; and a bitstream decompressor adapted to decompress the selected configuration bitstream into a decompressed configuration bitstream."

Technology in one paragraph

SRAM-based FPGAs must load configuration data at power-up from external non-volatile memory. Historically that meant a proprietary PROM, and conventional SPI-flash-based FPGAs could read from only one SPI flash. The patent teaches a master FPGA whose configuration logic engine (1) reads a compressed bitstream from multiple SPI flash memories in an interleaved fashion, (2) decompresses it on-chip, and (3) passes the decompressed bitstream on to daisy-chained slave FPGAs. The SPI processor gates a read clock so that one SPI-read-clock cycle occurs per n internal read-clock cycles, where n = number of SPI flash devices (set by a 3-bit SZ(2:0) input, max 8). A multiplexer picks among the D[0:n] serial outputs one bit per internal clock. A latch holds the SPI "leading read address," which may be loaded from internal configuration SRAM cells or written externally via a serial memory interface — enabling multi-boot/reconfiguration (swap bitstream images stored in the SPI flash).

Independent claim overviews (plain language)

Claim 1 — programmable logic device (apparatus).
A PLD containing four cooperating elements:

• a multiplexer that selects a compressed configuration bitstream coming from a plurality of external serial-interface memories;
• a serial interface processor that controls/commands that multiplexer selection;
• a latch that stores at least a portion of a leading read address signal that the serial interface processor supplies to those serial interface memories; and
• a bitstream decompressor that decompresses the selected bitstream into a decompressed configuration bitstream.

Note the latch limitation was added to claim 1: as presented in the SUMMARY the first embodiment recited only mux + serial interface processor + decompressor, but granted claim 1 additionally requires the leading-read-address latch.

Claim 7 — programmable logic device (apparatus).
A PLD with:

• a memory interface that receives a first address signal from an external source;
• configuration memory cells that store a second address signal;
• an SPI processor that selects either the first (external) or the second (internal) address and provides the selected one as the leading read address to a plurality of SPI flash memories; and
• a multiplexer that selects among the SPI flash memories' serial output signals to produce a configuration bitstream input signal, the SPI processor also commanding that selection.

In short: two-source, selectable leading read address + multi-flash output multiplexing.

Claim 11 — system.
A system comprising:

• a plurality of serial interface memory devices, each storing a configuration bitstream;
• a master FPGA coupled to those memories to receive their bitstreams, the master including a multiplexer selecting the bitstream from each of the memories plus a serial interface processor commanding that selection; and
• one or more slave FPGAs daisy-chained to the master FPGA, receiving a configuration bitstream from the master.

Literal-text observation (as-written, not corrected): Claim 11 recites "a master field programmable gate array (FPGA) ... the master PLD including" — the claim body mixes "FPGA" and "PLD" for the same element. This is reproduced verbatim from the record.

Dependent-claim map

• 1 → 2: PLD is a master FPGA feeding a daisy-chained slave FPGA.
• 1 → 3: memories are SPI flash; processor is an SPI processor.
• 3 → 4: interface receives a size command (SZ) indicating flash count; SPI processor gates read clock responsive to it.
• 1 → 5: memory interface takes a first (external) address signal into the latch.
• 5 → 6: latch also store a second address signal from configuration memory.
• 7 → 8: SPI processor gates the read clock to produce the SPI read clock.
• 8 → 9: read command sent via the HDC (high-during-configuration) signal.
• 7 → 10: latch stores at least a portion of the leading read address.
• 11 → 12: master FPGA includes the bitstream decompressor and supplies a decompressed bitstream to slaves.
• 11 → 13: memories are SPI memories.
• 11 → 14: master includes the leading-read-address latch.
• 14 → 15: memory interface external address into the latch.
• 15 → 16: latch also stores configuration-memory-provided address.
• 15 → 17: interface for the size command indicating memory count.
• 17 → 18: memories are SPI flash; processor is an SPI interface processor.

Notable prosecution / record details

• No method claim issued. The SUMMARY recites a "method of configuring at least one programmable logic device" (receiving a size signal, gating a PLD read clock according to that number, receiving a compressed bitstream from each of the number of memories). That method aspect does not appear among the granted 18 claims — all granted claims are apparatus (PLD) or system claims. Anyone relying on the SUMMARY for claim scope would be wrong.
• Prior art cited includes US 5,563,592 (Altera, compressed configuration file + decompression), US 5,872,529 (Altera, dynamic datastream compression/decompression), US 6,327,634 / 6,493,862 / 6,507,943 (Xilinx compression), US 6,563,437 (Cypress, PLD logic for decompression), US 6,525,678 (Altera, configuring a PLD), US 6,903,574 (Lattice, memory access via serial memory interface), and US 6,483,342 / US 6,773,230 (Lattice). Non-patent citations include Atmel AT17LV(A) and FPGA Configuration EEPROM datasheets, and Altera Cyclone II Device Handbook Ch. 13–14.
• Incorporated-by-reference discrepancy (literal): the specification states U.S. Pat. No. 6,483,342 is incorporated for the bitstream format, but the citation table lists US 6,483,342 as "Multi-master multi-slave system bus in a field programmable gate array (FPGA)" while "Field programmable gate array (FPGA) bit stream format" is listed as US 6,773,230. Flagging as an apparent mismatch in the record; I am not auto-correcting either number.
• Related Lattice family / subsequent art: US 7,570,078 B1 ("Programmable logic device providing serial peripheral interfaces"), US 7,631,223 B1 ("...multi-boot configuration data support"), US 7,959,208 B1 ("Flexible memory architectures for programmable logic devices"), and US 8,384,427 B1 ("Configuring multiple programmable logic devices with serial peripheral interfaces," 2013) all cite or are cited by this family.
• OCR/scan artifacts in the supplied text (reproduced verbatim in the source, not corrected here): "master EPGA 100," "slave FPOA 160," "bitstream decompressed 115," and "the master FPGA may includes." These are read-through artifacts of the PDF conversion; the substance is master FPGA / slave FPGA / bitstream decompressor.

Bottom line on the two requested searches

• USPTO record: bibliographic data above is consistent with the USPTO publication data reflected in the Google Patents record (app. 11/346,817; pub. US 2007/0182445 A1; grant 2009-06-30). I could not directly query USPTO PatentCenter in this session, so treat the current fee/expiration status as unconfirmed.
• CAFC 2026 dockets: No 2026 (or other) Federal Circuit appeal involving 7,554,357 was found. Searches for the number in CAFC contexts returned only unrelated matters. Absence of search results is not proof of absence of a docket; it means I have no authoritative confirmation of any appeal. The Lattice-related 2026 district activity surfaced (e.g., DataCloud Technologies, LLC v. Lattice Semiconductor Corporation, W.D. Tex. 7:26-cv-00083, filed 2026, voluntarily dismissed May 2026) did not identify 7,554,357 as an asserted patent in the material retrieved.

I'll search for litigation involving US patent 7,554,357.

Initial searches returned mostly unrelated "435" matches. Let me refine with targeted patent-litigation queries.

No hits yet specific to '357. Let me check the Unified Patents litigation portal and other case-list sources directly.

Summary finding

No litigation is known to me, and my searches identified none, involving U.S. Patent No. 7,554,357.

I searched for the number in the forms most likely to surface a docket record — "7554357", "7,554,357", "patent:7554357", "US7554357", and combinations with "litigation," "lawsuit," "infringement," and "Lattice Semiconductor" — across sources that aggregate patent litigation (Unified Patents litigation caselist, CourtListener/RECAP, Docket Alarm, RPX Insight, PACER Monitor, Justia, and PTAB PTACTS). Nothing in the returned results was a suit, IPR/PGR, ITC §337 investigation, or Federal Circuit appeal in which U.S. 7,554,357 is an asserted patent. I could not reach a positive docket hit for this specific number.

Because a negative is only as good as the search, here is what I can affirmatively state and what I cannot.

Patent identifiers (as given, taken literally)

Case-by-case list

There are no cases to list. For completeness, the requested fields return empty:

• Plaintiff(s): — none identified
• Defendant(s): — none identified
• Jurisdiction: — none identified
• Case number: — none identified
• Filing date: — none identified
• Outcome / status: — none identified

Important caveat on false positives (do not conflate these)

My searches repeatedly surfaced matters that involve different patents whose numbers are similar or whose short form is also "the '435 patent." These are not US 7,554,357 and I am explicitly excluding them:

• WSOU Investments, LLC v. Dell Technologies, Inc., No. 6:20-cv-00476 (W.D. Tex.) — asserts US 7,565,435 B2 (network switching), dismissed with prejudice April 18, 2024. Different patent.
• Sam's West, Inc. / Walmart Apollo, LLC v. BJ's Wholesale Club Holdings, Inc., No. 6:22-cv-00587 (M.D. Fla.) — the "'435 Patent" in that docket is US 7,565,435 (PTAB final written decisions finding claims unpatentable; Fed. Cir. affirmed April 13, 2026). Different patent.
• Stratasys v. Bambu Lab (E.D. Tex.) — asserts US 7,555,357, a 3D-printing patent. Different patent (note the transposed digits: 7,555,357 vs. 7,554,357).
• Amtel / Epson / NEC matters — unrelated patents and numbers (e.g., US 7554357 appearing as a docket/registration number, a JP publication number, and an IEEE DOI 10.1109/CHICC.2016.7554357, none of which are this patent).

Enforcement context worth noting

• The only third-party document activity I located for US 7,554,357 is citation, not litigation: the specification is cited as prior art in DE 10 2012 205 160 A1 (Robert Bosch GmbH, published 2013-10-02), which is itself in the "cited by" list on the patent's face.
• The patent has also been cited in subsequent Lattice filings (e.g., US 7,954,208 B1; US 8,384,427 B1, "Configuring multiple programmable logic devices with serial peripheral interfaces"), which are continuations of the same technical line, not adversarial proceedings.
• Assignee history shows only security-interest/release events (Jefferies Finance LLC 2015; release 2019; Wells Fargo as administrative agent 2019) — corporate financing, not litigation.

Confidence and limits

• Confidence that no litigation is reported in the sources I searched: moderate-to-high. The number is distinctive and the searches returned nothing on point.
• Confidence that no litigation has ever occurred: not high. I was not able to open a live, authoritative docket for this patent number (a direct Unified Patents / CourtListener / Docket Alarm patent-number query returned no matching record in the retrieved results), and free search indices do not capture every case, every sealed filing, every state-court or foreign action, or actions filed under a pre-grant publication number. Patent-assertion suits involving Lattice have typically arisen against Lattice as defendant (e.g., Commonwealth Research Group LLC v. Lattice Semiconductor, D. Del. 11-655; Bell Semic v. Lattice; DataCloud Technologies v. Lattice, W.D. Tex. 7:26-cv-00083), and '357 has not appeared among the patents asserted in those.
• To convert this negative into a verified negative, I would pull the patent's "Litigation" tab on a paid docket service (Docket Navigator, Lex Machina, RPX) and independently query PACER/Unified Patents by the 7,554,357 number and by both pre- and post-grant publication numbers. I have not done that here.

Bottom line: on the record available to me, U.S. Patent No. 7,554,357 has never been asserted in reported litigation — no district court case, no IPR/PGR, no ITC investigation, and no appeal. Please treat that as "no known litigation" rather than a certified clean title; verify against a live docket service if the answer is decision-critical.

I'll verify the ODP result against public sources before reporting.

Let me run a couple more targeted checks for any proceeding or appeal tied to this patent.

Proceedings overview

Zero AIA trial proceedings have ever been filed against US 7,554,357 — 0 active, 0 with claims invalidated, 0 with claims sustained, 0 settled, 0 institution denials. The canonical source for this task (the structured "PTAB proceedings on file" block sourced from the USPTO Open Data Portal) returns an empty list, and my independent searches (Google Patents prosecution/legal-events data, general web, CourtListener) surfaced no IPR, PGR, or CBM naming this patent and no Federal Circuit appeal of any PTAB decision on it.

The bottom-line defensive posture is therefore not "the patent has survived IPRs and is hardened" and not "claims are dead." It is: the patent's validity has never been tested at the Board, but that is largely academic because the patent is at the very end of its term. Google Patents' record lists the patent as Active with an adjusted expiration of 2026-10-19 — roughly three weeks from today (2026-09-27). A defendant facing assertion today is looking at a near-zero remaining term, not at a validity fight.

Verification steps taken (so you can reproduce / challenge them):

• Structured ODP "PTAB proceedings on file" block in the prompt: empty (no proceedings indexed).
• Google Patents legal-events and "Cited By" sections for US 7,554,357: no PTAB trial events; the "Cited By" entries are later Lattice patents (e.g., US 8,384,427), not proceedings.
• Web searches for IPR/PGR identifiers tied to the patent number or to the patent title ("Efficient configuration of daisy-chained programmable logic devices"): no hits.
• Federal Circuit / CourtListener search for the patent: no appeal found (the only Lattice-adjacent appellate hit was Papst Licensing GmbH & Co. KG v. Lattice Semiconductor Corp., a district-court matter on unrelated patents).

Caveat, stated plainly: an absence of hits in web search is not a forensic negative. Web indexes do not comprehensively cover every PTAB paper. If you need a bulletproof negative, pull the patent's file wrapper in USPTO Patent Center (https://patentcenter.uspto.gov — application 11/346,817) and run the number through PTAB E2E / PTAB Center (https://ptacts.uspto.gov). Neither the ODP block nor my searches indicate anything to find.

No proceedings to report — items that are not PTAB proceedings (do not misread these)

• Certificate of Correction, 2010-04-20. A certificate of correction issued ~10 months after grant. This is a prosecution/post-grant administrative event, not an AIA trial. It matters to you for a different reason: if it corrected claim text, the operative claim language is the corrected language. Pull the certificate before you build any claim chart.
• Cited-by patents (Lattice-family). US 7,957,208, US 8,384,427, US 7,570,078, US 7,631,223 and similar are later Lattice patents that cite or incorporate 7,554,357. Citations are not challenges. In particular, US 8,384,427 expressly incorporates US 7,554,357 by reference — a family/continuation signal, not a validity attack.
• Security-interest and release assignments (Jefferies Finance 2015-03-18; Wells Fargo 2019-05-21) are UCC/security filings, not proceedings.
• Maintenance fees. 4th-year, 8th-year and 11th/12.5-year fees were paid (last payment event 2020-12-30, 12th-year). No lapse-for-non-payment risk and no intervening-rights/expired-for-fee argument available.

6.5 — Defensive value of the null result

• No IPR estoppel exists against anyone. Because no Final Written Decision has ever issued on this patent, 35 U.S.C. § 315(e)(2) estoppel has never attached to any petitioner or its privies/real parties in interest. Any defendant retains the entire universe of § 102/§ 103 prior-art (patents and printed publications) grounds in district court — nothing is estopped.
• But there is also no IPR short cut. You cannot point to a Board FWD canceling claims, because none exists. Any invalidity theory must be litigated in court or raised in a fresh AIA petition.
• The real defense is term, not validity. With an adjusted expiration of 2026-10-19 per the Google Patents record (and the bare 20-year term from the 2006-02-03 filing having run out on 2026-02-03), almost all of the enforceable window has closed. Note the interplay: the § 286 six-year damages lookback is measured from your service date, so a pre-suit licensee/infringer can face a six-year tail even on an expiring patent — but a demand letter sent now has very little remaining runway.

Strategic summary

Claim status: all 18 claims are UNTESTED. US 7,554,357 has 18 claims. The independent claims are claim 1 (multiplexer + serial interface processor + latch + bitstream decompressor), claim 7 (memory interface + configuration memory cells + SPI processor selecting between first/second address signals + multiplexer selecting from SPI flash serial outputs), and claim 11 (system: multiple serial interface memories + master FPGA with multiplexer and serial interface processor + daisy-chained slave FPGAs). No claim — independent or dependent — has been canceled, confirmed, or construed by the Board, because no petition has ever been filed. There is no PTAB-fixed claim construction to borrow and no Board finding to cite. Contrast this with the typical "hardened patent" narrative: here the reason there is no adverse record is that no one has ever challenged it, not that challengers tried and failed.

Estoppel landscape. Nothing is barred by § 315(e)(2), and nothing needs to be. Because no FWD exists, no petitioner-side estoppel runs against an alleged infringer's privies either. Practically: your IPR-available art is identical to your litigation-available art, and you are not boxed out of any § 102/§ 103 ground. That is a genuinely favorable estoppel posture — but the value of that freedom is capped by how little term remains. Conversely, note § 315(b): if you have been served with a complaint alleging infringement, you have one year to file an IPR; given the 2026-10-19 expiration, that clock is almost certainly moot.

Pattern signals. There is no pattern to read: no repeat petitioner, no serial petitions, no joinder, no defensive aggregator (no Unified Patents / RPX-style IPR found against this patent). The patent owner (Lattice Semiconductor, now subject to a Wells Fargo security interest) has never litigated a PTAB appeal on this patent. For a technology of this vintage (SPI-flash configuration of daisy-chained PLDs), the absence of any IPR across ~17 years of enforceability is a meaningful signal: this patent was evidently never the centerpiece of an assertion campaign large enough to attract a petition — and its term is now spent.

Recommended next steps

1. Confirm the expiration date first — it likely ends the analysis. Pull the front page and the Patent Term Adjustment/extension statement in Patent Center (application 11/346,817) and verify whether the operative expiration is 2026-10-19 (as Google's adjusted-expiration field states) or the unadjusted 2026-02-03. Either way, term ends within weeks of today.
2. Pull the 2010-04-20 Certificate of Correction before reading any claim literally. If it amended claim text, the corrected language governs, and the front-page claim text you reproduce in a chart must match it.
3. If a demand letter cites this patent, respond on term and damages, not on validity. Ask for the asserted claims (likely 1, 7, and/or 11), the accused instrumentalities, and the royalty base for any pre-expiration period, and note that the § 286 six-year lookback is the only meaningful exposure left.
4. Do not spend IPR money without a scope check. A petition filed now would face a patent expiring before any FWD could issue (the Board's statutory 1-year trial deadline runs from institution under § 316(a)(11)), which is a strong practical reason for discretionary denial and a poor use of budget. Confirm with the patent's exact expiry before funding anything.
5. Verify the negative yourself if the stakes justify it. Query the patent number in PTAB E2E / PTAB Center (https://ptacts.uspto.gov) and Patent Center (https://patentcenter.uspto.gov), and a party-name search (Lattice Semiconductor) in CourtListener (https://www.courtlistener.com) for any appeal. The ODP structured list plus these three checks are the defensible record: no PTAB activity on file.

Sources consulted: Google Patents, US 7,554,357 (https://patents.google.com/patent/US7554357/en) — legal events, cited-by/citations, family and expiration fields; USPTO ODP structured "PTAB proceedings on file" block (empty); USPTO Patent Center and PTAB E2E (recommended verification endpoints); CourtListener (no Federal Circuit appeal located). No PTAB proceeding number, judge panel, ground, or Final Written Decision is stated above because none exists — stating otherwise would be fabrication.

I'll research the assignment record for US 7554357 across the sources I can reach.

Let me dig for the specific assignment record details, the correspondent of record, and any litigation or NPE involvement.

I hit the tool-step limit on follow-up queries, so the report below rests on (a) the authoritative Google Patents legal-events extract you supplied and (b) what my searches could confirm. Where a field could not be verified, I say so rather than guess.

Inventors

All three executed the assignment to Lattice between 2006-01-30 and 2006-02-02, days before the 2006-02-03 filing date — the classic employee-invention assignment, not a later cleanup.

Unusual-pattern check: the "all inventors bolt within 12 months" precursor to a fire-sale is not present. Search results surface Britton and Chen as co-inventors on Lattice-assigned applications filed years later (e.g., app. 13/076,300), which is inconsistent with the inventors quitting near filing. Caveat: that evidence comes from a patent-indexing aggregator (radaris.com) and the WO 2005/048454 applicant listing, not from employment records; treat "still employed" as likely, not proven.

Original assignee

Lattice Semiconductor Corporation — the entity named on the issued patent and the only entity that has ever held title.

• Business: fabless supplier of low-power FPGAs, CPLDs and programmable mixed-signal devices (EC/ECP, MachXO, LatticeSC families). Founded 1983; HQ Hillsboro/Portland, Oregon.
• Product embodiment: Yes. The claims cover SPI-flash configuration of daisy-chained PLDs, which is a shipped configuration mode of Lattice's SRAM-based FPGA families. Lattice's own US 8,384,427 B1 ("Configuring multiple programmable logic devices with serial peripheral interfaces") expressly incorporates US 7,554,357 by reference and describes it as a conventional daisy-chain technique alongside U.S. Pat. No. 7,397,272 — i.e., Lattice built follow-on products and patents directly on this disclosure.
• Current status: Operating. NASDAQ: LSCC; acquired Silicon Image, Inc. on 2015-03-10; per its 10-K, its patents "expire at various times between 2020 and 2038," and the patent at issue here (Google's adjusted-expiration field) runs to 2026-10-19, still active as of today (2026-09-27). No bankruptcy, dissolution, or wind-down found.

Assignment timeline

Scope note: The USPTO Assignment Center / assignment.uspto.gov record for this patent is surfaced in the Google Patents legal-events extract. Four records appear; two are true title documents (the inventor assignment; the financing release) and two are security interests (liens), which are not ownership transfers. I could not retrieve the recorded correspondent (attorney/firm) for any of the four — the legal-events extract omits correspondence data, and the Assignment Center's browser app could not be queried in this session. I am flagging that as an unresolved field rather than inventing a name.

• 2006-01-30 → 2006-02-02 (executed) / recorded 2006-03-14 — Reel 017304/0674

  • Conveyance: Assignment (Assignment of Assignors' Interest)
  • Assignor: Chen, Zheng; Britton, Barry; Scholz, Harold
  • Assignee: Lattice Semiconductor Corporation (Oregon)
  • Correspondent: not available in the record I could reach — this is the one link where a correspondent attorney/firm would be most informative; I could not confirm it.
  • Context: ordinary employee-invention assignment to the operating employer, recorded ~6 weeks after filing.

• 2015-03-10 (effective) / recorded 2015-03-18 — Reel 035223/0001

  • Conveyance: Security Agreement (security interest, not a title transfer)
  • Assignor (grantor): Lattice Semiconductor Corporation; also Silicon Image, Inc., SiBEAM, Inc., DVDO, Inc. (as co-grantors)
  • Assignee (secured party): Jefferies Finance LLC (New York)
  • Correspondent: not available.
  • Context: securitization — blanket lien on the Lattice IP portfolio securing the credit facility used in connection with the Silicon Image acquisition (effective date coincides exactly with the 2015-03-10 close).

• 2019-05-17 (effective) / recorded 2019-05-21 — Reel 049827/0326

  • Conveyance: Release by Secured Party
  • Assignor: Jefferies Finance LLC
  • Assignee (released party): Lattice Semiconductor Corporation, Silicon Image, Inc., SiBEAM, Inc., DVDO, Inc.
  • Correspondent: not available.
  • Context: lien discharge on refinancing — extinguishes the Jefferies encumbrance; Lattice's ownership is undisturbed.

• 2019-05-17 (effective) / recorded 2019-05-21 — Reel 049980/0786

  • Conveyance: Security Agreement (security interest, not a title transfer)
  • Assignor (grantor): Lattice Semiconductor Corporation
  • Assignee (secured party): Wells Fargo Bank, National Association, as Administrative Agent (Colorado)
  • Correspondent: not available.
  • Context: securitization — replacement credit facility; Wells Fargo takes the blanket IP lien the same day Jefferies releases.

Non-assignment events on the record (for completeness): 2008-12-06 fee-payment/entity-status entry; 2009-06-10 patent grant; 2010-04-20 certificate of correction; 2012-10-01 4th-year maintenance fee; 2016-12-30 8th-year fee; 2020-12-30 12th-year fee. No ownership change accompanies any of these.

Bottom line: there is no recorded post-issuance transfer of title for US 7,554,357. The only two title documents in the chain are the 2006 inventor→Lattice assignment and the 2019 lien release; everything else is collateral.

Timeline diagram

timeline
    title Ownership of US 7554357
    2006 : Filed by Lattice Semiconductor
         : Inventors assign rights to Lattice
    2009 : Patent issued to Lattice
    2015 : Jefferies takes portfolio lien
    2019 : Jefferies lien released
         : Wells Fargo takes portfolio lien
    2026 : Patent reaches adjusted expiry

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. No "IP / Holdings / Licensing / Ventures" assignee appears. The only assignee of title is Lattice Semiconductor Corporation itself (Reel 017304/0674). No registered-agent address, no single-purpose LLC.

2. Known asserter in the chain — Not present. Chain entities are Lattice Semiconductor Corp., Jefferies Finance LLC (a lender), and Wells Fargo, N.A. (a lender). None appears on the Acacia / Marathon / IV / IPNav / Wi-LAN / Conversant / Vringo / Pendrell / Round Rock / Spangenberg lists. Jefferies and Wells Fargo are secured creditors, not patent owners.

3. Repeat correspondent across the chain — Unclear (unable to test). The correspondence field was not obtainable for any of Reels 017304/0674, 035223/0001, 049827/0326, or 049980/0786. I therefore cannot either assert or rule out a recurring filing attorney. This is a genuine gap, not a negative finding — the signal can only be scored once correspondents are pulled from the Assignment Center detail pages.

4. Cascading transfers — Not present. Four recorded events span 13 years (2006→2019), and only one is a title transfer. No chained LLCs, no sub-24-month succession, no common-principal pattern.

5. Pre-litigation transfer — Not present. I found no infringement suit naming US 7,554,357. Its litigation-adjacent footprint is purely defensive/technical: it is cited as prior art by DE 10 2012 205 160 A1 (Robert Bosch GmbH) and incorporated by reference in Lattice's own US 8,384,427 B1. No transfer precedes any assertion because there is no assertion to precede. (Caveat: my docket sweep was not exhaustive; a district-court or ITC complaint outside the sources I reached could have been missed.)

6. Bankruptcy fire-sale — Not present. No Chapter 7/11 filing by Lattice or by any assignor; Lattice remained an operating NASDAQ issuer with a 12th-year maintenance fee paid 2020-12-30.

7. Privateering — Not present. No operating-company→NPE transfer; no third party asserting on Lattice's behalf. Lattice's actually-litigated patent activity is a 2016 Technicolor HDMI complaint in Lattice's own name (per its 10-K), i.e., first-party assertion, and it does not involve this patent.

8. Defensive aggregator — Not present. Chain does not terminate at RPX, AST, LOT, Unified Patents or OIN. It terminates at the original operating company, with its lender holding a lien.

Verdict

Insufficient data (per the rubric's literal definition — the only recorded title transfer is the original inventor→Lattice assignment; there is no NPE chain to evaluate).

Justification: Reel 017304/0674 (recorded 2006-03-14) is the sole ownership assignment, moving rights from inventors Chen, Britton and Scholz to Lattice Semiconductor Corporation, which is corroborated as an operating company by its continued product line and by Lattice's own follow-on patent US 8,384,427 B1 incorporating this patent. The only later records — Reel 035223/0001 (Jefferies security interest, effective 2015-03-10), Reel 049827/0326 (Jefferies release, 2019-05-17), and Reel 049980/0786 (Wells Fargo security interest, 2019-05-17) — are financing liens and a lien discharge, not transfers of title, and both secured parties are commercial lenders rather than asserters. No NPE, shell LLC, cascading transfer, bankruptcy sale, or infringement suit was found. The residual uncertainty is (i) the unretrievable correspondent of record on all four reels and (ii) the non-exhaustive nature of my litigation sweep — both of which are the only things that could change this call.

Verify at:

• USPTO Assignment Center — https://assignmentcenter.uspto.gov/
• Legacy Assignment Search — https://assignment.uspto.gov/patent/index.html (search patent number 7554357)
• Google Patents (source of the reel/frame data above) — https://patents.google.com/patent/US7554357/en

I'll verify the patent via search and gather details on the most relevant cited references.

Let me verify the remaining key cited references.

Search verification — US 7,554,357

Search of the U.S. patent record confirms the target document (Google Patents / USPTO PatentCenter data):

(Note: the OCR text of the Google Patents reproduction renders "FPGA" as "EPGA"/"FPOA" in places — I read these literally as FPGA.)

The patent has 18 claims. For § 102 purposes they break down into four families:

• A — Multi‑memory SPI + mux + decompressor: claims 1, 2, 3, 4
• B — Programmable leading read address (memory interface / config cells → latch): claims 5, 6, 7, 8, 9, 10
• C — Daisy‑chained system (master FPGA + slaves): claims 11, 12, 13, 14, 15, 16, 17, 18

Important analytic caveat

No single cited reference appears to anticipate any independent claim in full. Claim 1 requires the concurrence of (a) a multiplexer selecting a compressed bitstream from a plurality of external serial interface memories, (b) a serial interface processor commanding that selection, (c) a latch storing at least a portion of a leading read address, and (d) a bitstream decompressor. The cited art splits across these elements (compression/decompression art; multi‑channel memory art; config‑memory‑access art). This is consistent with the patent having issued over these references. The analysis below therefore maps which claims each reference is most relevant to, i.e., which claim elements it can supply in a § 102 single‑reference or (more likely) § 103 combination challenge. I flag where I have lower confidence.

Tier 1 — Most relevant prior art

1. US 5,563,592 A — Altera

• Citation: Cliff et al., "Programmable logic device having a compressed configuration file and associated decompression," US 5,563,592, filed 1993‑11‑22, granted 1996‑10‑08.
• Disclosure: Seminal PLD compression scheme — configuration file compressed, stored in an external serial EPROM, decompressed by a decompression circuit on the PLD, then used to program the device. Claims recite an "electronic decompression circuit" on the device and a serial EPROM storage device; also notes storing more than one configuration file in a single memory element.
• Potentially anticipates: claim elements of claim 1 and claim 12 (the "bitstream decompressor adapted to decompress the selected configuration bitstream"). Strongest § 102 hit against the decompressor limitation. It does not disclose a mux selecting among a plurality of external serial memories, nor the leading‑read‑address latch.

2. US 6,028,445 A — Xilinx

• Citation: Lawman et al., "Decoder structure and method for FPGA configuration," US 6,028,445, filed 1997‑12‑29, granted 2000‑02‑22.
• Disclosure: Configures a first portion of an FPGA as a decoder; encoded (e.g., compressed) configuration data is transferred to the decoder, which decompresses/reconfigures the rest of the FPGA. Also covers embedded non‑volatile memory and internal configuration access port.
• Potentially anticipates: claim 1 / claim 12 (decompressor within the PLD; recognizing/decompressing encoded config data). No multi‑memory mux; no SPI; no read‑address latch.

3. US 6,903,574 B2 — Lattice Semiconductor (expressly incorporated by reference in the patent)

• Citation: Chen, Scholz, Zhang, "Memory access via serial memory interface," US 6,903,574 B2, filed 2003‑07‑29 (10/629,512), granted 2005‑06‑07.
• Disclosure: Serial memory interface per special functional block giving access to configuration memory cells after configuration to write system‑bus data into them; system bus register file; programmable interconnect. This is the very architecture the specification cites as enabling the user‑writable leading read address.
• Potentially anticipates: claims 5, 6, 10, 14, 15, 16 (memory interface / configuration memory cells / latch storing the address, writable post‑configuration). Note the shared inventor (Chen) — this is closely related work. It does not disclose SPI flash memories or the multi‑memory multiplexer.

4. US 6,483,342 B2 — Lattice Semiconductor (expressly incorporated by reference)

• Citation: Britton et al., "Multi‑master multi‑slave system bus in a field programmable gate array (FPGA)," US 6,483,342 B2, priority 2000‑05‑26, granted 2002‑11‑19.
• Disclosure: Embedded multi‑master/multi‑slave system bus with an external microprocessor interface (MPI) permitting direct access to embedded elements regardless of configuration state; also discloses the configuration bit‑stream format (header, ID frame, address frame, data frame, postamble) — the format the '357 patent relies on to signal compression.
• Potentially anticipates: elements of claims 5/7/10 (external source writing configuration/address data) and background for claims 1/7 (bitstream frame structure). No SPI flash; no mux across multiple serial memories.

5. US 6,772,230 B2 — Lattice Semiconductor

• Citation: "Field programmable gate array (FPGA) bit stream format," US 6,772,230 B2, 2000‑05‑26, granted 2004‑08‑03.
• Disclosure: Multi‑format FPGA bit stream (header / ID frame / address / data / postamble) loadable from an external interface; embedded system bus context.
• Potentially anticipates: the bitstream‑format/frame elements used in claims 1/7/9 (e.g., identification frame; command/address frames). Low standalone § 102 value.

Tier 2 — Compression / decompression art (claim 1 / 12 elements)

These establish that on‑chip decompression of compressed PLD configuration data was well known by the 2006 priority date. They are anticipation candidates only for the decompressor limitation of claims 1 and 12; each lacks at least the plurality‑of‑serial‑memories mux and the address latch.

Tier 3 — Interface / memory / multi‑channel art (claims 3–9 elements)

None of these discloses the specific interleaved multiplexing of a compressed bitstream from N SPI flash memories gated one clock per N recited in claim 1/4/8.

Tier 4 — Clock generation / gating art (claims 4 and 8)

• US 6,885,227 B2 — Lattice, "Clock generator with skew control," 2003‑07‑29 / 2005‑04‑26.
• US 7,019,577 B2 — Lattice, "Clock generator," 2003‑07‑29 / 2006‑03‑28.
• US 7,034,599 B1 — Lattice, "Clock generator with skew control," 2003‑07‑29 / 2006‑04‑25.

These are relevant to the internal clock (140) / read‑clock generation and the gated RCLK concepts of claims 4 and 8, but do not disclose gating a read clock by a "number of SPI flash memories" size signal.

Tier 5 — Remaining cited references (marginal / background)

Non‑patent citations (from the '357 record)

The three vendor datasheets (Atmel AT17LV, Atmel FPGA Config EEPROM, Altera Cyclone II handbook) are the most substantive non‑patent art; they are printed publications predating the 2006‑02‑03 priority date.

Bottom line — best § 102 candidates by claim

Honest limitations: Without full claim‑by‑claim element mapping against the complete text of every cited reference, these are candidacy assessments, not adjudicated anticipation findings. The two references expressly incorporated by the '357 specification (US 6,483,342 and US 6,903,574) and the two decompression pioneers (US 5,563,592 and US 6,028,445) are the citations most likely to be relied upon; the plurality‑of‑SPI‑flash multiplexer with interleaved data and the latch‑stored leading read address — the apparent point of novelty — do not appear to be fully disclosed by any single cited item, which is consistent with the claim set that actually issued.

I'll ground my characterization of the cited references before building the combinations.

Scope and method

This analysis addresses the patentability of US 7,554,357 B2 ("Efficient configuration of daisy-chained programmable logic devices," Lattice Semiconductor; filed 2006‑02‑03; granted 2009‑06‑30) under 35 U.S.C. § 103(a) (pre‑AIA applies, since the effective filing date precedes 2013‑03‑16).

Per the strict rule, I have interpreted all identifiers literally as they appear. Note that the source page's rendering of the patent contains OCR artifacts (e.g., "master EPGA 100," "slave FPOA 160," "bitstream decompressed 115"). I treat these as the literal strings on the page but analyze the claims as recited (claim 1 recites "programmable logic device," claim 11 recites "master field programmable gate array (FPGA)" while its body inconsistently says "master PLD" — I flag that but do not correct it).

I use only the references appearing in the page's Prior Art sections: the "Patent Citations (29)" list, the 27‑item "Citations" list, and the "Non‑Patent Citations (7)" list. I verified the substance of several key references by live search (URLs cited below); for those I did not retrieve full text, I characterize them by title only and mark that limitation explicitly rather than inventing disclosures.

1. Legal framework and level of ordinary skill

• Graham v. John Deere Co. factors: scope/content of prior art; differences between prior art and claims; level of ordinary skill; secondary considerations.
• KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007): a claimed combination is obvious where the elements were known and combined "according to known methods" to yield "predictable results"; a "design need or market pressure" or a "finite number of identified, predictable solutions" supports obviousness. No express teaching, suggestion, or motivation in the references is required.
• POSITA (my proposed definition): a B.S. in EE/CS plus ~2–4 years of experience in FPGA/PLD configuration and external configuration memory interfaces, or equivalent; familiar with the SPI protocol, serial configuration EEPROM/flash (e.g., EPCS devices), bitstream compression, and daisy‑chain master/slave configuration.

High‑confidence legal facts about this patent: it was granted 2009‑06‑30, has an Active status with an adjusted expiration of 2026‑10‑19, and a Certificate of Correction dated 2010‑04‑20 appears in the Legal Events (source: https://patents.google.com/patent/US7554357/en). Grant of the patent is not evidence of non‑obviousness and does not preclude a § 103 challenge.

2. The prior art of record, grouped by the element it supplies

Date/status caveats (important, and I will not hide them):

• U.S. Appl. No. 11/494,862 (Booth et al., filed Jul. 28, 2006) and U.S. Appl. No. 11/530,620 (Callahan et al., filed Sep. 11, 2006) appear in the Non‑Patent Citations list but were filed after the '357 filing date (2006‑02‑03) and therefore are not § 102 prior art to the '357 claims (absent earlier priority not evident from this page). I would exclude them from any rejection.
• U.S. Appl. No. 10/809,658 and 11/243,255 (Tang) and US 2006/0143366 A1, US 7,242,221, US 7,088,131 are usable only on their earliest effective filing dates (§ 102(e)).
• US 7,570,078 and US 8,384,427 appear on the page only under "Families Citing this family"/"Cited By," with post‑2006 priority dates — they are not prior art to this patent. (They surfaced in my search and are Lattice SPI‑configuration art, but they cannot be used.)

3. Ground 1 — Claim 1 (independent claim)

Claim 1 requires: (a) a multiplexer to select a compressed configuration bitstream from a plurality of external serial interface memories; (b) a serial interface processor commanding the multiplexer selection; (c) a latch storing at least a portion of a leading read address signal provided by the serial interface processor to the plurality of serial interface memories; and (d) a bitstream decompressor.

Proposed primary combination: US 6,028,445 (Xilinx) in view of US 5,563,592 (Altera) and the Altera "Configuring Cyclone II Devices" (July 2005) NPL, further in view of US 6,564,285 (Intel) and US 6,903,574 (Lattice).

• (d) Decompressor — met directly by US 5,563,592 (compressed configuration file stored in a serial EPROM, decompressed by a decompression circuit to program the PLD; the decompression circuit may reside on the PLD), and by US 6,327,634 (decompression in the FPGA itself). The Altera Cyclone II NPL independently establishes that on‑device decompression of a compressed bitstream from a serial configuration device was commercial practice by July 2005.
• (b) Serial interface processor commanding selection — met by the configuration controller/master logic taught in US 6,028,445 and by the AS‑scheme controller in the Cyclone II NPL, which drives DCLK, ASDO, and nCSO and issues the serial operation commands and read addresses; the same controller logic necessarily directs which data source is consumed. US 6,903,574 supplies an explicit serial interface/serial‑memory‑interface processor with ADDR/RD/WR/CLK control signals.
• (c) Latch storing a leading read address — met in substance by the ALTERA AS scheme, where the FPGA "uses the serial clock (DCLK) and serial data output (ASDO) pins to send operation commands and/or read address signals to the serial configuration device," combined with US 6,903,574's SMI register/latch architecture (SYSTEM BUS REGISTER FILE 102 + serial memory interface 104 with ADDR signal), which the '357 patent itself incorporates by reference. US 6,564,285 supplies address latching/registration in a synchronous non‑volatile memory interface.
• (a) Multiplexer over a plurality of external serial interface memories — this is the element not squarely disclosed by any reference I could confirm, and it must be supplied by an explicit obviousness rationale:
  • US 6,327,634 (of record) states that for the largest FPGAs "several PROMs may be required" to store a single bitstream — i.e., the art recognized the multi‑memory problem the '357 patent addresses.
  • US 6,564,285 (of record) teaches a synchronous non‑volatile memory in which addresses of a burst are applied one per clock and data are output sequentially in subsequent clock periods — the selection/de‑interleaving of clocked memory outputs.
  • US 7,062,615 (of record) teaches arbitration/selection among multiple memory channels.
  • The Cyclone II NPL teaches multiple configuration devices chained/shared (master + slaves with nCE/nCEO; and a figure where the configuration device's DATA and DCLK are connected in parallel to multiple devices).
  • The '357 specification's own Background is an admission that "Conventional FPGAs using SPI flash as their external configuration memories are limited … to downloading their configuration bit stream from just a single SPI flash." Under KSR, a known deficiency in the field, addressed by known elements (a multiplexer and multiple memories) with predictable results (more storage), is a classic obviousness rationale.

Conclusion, Ground 1: Claim 1 is arguably obvious but not unavoidable — the examiner would have to (i) treat the Altera AS serial configuration device as a "serial interface memory," (ii) read the configuration controller as the claimed "serial interface processor," and (iii) supply the multiplexer‑over‑plural‑memories from the capacity motivation in US 6,327,634 / arbitration teaching of US 7,062,615 / burst‑address teaching of US 6,564,285. The combination is strongly supported on motivation and predictability; the weakest link is the literal absence of a multiplexed plural‑serial‑memory front end in the art of record.

4. Ground 2 — Claims 2, 3, 4

Claim 2 (master FPGA providing the decompressed bitstream to at least one daisy‑chained slave FPGA): met by the Cyclone II handbook ch. 13, "Multiple Device AS Configuration" (master device controls the chain; nCEO of one device drives nCE of the next; the cycled compressed/uncompressed data goes down the chain) combined with US 5,563,592/US 6,327,634 decompression. This is a strong rejection.

Claim 3 (memories are SPI flash memories; processor is an SPI processor): The Cyclone II NPL and the Atmel AT17LV(A) / FPGA Configuration EEPROM Memory NPLs show serial configuration memories with a four‑pin serial interface (DCLK/DATA/ASDI/nCS) and read commands/addresses; the '357 Background itself concedes that SPI flash configuration of FPGAs was conventional. Substituting an SPI‑flash serial memory for the known serial configuration EEPROM is a known, expected substitution of one known serial‑interface non‑volatile memory for another, with the predictable benefit of lower cost (expressly the motivation stated in the '357 Background and in the art generally). Moderate‑to‑strong rejection, though the art of record arguably does not name "SPI flash" for configuration; it may be necessary to rely on the applicant's own admissions plus the AT17LV/Cyclone documents.

Claim 4 (interface for a size command indicating the number of SPI flash memories; SPI processor gates a read clock responsive to the size command): This requires (i) an input indicating how many memories, and (ii) read‑clock gating responsive to that number. Related art of record:

• US 6,564,285 teaches a clock signal provided to the flash chip and address bursts clocked one per period (the clock‑gating/clocking‑per‑memory notion).
• US 6,885,227 / US 7,019,577 / US 7,034,599 (Lattice) are clock‑generator/clock‑control references of record (I did not retrieve full text; I do not assert they gate a read clock in response to a memory count).
• US 6,903,574 supplies the SMI address/ID mechanism (SMI_ID[3:0]) but not a memory‑count‑responsive clock gate.
• No reference I could verify discloses receiving a count of memories and dividing the PLD read clock by that count. The closest art of record is the multi‑device chain in the Cyclone II NPL, which does not count memories for clock gating.

Claim 4 is the claim I would expect to survive the art of record absent additional art (e.g., a memory‑controller article teaching clock division by the number of interleaved banks) or reliance on the "routine engineering" line of KSR. I flag this candidly.

5. Ground 3 — Claims 7, 8, 9, 10

Claim 7 requires: memory interface receiving a first address signal from an external source; configuration memory cells storing a second address signal; an SPI processor that selects either the first or the second address and provides it as a leading read address to a plurality of SPI flash memories; and a multiplexer selecting among the SPI flash memories' serial outputs to form a configuration bitstream input.

• The first/second‑address selection architecture is squarely met by US 6,903,574 in combination with the '357 specification's own description, since US 6,903,574 discloses (a) a serial memory interface that writes data into configuration memory cells after configuration, and (b) configuration memory cells holding values that are selectable/addressable, with the SMI receiving an external address ADDR[6:0], a write‑data path WDATA, and the cell write path MEM_IN/BYTE_WEN (verified: https://patents.google.com/patent/US6903574; https://www.patents-review.com/a/20050024085-memory-access-serial-memory-interface.html). The '357 patent's FIG. 3 multiplexer 345 / SRAM cells 335 / Mem_In[7:0] / Byte_Write_En structure maps element‑for‑element onto the SMI architecture of US 6,903,574, which is incorporated by reference into the '357 patent.
• The SPI read command and leading read address over a serial input line are met by the Cyclone II NPL (ASDO carries "operation commands and/or read address signals" to the serial configuration device; ASDI is the device's data input).
• The plural SPI flash memories + output multiplexer remains the gap identified in Ground 1, addressed by the same capacity/arbitration/burst motivations plus the parallel‑DATA wiring shown in the Cyclone II multi‑device figures.

Claim 8 (command gating of a read clock to provide an SPI read clock to the plurality of flash memories): supported by US 6,564,285's clocked flash interface plus Lattice clock references (titles only) plus the routine nature of clock gating. Moderate.

Claim 9 (read command sent via a high‑during‑configuration (HDC) signal): the concept of using a configuration‑mode‑active signal as the serial command path is taught in substance by the Cyclone II AS scheme (configuration pins ASDO/ASDI active during configuration, idle after) and by US 6,028,445 / US 5,794,033 (multi‑purpose pins). The specific signal naming ("HDC") cannot itself confer patentability; only the function matters. Moderate‑to‑strong.

Claim 10 (latch storing at least a portion of the leading read address provided by the SPI processor): met by the address‑latch/register of US 6,903,574 and the read‑address transmission of the Cyclone II AS scheme. Moderate‑to‑strong.

6. Ground 4 — Claims 5 and 6

Claim 5 (memory interface receiving a first address signal from an external source and coupling it to the latch) and Claim 6 (configuration memory storing a second address signal, the latch also storing that second address signal):

These are the claims for which the art of record is strongest, because US 6,903,574 — which is expressly incorporated by reference into the '357 specification — discloses precisely (i) a serial memory interface that receives external address/data from the system bus after configuration and writes it into configuration memory cells, and (ii) configuration memory cells that can be updated after configuration. The '357 FIG. 3 architecture (latch 300, parallel‑to‑serial converter 315, Mem_Out 320, Mem_In 346, Byte_Write_En 375, configuration SRAM cells 335, multiplexer 345) is a direct implementation of the incorporated '357/US 6,903,574 memory‑access architecture, with the selection between externally supplied and internally stored address bytes being an evident design choice in a multi‑source addressing system. Strong rejection of claims 5–6 as a combination of US 6,903,574 with the basic serial‑configuration‑memory art (Atmel/Cyclone II NPL).

7. Ground 5 — Claims 11–18 (system claims)

Claims 11–18 recite a system of (i) plural serial interface memories, (ii) a master FPGA having a multiplexer and serial interface processor, and (iii) one or more daisy‑chained slave FPGAs; plus (12) decompression, (13) SPI memories, (14) latch for a leading read address, (15) memory interface for an external first address, (16) configuration memory for a second address, (17) size command interface, and (18) SPI flash + SPI interface processor.

Proposed primary combination: Altera "Configuring Cyclone II Devices" (July 2005 NPL) in view of US 5,563,592 and US 6,903,574, further in view of US 6,028,445 and US 6,564,285.

• The master/slave daisy chain driving configuration of downstream devices, with the master acting as configuration controller, is taught by the Cyclone II NPL "Multiple Device AS Configuration" and by US 6,028,445. Claim 11's chain architecture is therefore met or obvious.
• Claim 12 (decompression in the master, decompressed bitstream to slaves) is strongly obvious: the Cyclone II NPL discloses compressed/uncompressed data flowing to cascaded devices, with a "Decompression Controller" in the master and the slave receiving uncompressed data (verified figures/text in the Cyclone II / Configuration Handbook excerpts at https://www.manualzz.com/doc/[8813687](/patent/8813687)... and https://www.manualzz.com/doc/36800584/altera-fpgas-handbook). That is essentially claim 12.
• Claim 13 (SPI memories) — see Ground 2 analysis for claim 3.
• Claims 14–17 — see Grounds 1, 3, 4; claim 17's size‑command interface is the same weak point as claim 4.
• Claim 18 — combination of claim 13 and claim 3 reasoning.

8. Why a POSITA would have been motivated to combine (KSR rationales)

1. Art‑recognized deficiency in the same field. The '357 Background expressly states that conventional SPI‑flash‑configured FPGAs "are limited … to downloading their configuration bit stream from just a single SPI flash," and US 6,327,634 of record states that "several PROMs may be required" for one bitstream. Responding to a known capacity limitation with additional memories is not an inventive leap.
2. Predictable results / finite set of solutions. Adding parallel memory devices and selecting among them (round‑robin, interleaved, or arbitrated) with a multiplexer is a standard, predictable technique. Sequencing the read clock across the memories is the natural companion of parallel storage — indeed, the '357 patent's own interleaving scheme (D[0], D[1], D[2], D[0]…) is a well‑known striping/interleaving pattern in memory systems, and US 6,564,285 of record teaches issuing burst addresses one per clock period with data returned sequentially.
3. Market/cost pressure. The '357 patent itself states that "SPI flash memory can be substantially less expensive than conventional (and often proprietary) PROMs," and the Atmel AT17LV/EEPROM configuration‑memory citations and Altera EPCS documents establish the commercial availability of low‑cost serial configuration memories. Cost reduction is a recognized KSR rationale.
4. Design incentive from the daisy‑chain context. Once a master FPGA must configure downstream slave FPGAs with a single serial data stream (Cyclone II ch. 13; US 6,028,445), placing the decompression and source‑selection logic in the master is the natural architectural choice, because the slaves cannot independently fetch their data when only the master controls DCLK/nCS.
5. Ordinary engineering of known elements. Gating or dividing a clock (US 6,885,227 / US 7,019,577 / US 7,034,599, Lattice clock art of record), latching an address (US 6,903,574; US 6,564,285), and multiplexing among sources (US 7,062,615 arbitration) are each individually known and combined with predictable effect.

9. Where the art of record is weakest — candid assessment

I do not think the art of record establishes a clean, literal § 103 case on every claim, and I would say so rather than overstate:

Two further points an examiner/judge should weigh:

• The specific interleaving pattern disclosed in the specification ("D[0], D[1], D[2], D[0], D[1], D[2], D[1], and so on") is not recited in any claim; claims 1 and 7 require only a multiplexer that selects "from" the memories. So the absence of striping art does not save the claims.
• The latch's dual‑source, reset‑to‑zero, Config_Done/Config_Done_Delay sequencing (FIG. 3: latch 300 reset by power_up 330 so the leading read address is zero for initial configuration, then loaded from SRAM cells 335 or Mem_In 346) is likewise not recited in the claims. Claims 5, 6, 10, 14–16 recite only the ability to store a first/second address in the latch. The detailed sequencing can therefore be argued as an unclaimed implementation detail.

10. Bottom line

On the prior art of record, I would pursue § 103 rejections as follows:

• Claims 2, 11, and 12 should be rejected over Altera's "Configuring Cyclone II Devices" (July 2005) in view of US 5,563,592, because the Cyclone II handbook of record expressly discloses (a) cascaded master/slave devices configured from serial configuration devices, (b) operation commands and read addresses sent over the serial configuration interface, and (c) compressed‑bitstream reception with on‑the‑fly decompression — that is the substance of these claims.
• Claims 5, 6, 14, 15, and 16 should be rejected over US 6,903,574 (expressly incorporated by reference in the '357 specification) in view of the Atmel/Cyclone II serial‑configuration‑memory NPLs, because US 6,903,574 discloses a serial memory interface that writes externally supplied data into configuration memory cells after configuration.
• Claims 1, 3, 7, 9, 10, 13, 18 present a viable but motivation‑dependent combination (US 6,028,445 + US 5,563,592 + US 6,564,285 + US 7,062,615 + the Atmel/Cyclone II NPLs), relying on KSR rationales (known capacity deficiency, cost pressure, predictable combinations of known elements).
• Claims 4, 8, and 17 are not established as obvious on this record; the "size command → gated read clock" feature has no verified counterpart in the cited art, and I would not assert otherwise without new art (e.g., a multi‑bank memory controller teaching clock division by bank count).
• Do not rely on US 7,570,078, US 8,384,427, US 2007/0182445's later family members, or U.S. Appl. Nos. 11/494,862 and 11/530,620 — they are not available as prior art against the 2006‑02‑03 filing date of the '357 patent.

Confidence note: the element‑to‑element mappings for US 5,563,592, US 6,028,445, US 6,327,634, US 6,564,285, US 6,903,574, and the Altera Cyclone II handbook are grounded in text I verified above and in the page's own citation list. For US 6,038,185, US 6,044,025, US 6,525,678, US 6,773,230, US 6,483,342, US 6,885,227, US 7,019,577, US 7,034,599, US 7,062,615, US 2006/0143366, US 7,242,221, and US 7,088,131, I rely on their titles/citation status only and did not verify their full disclosures; those characterizations should be confirmed against full text before being placed in a rejection.