Invalidity dossier
US 7388277
Chip and wafer integration process using vertical connections
Current assignee: GlobalFoundries US Inc
Added 9/24/2026, 12:04:48 AM
Active provider: DeepSeek · deepseek-flash
Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Patent Overview — US 7,388,277 B2
Title: Chip and wafer integration process using vertical connections
Patent number / application: US 7,388,277 B2, application US 11/033,926, published also as US 2005/0121711 A1.
Inventors: H. Bernhard Pogge; Roy Yu; Chandrika Prasad; Chandrasekhar Narayan.
Assignee: Originally International Business Machines Corp. The source lists a current assignee of GlobalFoundries US Inc., but per your instructions the ownership-transfer details are not analyzed here.
Key dates: Priority date 2001-12-19; filing date 2005-01-12; grant/publication 2008-06-17; adjusted expiration 2022-11-22. Status listed as "Expired – Lifetime." A related application US 12/114,145 (granted as US 7,564,118 B2) claims priority from this filing.
Purpose (from the title and classifications): The patent concerns integrating chips and wafers using vertical (through-substrate) electrical connections. The classification record places it in through-semiconductor via (TSV) territory, including blind vias formed during manufacture, conductive fill methods and materials, filling of holes/grooves/trenches, and handling/holding of wafers using a temporary auxiliary support.
Plain-language scope, as far as the supplied excerpt shows: A semiconductor structure in which vertical connections are formed through a substrate, involving a dielectric layer on the substrate, blind vias that are subsequently filled with conductive material, and wafer-handling via a temporary support. The excerpt's "prior art keywords" (substrate, structure according, semiconductor structure, dielectric layer, layer) are consistent with a structure-plus-method disclosure, but the excerpt does not reproduce any claims, so the precise claim scope is not established.
Source: https://patents.google.com/patent/US7388277/en
What the excerpt does not establish: the full specification, the text of the claims, the cited prior art references, prosecution history, the detailed process sequence, and the specific materials or dimensions. It also does not provide a legal analysis of claim scope or validity.
Generated 10/1/2026, 9:32:05 PM
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Litigation summary
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Proceedings on file (0)
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No PTAB proceedings on file. This patent has not been challenged via IPR, PGR, or CBM. The absence is itself a signal — well-asserted patents eventually attract IPRs. The LLM analysis below may surface filings the ODP feed hasn’t indexed yet.
PTAB challenges
AIA trial proceedings at the USPTO Patent Trial and Appeal Board — IPR, PGR, and CBM. Petitioners, judge panels, claim-level invalidation outcomes from Final Written Decisions, and Federal Circuit appeals. The single most important defensive datapoint after litigation history.
Assignment history
Inventors, original assignee, and the chain of ownership recorded with the USPTO — including the correspondent attorney who recorded each assignment, since shell-LLC chains often share one repeat-player attorney even when the entity names look unrelated. Surfaces NPE / patent-troll patterns: shell-entity transfers, known asserters in the chain, repeat correspondent fingerprints, pre-litigation assignments, and bankruptcy fire-sales.
Prior art
Earlier patents, publications, and products that may anticipate or render the claims unpatentable.
Obviousness
Combinations of prior art that suggest the claimed invention would have been obvious under 35 U.S.C. § 103.
Extensions
Patent term adjustments, term extensions, continuations, divisionals, family members, and expiration dates.
Derivative works
Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.