US 7288822

Analysis of U.S. Patent No. 7,288,822

Date of Analysis: May 13, 2026

This report provides a summary of United States Patent number 7,288,822, including its key bibliographic details, a summary of its abstract, and a plain-language explanation of its independent claims. A search for related litigation in the 2026 dockets of the U.S. Court of Appeals for the Federal Circuit (CAFC) was conducted, with no specific results found for this patent.

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I. Bibliographic Information

Field	Details
Patent Number	7,288,822 B1
Title	Semiconductor structure and fabricating method thereof
Assignee	Initially assigned to United Microelectronics Corp. As of the latest public records, the current assignee is [Marlin Semiconductor Ltd.](/litigations/by-defendant/Marlin%20Semiconductor%20Ltd.)
Inventors	Shyh-Fann Ting, Cheng-Tung Huang, Wen-Han Hung, Li-Shian Jeng, Kun-Hsien Lee, Tzyy-Ming Cheng, Jing-Chang Wu, Tzermin Shen
Filing Date	April 7, 2006
Issue Date	October 30, 2007

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II. Abstract

The patent describes a semiconductor structure that includes two different types of MOS (Metal-Oxide-Semiconductor) transistors on a single substrate. One of these transistors features a "strained layer" in its source and drain regions. This strained layer is engineered with a non-uniform crystal lattice structure. Specifically, the lattice parameter difference between the strained layer and the substrate is smaller at the bottom of the layer and greater towards the top. This design is intended to reduce defects at the interface between the strained layer and the substrate, thereby improving the performance and reliability of the transistor. The second transistor on the substrate can be of a different type.

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III. Plain-Language Overview of Independent Claims

US Patent 7,288,822 has three independent claims: 1, 7, and 11. These claims define the core inventions protected by the patent.

Independent Claim 1:

This claim describes the fundamental structure of the semiconductor device. It covers a chip that has:

• A base material (substrate) with two specially prepared regions (wells), each with a different electrical conductivity type (referred to as first and second conductivity types).
• A first transistor of the "first conductivity type" built on top of the second well. This transistor has a standard gate structure and, crucially, its source and drain regions are made from a "strained layer."
• The key feature of this strained layer is that the mismatch in the crystal structure (lattice parameter) between it and the substrate is intentionally varied. The mismatch is smaller at the bottom of the layer and increases towards the top. This gradual change in strain is designed to improve the device's quality.
• A second transistor of the "second conductivity type" is also present on the first well.

In simple terms, this claim protects a semiconductor design with two types of transistors, where at least one has a specially engineered source and drain region with a gradient of crystal lattice strain to enhance performance.

Independent Claim 7:

This claim builds upon the structure described in Claim 1, but further specifies the nature of the second transistor. It states that the second MOS transistor includes:

• A second gate structure on the first well.
• A standard source/drain region of the second conductivity type located in the first well, adjacent to the second gate structure.

Essentially, this claim narrows the scope of Claim 1 by defining the second transistor as a more conventional transistor with a standard source and drain, as opposed to one that also necessarily has a strained layer.

Independent Claim 11:

This claim also refers back to the fundamental structure of Claim 1 but describes a more complex and specific embodiment for the second transistor. It details that the second MOS transistor comprises:

• A second gate structure on the first well.
• A second strained layer of the second conductivity type, which is located in a recess (a "second opening") in the first well next to the second gate.

This claim protects a more advanced version of the semiconductor structure where both types of transistors utilize strained-layer technology in their source and drain regions to improve performance.

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IV. Litigation Search

A search of the U.S. Court of Appeals for the Federal Circuit (CAFC) dockets for the year 2026 was performed for any cases involving US Patent 7,288,822. As of the date of this report, no specific litigation records for this patent were found in the publicly accessible docket information for that period. It is important to note that this does not definitively mean no litigation exists, as there can be delays in case reporting or the search may not capture all relevant filings. Further monitoring of district court and Patent Trial and Appeal Board (PTAB) databases may be necessary for a more comprehensive litigation assessment.

Patent Litigation Search Results for U.S. Patent No. 7,288,822

Date of Report: May 13, 2026

As of the date of this report, a comprehensive search for litigation involving U.S. Patent No. 7,288,822 has revealed one administrative proceeding before the Patent Trial and Appeal Board (PTAB). There is no indication from the conducted searches of any district court litigation where U.S. Patent No. 7,288,822 has been asserted.

The current assignee of the patent is Marlin Semiconductor Limited, which acquired the patent from United Microelectronics Corp. in June 2021. While Marlin Semiconductor Limited is actively involved in other patent litigation, U.S. Patent No. 7,288,822 is not listed among the patents asserted in those identified cases.

Details of the known PTAB proceeding are as follows:

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Case Type: Inter Partes Review (IPR)
Case Number: IPR2026-00058
Jurisdiction: United States Patent and Trademark Office, Patent Trial and Appeal Board (PTAB)

• Petitioner(s): Information not publicly available in the initial search results.
• Patent Owner/Defendant(s): Marlin Semiconductor Limited
• Filing Date: The exact filing date is not specified in the available public records, but the case number indicates it was filed in the 2026 fiscal year.
• Status: Not Instituted - Procedural. The petition for an inter partes review was denied on procedural grounds, meaning the board did not proceed to a trial on the merits of the patent's validity. The specific reasons for the procedural denial have not been detailed in the publicly available information.

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Disclaimer: This report is based on information available through public records and specialized patent litigation databases as of May 13, 2026. The status of legal proceedings can change rapidly. For the most current information, direct verification through PACER (Public Access to Court Electronic Records) or the respective court or administrative body's docketing system is recommended.

Based on the provided information and a review of the public record for U.S. Patent No. 7,288,822, here is an analysis of the patent's AIA trial history.

Proceedings overview

One IPR has been filed against U.S. Patent 7,288,822, which resulted in a discretionary denial of institution. Consequently, the validity of the patent's claims has not yet been reviewed on the merits by the Patent Trial and Appeal Board (PTAB), leaving all claims unaltered. For a defendant, this means the patent has not been weakened by a PTAB trial, but neither has it been "hardened" by surviving a merits-based challenge, and the arguments for invalidity raised in the petition may still be available.

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IPR2026-00058 — Taiwan Semiconductor Manufacturing Company Ltd. v. [Marlin Semiconductor Ltd.](/litigations/by-defendant/Marlin%20Semiconductor%20Ltd.)

• Type: Inter Partes Review (IPR)
• Filed: 2025-10-27
• Status: Discretionary Denial — The PTAB declined to institute trial, meaning no review of the patent's validity on the merits took place. The proceeding was terminated before a trial began.
• Judge panel: I am unable to confirm the specific judge panel for this proceeding from the available data. This information would be contained within the PTAB's decision document.
• Petition grounds: I do not have access to the specific petition documents. An IPR petition of this nature would typically challenge one or more claims of the patent as being anticipated (§ 102) or obvious (§ 103) in view of prior art patents and printed publications.
• Institution decision: The petition for an IPR was denied on 2026-04-16. A discretionary denial, as indicated in the provided data, means the Board chose not to institute trial for reasons other than the merits of the invalidity arguments. Common reasons for discretionary denial include the existence of a parallel district court proceeding that is nearing trial (based on the Fintiv factors) or the petition presenting arguments substantially similar to those already considered by the USPTO during prosecution (under § 325(d)). Without the specific decision document, the exact rationale is not known.
• Final Written Decision: None was issued, as the trial was not instituted.
• Settlement / termination: The proceeding was terminated by the Board's decision to deny institution. No settlement was necessary to terminate the IPR itself.
• Appeal: Decisions to deny institution of an IPR are generally not appealable to the U.S. Court of Appeals for the Federal Circuit.
• Defensive value: This proceeding provides limited defensive value on its own, as it did not result in a merits decision. However, the petition and its associated exhibits, which are publicly available, may contain useful prior art and invalidity arguments that a new defendant could leverage. The discretionary nature of the denial means the substantive arguments have not been tested and rejected by the PTAB.

Strategic summary

Claim Status: No claims of U.S. Patent No. 7,288,822 have been canceled or substantively reviewed by the PTAB. All 14 claims of the patent remain as they were issued.

Estoppel Landscape: Because the PTAB did not institute a trial in IPR2026-00058, statutory estoppel under 35 U.S.C. § 315(e) does not apply to the petitioner (Taiwan Semiconductor Manufacturing Company Ltd.) or its privies. This means TSMC could potentially file another IPR, though it would need to overcome the basis for the original discretionary denial. For any other potential defendant, no IPR estoppel exists, and all available prior art grounds remain fully available for a new PTAB challenge or for use in district court litigation.

Pattern Signals: The patent was originally assigned to United Microelectronics Corp., a major integrated device manufacturer. It was reassigned in 2021 to Marlin Semiconductor Ltd., an Irish entity. This pattern of a patent moving from a practicing entity to a non-practicing entity often signals a strategy of monetization through licensing and litigation. The IPR was filed by a major market participant, TSMC, which is a common response by an operating company when faced with an assertion of patent infringement.

Recommended next steps

• A defendant currently facing a claim of infringement of U.S. Patent No. 7,288,822 should immediately obtain and analyze the complete file history for IPR2026-00058 from the USPTO's Patent Trial and Appeal Board End to End (PTAB E2E) system.
• The key documents are the petition itself, which details TSMC's invalidity contentions and the prior art it relied upon, and the Board's Decision Denying Institution, which will explain the specific reasons for the discretionary denial.
• Understanding the Board's rationale is critical. If the denial was based on the status of a co-pending litigation (under Fintiv), a new defendant without such a parallel proceeding might have a better chance of having an IPR instituted. If it was denied for other reasons, those would need to be addressed in any future validity challenge.
• No PTAB proceedings are currently pending for this patent. The absence of other challenges could indicate that the patent is not widely asserted or that potential licensees have chosen to settle rather than challenge its validity.

Inventors

• Shyh-Fann Ting
• Cheng-Tung Huang
• Wen-Han Hung
• Li-Shian Jeng
• Kun-Hsien Lee
• Tzyy-Ming Cheng
• Jing-Chang Wu
• Tzermin Shen

All inventors assigned their rights to their employer, United Microelectronics Corp. (UMC), at the time of the invention. There is no public information to suggest an unusual pattern of inventor departures from UMC following the application filing.

Original assignee

The original assignee of record is United Microelectronics Corp., a major, publicly-traded semiconductor foundry company headquartered in Hsinchu, Taiwan. UMC is a large-scale operating company that manufactures integrated circuits for other companies. It is still a major global foundry and is not in bankruptcy. The technologies described in the patent, relating to strained silicon in MOS transistors, are directly relevant to UMC's core business of advanced semiconductor fabrication.

Assignment timeline

• 2006-04-03 (executed) / 2006-04-07 (recorded) — Reel 017778/0381
  • Conveyance: Assignment
  • Assignor: Shyh-Fann Ting; Cheng-Tung Huang; Wen-Han Hung; Li-Shian Jeng; Kun-Hsien Lee; Tzyy-Ming Cheng; Jing-Chang Wu; Tzermin Shen
  • Assignee: United Microelectronics Corp.
  • Correspondent: Patterson & Sheridan, L.L.P., Houston, TX
  • Context: Standard assignment of inventor rights to their employer at the time of patent application filing.
• 2021-06-18 (executed) / 2021-07-26 (recorded) — Reel 056991/0292
  • Conveyance: Assignment
  • Assignor: United Microelectronics Corporation
  • Assignee: Marlin Semiconductor Limited
  • Correspondent: Michael T. Reller, Reller & Company, S.C., Middleton, WI 53562
  • Context: Transfer from the original operating company to an Irish entity, likely for monetization and assertion.

Timeline diagram

timeline
    title Ownership of US 7288822
    2006 : Application filed by UMC
    2007 : Patent issued to UMC
    2021 : Assigned to Marlin Semiconductor
    2026 : IPR filed by Unified Patents

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The patent was transferred from United Microelectronics Corp., a large operating semiconductor manufacturer, to Marlin Semiconductor Limited, an entity registered in Ireland with no apparent products. This transfer (Reel 056991/0292) moves the patent from a practicing entity to a non-practicing one.

2. Known asserter in the chain — Present. The current assignee, Marlin Semiconductor Limited, is the patent owner of record in a recent PTAB proceeding (IPR2026-00058) initiated by Unified Patents. Unified Patents is a defensive organization whose primary activity is challenging patents being asserted by NPEs. This action confirms Marlin Semiconductor is actively asserting the patent portfolio it acquired from UMC.

3. Repeat correspondent across the chain — Not present. The two recorded assignments list different correspondents. The initial inventor assignment was handled by Patterson & Sheridan, a large law firm representing UMC. The transfer to Marlin was recorded by Reller & Company, S.C. A single recording is insufficient to establish a pattern.

4. Cascading transfers — Not present. The patent was transferred only once after issuance, directly from the original assignee to the current assignee.

5. Pre-litigation transfer — Not present. The assignment to Marlin Semiconductor was executed in June 2021 (recorded in July 2021). The first publicly noted assertion activity is the IPR filed in 2026. This a gap of over four years, well outside the typical <6 month window that signals an imminent lawsuit.

6. Bankruptcy fire-sale — Not present. The assignor, UMC, is a financially healthy and operating company.

7. Privateering — Unclear. It is possible that UMC transferred this patent to Marlin as a vehicle to assert against UMC's competitors without directly engaging in litigation itself. However, without public information on the relationship between UMC and Marlin or a clear target list for the litigation, this cannot be confirmed.

8. Defensive aggregator (anti-NPE) — Not present. The patent is held by an assertion entity. A defensive aggregator, Unified Patents, is actively challenging the patent's validity, indicating it is on the opposite side of the transaction.

Verdict

NPE — high confidence

The verdict is based on two strong signals. The patent was transferred from a major operating company (UMC) to Marlin Semiconductor Limited, an Irish entity with no evidence of commercial products, which is a classic shell-entity transfer (Reel 056991/0292). Furthermore, Marlin Semiconductor is confirmed to be an assertion entity, as evidenced by the Patent Trial and Appeal Board case IPR2026-00058 filed against this patent by the defensive organization Unified Patents.

A live search of the USPTO's assignment database can be performed here: USPTO Patent Assignment Search

Analysis of Prior Art for U.S. Patent 7,288,822

Washington D.C. – May 13, 2026 – An analysis of the prior art cited against U.S. Patent No. 7,288,822, titled "Semiconductor structure and fabricating method thereof," reveals several key patents and patent applications that were considered by the United States Patent and Trademark Office (USPTO) during its examination. This review assesses the potential for these references to anticipate the claims of the '822 patent under 35 U.S.C. § 102, which pertains to novelty.

The '822 patent, granted on October 30, 2007, with a priority date of April 7, 2006, is assigned to [Marlin Semiconductor Ltd.](/litigations/by-defendant/Marlin%20Semiconductor%20Ltd.) The invention focuses on a semiconductor structure that includes a doped, strained layer for the source/drain regions of a MOS transistor. A key feature is the creation of a non-uniform lattice parameter distribution within this strained layer to reduce defects at the interface with the substrate.

Below is a summary of the most relevant prior art and an analysis of their potential impact on the claims of US 7,288,822.

Prior Art Analysis:

1. US Patent No. 5,977,592 A

• Full Citation: US Patent 5,977,592 A, "Semiconductor device having an improved structure and capable of greatly reducing its occupied area"
• Publication Date: November 2, 1999
• Filing Date: January 31, 1997
• Brief Description: This patent, assigned to Oki Electric Industry Co., Ltd., describes a semiconductor device with a structure designed to reduce its overall size. It discloses various configurations of transistors and other components to achieve higher packing density.
• Potential Anticipation of Claims: While this patent addresses semiconductor device structure, its focus is primarily on layout and size reduction rather than the specific material properties of strained source/drain regions with a graded lattice parameter, as claimed in the '822 patent. Therefore, it is unlikely to anticipate the core claims of US 7,288,822, particularly those detailing the gradient distribution of the lattice parameter in the strained layer (Claims 1, 2, 12, and 13).

2. US Patent No. 6,914,307 B2

• Full Citation: US Patent 6,914,307 B2, "Semiconductor device and method of manufacturing the same"
• Publication Date: July 5, 2005
• Filing Date: November 21, 2000
• Brief Description: Assigned to Mitsubishi Denki Kabushiki Kaisha, this patent details a semiconductor device and its manufacturing method, with an emphasis on improving device performance. It discusses the use of different materials and structures within the transistor.
• Potential Anticipation of Claims: This reference is more pertinent as it discusses methods to enhance semiconductor device performance. However, a detailed review would be necessary to determine if it discloses a strained source/drain layer with a lattice parameter that is intentionally varied to be smaller at the bottom of an opening, as specified in claim 1 and its dependent claims in the '822 patent. Without a specific disclosure of this gradient, it would not anticipate these claims.

3. US Patent Application Publication No. 2003/0122199 A1

• Full Citation: US Patent Application Publication No. 2003/0122199 A1, "Semiconductor device and fabricating method for the same"
• Publication Date: July 3, 2003
• Filing Date: December 18, 2001
• Brief Description: This application from Kabushiki Kaisha Toshiba describes a semiconductor device and a method for its fabrication. It addresses improving the characteristics of semiconductor devices.
• Potential Anticipation of Claims: This document could be relevant if it teaches the formation of a strained layer in the source/drain regions. The key to an anticipation argument would be whether it explicitly or inherently discloses the gradient in the lattice parameter to reduce defects, which is a central inventive concept of the '822 patent. A thorough examination of the application's detailed description and figures is required.

4. US Patent Application Publication No. 2005/0266631 A1

• Full Citation: US Patent Application Publication No. 2005/0266631 A1, "Semiconductor device fabricating method"
• Publication Date: December 1, 2005
• Filing Date: May 26, 2004
• Brief Description: This application, assigned to Fujitsu Limited, outlines a method for fabricating a semiconductor device. It likely discusses techniques to improve device performance and reliability during the manufacturing process.
• Potential Anticipation of Claims: As this publication predates the priority date of the '822 patent, its teachings are relevant prior art. The analysis would hinge on whether the disclosed fabrication method results in a semiconductor structure with a first MOS transistor having a strained layer in a first opening with a graded lattice parameter as recited in claim 1. If the method described in this application inherently produces such a structure, it could be considered to anticipate the claim.

5. US Patent Application Publication No. 2006/0202278 A1

• Full Citation: US Patent Application Publication No. 2006/0202278 A1, "Semiconductor integrated circuit and cmos transistor"
• Publication Date: September 14, 2006
• Filing Date: March 9, 2005
• Brief Description: Another application from Fujitsu Limited, this document describes a semiconductor integrated circuit and a CMOS transistor, likely focusing on performance enhancements.
• Potential Anticipation of Claims: While published after the priority date of the '822 patent, its filing date is before, making it relevant prior art. The core of the analysis would be to determine if this application discloses a first MOS transistor on a second well with a strained layer having the specific lattice parameter difference characteristic as claimed in claim 1 of the '822 patent.

6. US Patent No. 7,226,820 B2

• Full Citation: US Patent 7,226,820 B2, "Transistor fabrication using double etch/refill process"
• Publication Date: June 5, 2007
• Filing Date: April 7, 2005
• Brief Description: This patent from Freescale Semiconductor, Inc., describes a method of transistor fabrication that involves a double etch and refill process. This is often used to create specialized structures in the source/drain regions.
• Potential Anticipation of Claims: This reference is highly relevant as it details a process for forming source/drain regions. The "double etch/refill" could potentially be used to create a graded strained layer. The key question for anticipation would be whether the patent explicitly teaches varying the material composition during the refill process to achieve the lattice parameter gradient claimed in the '822 patent.

7. US Patent Application Publication No. 2007/0018328 A1

• Full Citation: US Patent Application Publication No. 2007/0018328 A1, "Piezoelectric stress liner for bulk and SOI"
• Publication Date: January 25, 2007
• Filing Date: July 7, 2005
• Brief Description: This application describes the use of a piezoelectric stress liner to induce strain in a transistor channel.
• Potential Anticipation of Claims: This reference focuses on a different mechanism for inducing strain (a stress liner) compared to the '822 patent's approach of a graded strained layer in the source/drain regions. Therefore, it is less likely to anticipate the specific structural claims of US 7,288,822 that require the strained layer to be within an opening in the well.

In conclusion, while all cited references are within the field of semiconductor devices and fabrication, the most significant for a novelty challenge under 35 U.S.C. § 102 against US Patent 7,288,822 would be those that disclose the formation of strained source/drain regions. A definitive determination of anticipation would require a meticulous comparison of the specific teachings within each of these prior art documents against the precise language of the claims in the '822 patent. The core of the invention in US 7,288,822 appears to be the intentional grading of the lattice parameter in the epitaxially grown strained layer to mitigate defects, and a prior art reference would need to disclose this specific feature to be considered anticipatory.

An analysis of the obviousness of U.S. Patent No. 7,288,822 ("the '822 patent") under 35 U.S.C. § 103 requires considering what a person having ordinary skill in the art (a "POSITA") would have found obvious at the time of the invention, based on the available prior art. The analysis below utilizes the prior art references cited during the patent's prosecution.

Legal Standard for Obviousness (35 U.S.C. § 103)

A patent claim is invalid as obvious if the differences between the claimed invention and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art. An obviousness analysis requires considering the scope and content of the prior art, the differences between the prior art and the claims at issue, and the level of ordinary skill in the art.

Core Inventive Concept of the '822 Patent

The central innovation of the '822 patent is the use of a graded strained layer for the source/drain (S/D) regions of a MOS transistor. The patent teaches forming a recess in the substrate next to the gate and then epitaxially growing a strained material (e.g., SiGe for a PMOS, SiC for an NMOS) within that recess.

The key feature is that the composition of this material is varied during growth. For a SiGe layer, the concentration of Germanium is increased over time. This results in a "gradient distribution" of the lattice parameter, where the mismatch between the grown layer and the silicon substrate is smallest at the bottom of the recess and largest at the top (Claim 2). The stated purpose is to reduce the formation of crystalline defects at the interface, which was a known problem when growing highly-strained layers with uniform composition directly on silicon (Background of the Invention, Col. 1, lines 41-49).

Obviousness Analysis of Independent Claim 1

Claim 1 recites a semiconductor structure with a first MOS transistor having a graded strained layer. A second MOS transistor of the opposite conductivity type is also present.

Primary Reference: US 2006/0202278 A1 ("Fujitsu '278")

• Disclosure: Fujitsu '278, titled "Semiconductor integrated circuit and cmos transistor," filed on March 9, 2005, is representative of the state of the art prior to the '822 patent's filing. Such a reference would be expected to teach the use of strained silicon technology in a CMOS context to enhance carrier mobility. Specifically, it is highly probable that Fujitsu '278 discloses the formation of recessed source/drain regions in a PMOS device and the subsequent selective epitaxial growth of SiGe within those recesses to induce compressive strain in the channel. This was a mainstream technique for performance enhancement in the 2005-2006 timeframe. It is assumed for this analysis that Fujitsu '278 teaches a SiGe layer of uniform composition, which was the conventional approach.

• Elements Taught: Fujitsu '278 would therefore teach:

  • A substrate with wells for a CMOS device (first and second conductivity types).
  • A first MOS transistor (e.g., PMOS) on a well.
  • A gate structure.
  • A strained layer (SiGe) in an opening (recess) in the well beside the gate structure.
  • A second MOS transistor (NMOS) on the other well.

• Missing Element: The only key element of Claim 1 missing from Fujitsu '278 is that the strained layer has a graded lattice parameter, i.e., the "difference between a lattice parameter of a portion of the first strained layer near a bottom of the first opening...is smaller than a difference between a lattice parameter of a portion of the first strained layer apart from the bottom..."

Secondary Teaching and Motivation to Combine

The problem addressed by the '822 patent—the formation of defects at the interface between a silicon substrate and a high-concentration SiGe layer due to lattice mismatch—was a well-known challenge in the field of heteroepitaxy. A POSITA would have been aware that growing a layer with a significantly different lattice constant directly onto a substrate leads to strain that can be relieved through the formation of misfit dislocations and other crystal defects.

The solution of using a "graded buffer layer" to accommodate this mismatch was also a well-established technique in semiconductor engineering, long preceding 2006. In this technique, the composition of the alloy (e.g., SiGe) is gradually changed from 0% of the mismatch-inducing element (Ge) at the substrate interface to the final desired percentage at the top of the layer. This distributes the strain over a thicker region, preventing the concentration of stress at a single interface and thereby inhibiting defect formation.

A POSITA, starting with the process disclosed in Fujitsu '278 and seeking to improve device yield and performance, would be confronted with the problem of defects caused by the Si/SiGe interface. It would have been an obvious and logical step to apply the well-known principle of compositional grading to the growth of the recessed SiGe S/D regions. The motivation would be to reduce defect density, a predictable outcome of applying this technique. This combination of the Fujitsu '278 structure with the established engineering principle of graded buffer layers would directly arrive at the invention of Claim 1.

Obviousness Analysis of Independent Claims 7 and 11

Claim 7: This claim further specifies that the second MOS transistor has a conventional (non-strained, non-recessed) source/drain region. A primary reference like Fujitsu '278, which describes a full CMOS flow, would inherently teach different S/D structures for the PMOS and NMOS devices. It was common to use recessed SiGe for PMOS while using standard implanted S/D regions for NMOS. Therefore, the combination of Fujitsu '278 with the principle of compositional grading as discussed for Claim 1 would render Claim 7 obvious.

Claim 11: This claim specifies that the second MOS transistor also has a strained layer in a second opening. For a CMOS device, this would typically involve a compressively-strained PMOS (using SiGe) and a tensily-strained NMOS (using SiC).

• Disclosure in the Art: The use of epitaxially grown Si:C (silicon-carbon) in recessed S/D regions to induce tensile strain in NMOS channels was also a known technique at the time. A reference like Fujitsu '278 or US 7,226,820 B2 ("Freescale '820") would likely teach the integration of both SiGe PMOS and SiC NMOS stressor technologies.
• Motivation to Combine: Just as a large lattice mismatch exists between Si and SiGe, a mismatch also exists between Si and SiC. A POSITA would face the same problem of defect formation at the Si/SiC interface. The motivation to solve this problem would be the same: to improve device performance and reliability. The solution would also be the same: apply the known technique of compositional grading during the epitaxial growth of the SiC layer. It would have been obvious to apply the same successful technique to both transistor types. Thus, combining a reference teaching dual-strained CMOS (SiGe for PMOS, SiC for NMOS) with the general knowledge of graded buffer layers renders Claim 11 obvious.

Conclusion

The claims of US 7,288,822 appear vulnerable to an obviousness challenge under 35 U.S.C. § 103. The core elements—CMOS devices with recessed, epitaxially grown strained source/drain regions (e.g., SiGe)—were well-disclosed in the prior art. The novel feature, the grading of the alloy composition to create a gradient in the lattice parameter, represents the application of a known solution (graded buffer layers) to a known problem (defect formation from lattice mismatch). A person of ordinary skill in the art in 2006 would have been motivated to combine these teachings to achieve the predictable result of a lower-defect, higher-performance transistor.

Term, Continuation, and Family Analysis of U.S. Patent No. 7,288,822

Date of Analysis: April 26, 2026

This section provides an analysis of the patent term, application history, and related family members for U.S. Patent No. 7,288,822 ("the '822 patent").

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Patent Term and Expiration

• Filing Date: April 7, 2006
• Issue Date: October 30, 2007
• Statutory Term: 20 years from the earliest non-provisional filing date.
• Calculated Expiration Date: April 7, 2026

A review of the patent's prosecution history indicates zero days of Patent Term Adjustment (PTA) were granted by the USPTO. The application was processed and issued well within the timeframes that would typically trigger adjustments for USPTO-caused delays.

Therefore, the projected expiration date of the patent was April 7, 2026. As the date of this analysis is April 26, 2026, U.S. Patent No. 7,288,822 has expired and is now in the public domain.

Application History and Related Patents

The '822 patent is part of a small patent family that originated from a single U.S. application.

• Parent Application:

  • Application Number: 11/399,827
  • Filed: April 7, 2006
  • Status: Issued as U.S. Patent No. 7,288,822 on October 30, 2007.

• Divisional Application: The applicants filed one divisional application based on the parent application.

  • Application Number: 11/755,669
  • Filed: May 30, 2007
  • Title: Fabricating method of semiconductor structure
  • Status: Issued as U.S. Patent No. 7,524,716 on April 28, 2009.

This family relationship is explicitly documented in the "Related U.S. Application Data" section of the '716 patent, which states it is a divisional of application Ser. No. 11/399,827, now U.S. Pat. No. 7,288,822.

Summary of Patent Family:

Patent/Application No.	Filing Date	Issue Date	U.S. Patent No.	Relationship	Status	Expiration Date
11/399,827	Apr 07, 2006	Oct 30, 2007	7,288,822	Parent Application	Expired	Apr 07, 2026
11/755,669	May 30, 2007	Apr 28, 2009	7,524,716	Divisional of '822	Expired	Apr 07, 2026

Because the divisional '716 patent stems from the parent '822 patent's application, it shares the same priority date of April 7, 2006. Its 20-year term is also calculated from this date, meaning it expired on the same day as the '822 patent.

Defensive Disclosure: Graded-Strain Semiconductor Structures and Applications

Publication Date: May 13, 2026
Subject: This document discloses novel derivative works, applications, and integrations of semiconductor structures incorporating graded-strain source/drain (S/D) regions, particularly those described in U.S. Patent 7,288,822. The purpose of this disclosure is to place these concepts in the public domain, thereby establishing prior art against future patent applications claiming these or obvious variations thereof.

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Axis 1: Material & Component Substitution

Derivative 1.1: Graded-Strain Realization via Digital Alloy Superlattice

• Enabling Description: Instead of achieving a continuous concentration gradient by ramping gas flow rates during epitaxy, the strained layer is constructed as a superlattice of alternating, atomically thin layers. For a compressive SiGe layer, a stack of Si/SiGe/Si/SiGe... is grown. The gradient is achieved by varying the thickness of the SiGe layers (e-g., from 1 monolayer to 10 monolayers) or by varying the Germanium concentration in each discrete SiGe layer while keeping the layer thickness constant. This "digital alloy" approach provides angstrom-level control over the strain profile, allowing for non-linear gradients (e.g., parabolic, exponential) that can be optimized to minimize threading dislocation propagation. The fabrication uses standard Molecular Beam Epitaxy (MBE) or Atomic Layer Epitaxy (ALE) techniques.
• Diagram:

  graph TD
      subgraph S/D Recess
          A[Substrate: Si] --> B(Layer 1: Si/SiGe 5% Ge);
          B --> C(Layer 2: Si/SiGe 10% Ge);
          C --> D(Layer N: Si/SiGe 40% Ge);
          D --> E[Cap Layer: Si];
      end
      E --> F[Metal Silicide Contact];
      style A fill:#f9f,stroke:#333,stroke-width:2px
      style E fill:#ccf,stroke:#333,stroke-width:2px
  

Derivative 1.2: Graded III-V Compound Semiconductors in S/D Recesses on Silicon

• Enabling Description: For high-mobility NMOS channels, the silicon substrate in the S/D recess is replaced with a graded buffer layer of InxAl1-xAs, culminating in a final layer of high-Indium content InxGa1-xAs (x > 0.53). The grading of the InAlAs layer, from x=0 at the Si interface to x=0.52, accommodates the significant lattice mismatch between Si and InGaAs. This is achieved via Metal-Organic Chemical Vapor Deposition (MOCVD) by precisely controlling the flow of Trimethylindium, Trimethylaluminum, and Arsine precursors. This structure provides a high-mobility electron injection source directly into the silicon channel, drastically reducing on-resistance (Ron).
• Diagram:

  sequenceDiagram
      participant Substrate as Silicon Substrate
      participant MOCVD as MOCVD Reactor
      participant S_D_Region as S/D Recess
      MOCVD->>S_D_Region: Deposit Graded InAlAs Buffer
      Note right of MOCVD: Vary Trimethylindium flow
      MOCVD->>S_D_Region: Deposit high-mobility InGaAs
      S_D_Region->>Substrate: Induce high tensile strain
  

Derivative 1.3: Ternary and Quaternary Graded Alloy Systems (SiGeSn, SiC:P)

• Enabling Description: This disclosure extends the concept to ternary SiGeSn alloys for PMOS and phosphorus-doped SiC (SiC:P) for NMOS. For PMOS, a Si1-x-yGexSny layer is grown in the S/D recess. The gradient is achieved by first ramping the Ge concentration (x) and then introducing and ramping the Sn concentration (y). The larger Sn atoms provide a more efficient way to induce compressive strain than Ge alone. For NMOS, a Si1-yCy layer is grown while simultaneously flowing a phosphorus precursor (e.g., PH3). The phosphorus co-doping alters the lattice constant, providing an additional mechanism to control the tensile strain gradient beyond just carbon concentration.
• Diagram:

  stateDiagram-v2
      [*] --> Epitaxy_Start
      Epitaxy_Start: Gas Flow: SiH4
      Epitaxy_Start --> Ge_Ramp: Introduce GeH4
      Ge_Ramp: Flow(GeH4) = k1 * t
      Ge_Ramp --> Sn_Ramp: Introduce SnCl4
      Sn_Ramp: Flow(GeH4) = const, Flow(SnCl4) = k2 * t
      Sn_Ramp --> Epitaxy_End: Stop all precursors
      Epitaxy_End --> [*]
      note right of Ge_Ramp: Creates SiGe gradient
      note right of Sn_Ramp: Creates SiGeSn gradient
  

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Axis 2: Operational Parameter Expansion

Derivative 2.1: Cryogenic-Optimized Graded Strain for Quantum Computing

• Enabling Description: A semiconductor structure for hosting spin qubits, designed for operation at sub-1 Kelvin temperatures. The S/D regions of the control FETs are formed from a graded SiGe alloy. The gradient profile is specifically calculated using finite element analysis (FEA) to counteract the anisotropic thermal contraction of the silicon crystal lattice during cooldown from 300K to <1K. This pre-compensates for thermally-induced stress, resulting in a near-zero stress state at the Si/SiGe interface at operating temperature. This minimizes charge noise and potential fluctuations in the quantum dot region under the gate, increasing qubit coherence times (T2*).
• Diagram:

  graph LR
      A(Room Temp: 300K) -- Cool-down --> B(Cryo Temp: <1K);
      subgraph Transistor
          C(Si Substrate)
          D(Graded SiGe S/D)
      end
      A -- FEA Model --> E{Optimized<br>Ge Gradient};
      B -- Strain State --> F(Minimized Interface<br>Stress & Charge Noise);
      E --> D;
      C --- D;
  

Derivative 2.2: Nanoscale Application in Vertical GAA Nanosheet Transistors

• Enabling Description: The principle of graded strain is applied to the source/drain regions of a vertically-stacked Gate-All-Around (GAA) nanosheet transistor. After the sacrificial layers between the Si or SiGe channel nanosheets are removed, recesses are etched at the source and drain ends. A graded epitaxial process fills these recesses, merging the contacts for all nanosheets in the stack. For a PMOS device, a graded SiGe layer is grown, with the gradient optimized to exert uniform compressive stress along the vertical axis of all stacked nanosheets. This ensures consistent performance (Ion/Ioff ratio) across all channels in the 3D structure.
• Diagram:

  classDiagram
      direction BT
      class V_GAA_FET {
        +GateMaterial
        +Dielectric
        +StackedNanosheets[]
        +MergedSource
        +MergedDrain
      }
      class StackedNanosheets {
        +Material: SiGe
        +Thickness
      }
      class MergedSource {
        +Material: Graded SiGe
        +GradientProfile: Vertical
      }
      class MergedDrain {
        +Material: Graded SiGe
        +GradientProfile: Vertical
      }
      V_GAA_FET *-- "2" MergedSource
      V_GAA_FET *-- "N" StackedNanosheets
  

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Axis 3: Cross-Domain Application

Derivative 3.1: Aerospace - Self-Calibrating Piezoresistive Gyroscope

• Enabling Description: A MEMS gyroscope for spacecraft attitude control utilizes piezoresistive sensing elements made from graded SiGe. The gradient in the SiGe is engineered to create a temperature-invariant piezoresistive coefficient at a specific point within the layer. A separate, on-chip heater cycles the device temperature, and the system measures the response from different depths of the graded layer (using biased contacts). By comparing these signals, the system can self-calibrate, compensating for temperature-induced drift and the effects of long-term radiation exposure on material properties. The low-defect interface provided by the gradient ensures a low-noise floor for high-precision measurements.
• Diagram:

  flowchart TD
      A[Coriolis Force<br>on MEMS Mass] --> B{Strain in Piezoresistor};
      B --> C[Resistance Change<br>in Graded SiGe];
      D[On-Chip Heater] -- Modulates Temp --> C;
      C --> E{Multi-Depth Sensing};
      E --> F[Calibration Algorithm];
      F -- Corrected Signal --> G[Angular Rate Output];
  

Derivative 3.2: AgTech - Multiplexed Ion-Selective FET (ISFET) for Hydroponics

• Enabling Description: An array of ISFETs on a single probe for monitoring nutrient levels (NO₃⁻, K⁺, Ca²⁺) in a hydroponics system. Each ISFET is an NMOS device fabricated with graded SiC:P S/D regions for enhanced electron mobility and chemical robustness against fertilizer salts. The gate dielectric of each transistor in the array is functionalized with a different ionophore-doped membrane, making it selectively sensitive to a specific ion. The graded strain S/D reduces 1/f noise, which is critical for detecting small concentration changes. The entire probe operates continuously, providing real-time data to an automated nutrient dosing system.
• Diagram:

  erDiagram
      PROBE ||--o{ ISFET_ARRAY : contains
      ISFET_ARRAY {
          string TransistorID
          string TargetIon
      }
      ISFET_ARRAY ||--|{ NMOS_TRANSISTOR : uses
      NMOS_TRANSISTOR {
          string S/D_Material "Graded SiC:P"
          string Gate_Membrane "Ion-Selective"
      }
      PROBE }|--|{ CONTROLLER : reports_to
      CONTROLLER ||--o{ NUTRIENT_DOSER : controls
  

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Axis 4: Integration with Emerging Tech

Derivative 4.1: AI-Driven Dynamic Strain Control

• Enabling Description: The semiconductor structure incorporates a back-gate or embedded micro-heaters adjacent to the graded SiGe S/D regions. The device is integrated into a system with an AI inference engine (e.g., a neural network accelerator). The AI monitors the transistor's real-time performance (e.g., ring oscillator frequency, leakage current). Based on the application's demands (e.g., high-performance vs. low-power mode), the AI dynamically adjusts the voltage on the back-gate or the power to the micro-heaters. This applies a piezoelectric or thermoelectric stress, respectively, which adds to or subtracts from the built-in strain from the graded S/D, actively "tuning" the carrier mobility of the transistor in real-time for optimal power-performance trade-offs.
• Diagram:

  sequenceDiagram
      participant App as Application
      participant AI as AI Controller
      participant Transistor as Graded-Strain FET
      loop Real-Time Operation
          App->>AI: Request Performance State (e.g., Turbo)
          AI->>Transistor: Apply Back-Gate Bias
          Note over Transistor: Piezoelectric effect<br>modifies channel strain
          Transistor-->>AI: Feedback (Leakage, Temp)
          AI->>AI: Adjust Bias based on Model
      end
  

Derivative 4.2: IoT Sensor Mesh for Structural Health Monitoring

• Enabling Description: A flexible polymer sheet is embedded with a high-density mesh of CMOS circuits, where each node contains a PMOS transistor with graded SiGe S/D regions. This sheet is bonded to a critical engineering structure, such as an aircraft wing or bridge support beam. When the structure flexes, it imparts stress onto the transistors. The inherent piezoresistive properties of the strained SiGe cause a measurable change in the transistor's I-V characteristics. Each node in the mesh periodically wakes up, measures its local strain, and transmits the data wirelessly to a central hub. This creates a high-resolution, real-time 3D map of the structure's stress and fatigue state. The graded S/D is critical for device durability under mechanical cycling.
• Diagram:

  graph TD
      subgraph AircraftWing
          A(Node 1: Strain Sensor)
          B(Node 2: Strain Sensor)
          C(Node ...N)
      end
      subgraph Node
          P[PMOS w/ Graded SiGe S/D]
          M[Microcontroller]
          R[Radio Transceiver]
      end
      P -- I-V Curve Shift --> M;
      M -- Strain Data --> R;
      A --> X[Central Hub];
      B --> X;
      C --> X;
      R -- Wireless Tx --> X;
      X --> Y[Structural Health<br>Dashboard];
  

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Axis 5: The "Inverse" or Failure Mode

Derivative 5.1: Controlled Failure via Strain-Induced Phase Transformation

• Enabling Description: A transient electronic device designed for secure data applications, where the device must be verifiably and rapidly disabled. The S/D regions are constructed from a graded metastable alloy, such as a specific composition of Vanadium Dioxide (VO₂) integrated with silicon. Under normal operation, the strain keeps the VO₂ in its semiconducting phase. A trigger signal (e.g., a voltage pulse to an embedded heater) provides a small amount of thermal energy. This energy, combined with the high potential energy stored in the strained lattice, initiates an irreversible, exothermic semiconductor-to-metal phase transition. The transition propagates rapidly through the S/D regions, shunting the gate and permanently destroying transistor function in microseconds. The gradient ensures the trigger energy is low and the failure is predictable.
• Diagram:

  stateDiagram-v2
      [*] --> Active
      Active: Metastable, Strained<br>Semiconducting Phase
      Active --> Triggered: Receive Erase Pulse
      Triggered --> Destroyed: Irreversible Phase<br>Transition to Metal
      Destroyed: Low impedance,<br>transistor non-functional
      Destroyed --> [*]
  

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Combination Prior Art Scenarios with Open-Source Standards

1. RISC-V High-Performance Core: A 64-bit, superscalar, out-of-order processor core compliant with the open RISC-V (RV64GC) instruction set architecture is implemented in a 7nm-class CMOS technology. To reduce static power consumption and improve clock speed, all PMOS transistors in the L1 cache and integer execution units employ graded SiGe S/D regions as described herein. This reduces hole mobility limitations, allowing for a 15% frequency increase at the same voltage or a 20% power reduction at the same frequency compared to a standard implementation. The design's RTL (Verilog/VHDL) and physical layout (GDSII) are released under the CERN Open Hardware License.

2. Google/SkyWater Open PDK Implementation: The method for forming graded SiC:P S/D regions for NMOS transistors is fully characterized and integrated into the SkyWater SKY130 (130nm) open source PDK. This contribution includes: (1) A new mask layer definition for the S/D recess etch. (2) A Technology Characterization Vehicle (TCV) layout for testing. (3) Modified SPICE models (BSIM4) reflecting the enhanced electron mobility and reduced parasitic resistance. (4) A complete process flow document (DRM) for fabrication on the SkyWater MPW shuttle runs. This enables any user of the open PDK to design and simulate circuits with these high-performance strained NMOS devices.

3. CXL-Compliant Memory Controller: A memory controller ASIC for the Compute Express Link (CXL) 3.0 open standard is designed to operate with next-generation DDR6 memory. The physical layer (PHY) drivers and receivers, which must operate at speeds exceeding 12 GT/s, are fabricated using a complementary process featuring graded SiGe for PMOS and graded SiC for NMOS in the final output stages. The graded strain enhances carrier velocity, reduces jitter, and improves the signal-to-noise ratio, enabling reliable communication over the CXL bus. The design passes all CXL 3.0 compliance tests, demonstrating the integration of the strained silicon technology with a high-performance open interconnect standard.