US 7288822

Analysis of U.S. Patent No. 7,288,822

Date of Analysis: May 13, 2026

This report provides a summary of United States Patent number 7,288,822, including its key bibliographic details, a summary of its abstract, and a plain-language explanation of its independent claims. A search for related litigation in the 2026 dockets of the U.S. Court of Appeals for the Federal Circuit (CAFC) was conducted, with no specific results found for this patent.

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I. Bibliographic Information

Field	Details
Patent Number	7,288,822 B1
Title	Semiconductor structure and fabricating method thereof
Assignee	Initially assigned to United Microelectronics Corp. As of the latest public records, the current assignee is Marlin Semiconductor Ltd.
Inventors	Shyh-Fann Ting, Cheng-Tung Huang, Wen-Han Hung, Li-Shian Jeng, Kun-Hsien Lee, Tzyy-Ming Cheng, Jing-Chang Wu, Tzermin Shen
Filing Date	April 7, 2006
Issue Date	October 30, 2007

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II. Abstract

The patent describes a semiconductor structure that includes two different types of MOS (Metal-Oxide-Semiconductor) transistors on a single substrate. One of these transistors features a "strained layer" in its source and drain regions. This strained layer is engineered with a non-uniform crystal lattice structure. Specifically, the lattice parameter difference between the strained layer and the substrate is smaller at the bottom of the layer and greater towards the top. This design is intended to reduce defects at the interface between the strained layer and the substrate, thereby improving the performance and reliability of the transistor. The second transistor on the substrate can be of a different type.

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III. Plain-Language Overview of Independent Claims

US Patent 7,288,822 has three independent claims: 1, 7, and 11. These claims define the core inventions protected by the patent.

Independent Claim 1:

This claim describes the fundamental structure of the semiconductor device. It covers a chip that has:

• A base material (substrate) with two specially prepared regions (wells), each with a different electrical conductivity type (referred to as first and second conductivity types).
• A first transistor of the "first conductivity type" built on top of the second well. This transistor has a standard gate structure and, crucially, its source and drain regions are made from a "strained layer."
• The key feature of this strained layer is that the mismatch in the crystal structure (lattice parameter) between it and the substrate is intentionally varied. The mismatch is smaller at the bottom of the layer and increases towards the top. This gradual change in strain is designed to improve the device's quality.
• A second transistor of the "second conductivity type" is also present on the first well.

In simple terms, this claim protects a semiconductor design with two types of transistors, where at least one has a specially engineered source and drain region with a gradient of crystal lattice strain to enhance performance.

Independent Claim 7:

This claim builds upon the structure described in Claim 1, but further specifies the nature of the second transistor. It states that the second MOS transistor includes:

• A second gate structure on the first well.
• A standard source/drain region of the second conductivity type located in the first well, adjacent to the second gate structure.

Essentially, this claim narrows the scope of Claim 1 by defining the second transistor as a more conventional transistor with a standard source and drain, as opposed to one that also necessarily has a strained layer.

Independent Claim 11:

This claim also refers back to the fundamental structure of Claim 1 but describes a more complex and specific embodiment for the second transistor. It details that the second MOS transistor comprises:

• A second gate structure on the first well.
• A second strained layer of the second conductivity type, which is located in a recess (a "second opening") in the first well next to the second gate.

This claim protects a more advanced version of the semiconductor structure where both types of transistors utilize strained-layer technology in their source and drain regions to improve performance.

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IV. Litigation Search

A search of the U.S. Court of Appeals for the Federal Circuit (CAFC) dockets for the year 2026 was performed for any cases involving US Patent 7,288,822. As of the date of this report, no specific litigation records for this patent were found in the publicly accessible docket information for that period. It is important to note that this does not definitively mean no litigation exists, as there can be delays in case reporting or the search may not capture all relevant filings. Further monitoring of district court and Patent Trial and Appeal Board (PTAB) databases may be necessary for a more comprehensive litigation assessment.