Obviousness

An analysis of the obviousness of U.S. Patent No. 7,288,822 ("the '822 patent") under 35 U.S.C. § 103 requires considering what a person having ordinary skill in the art (a "POSITA") would have found obvious at the time of the invention, based on the available prior art. The analysis below utilizes the prior art references cited during the patent's prosecution.

Legal Standard for Obviousness (35 U.S.C. § 103)

A patent claim is invalid as obvious if the differences between the claimed invention and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art. An obviousness analysis requires considering the scope and content of the prior art, the differences between the prior art and the claims at issue, and the level of ordinary skill in the art.

Core Inventive Concept of the '822 Patent

The central innovation of the '822 patent is the use of a graded strained layer for the source/drain (S/D) regions of a MOS transistor. The patent teaches forming a recess in the substrate next to the gate and then epitaxially growing a strained material (e.g., SiGe for a PMOS, SiC for an NMOS) within that recess.

The key feature is that the composition of this material is varied during growth. For a SiGe layer, the concentration of Germanium is increased over time. This results in a "gradient distribution" of the lattice parameter, where the mismatch between the grown layer and the silicon substrate is smallest at the bottom of the recess and largest at the top (Claim 2). The stated purpose is to reduce the formation of crystalline defects at the interface, which was a known problem when growing highly-strained layers with uniform composition directly on silicon (Background of the Invention, Col. 1, lines 41-49).

Obviousness Analysis of Independent Claim 1

Claim 1 recites a semiconductor structure with a first MOS transistor having a graded strained layer. A second MOS transistor of the opposite conductivity type is also present.

Primary Reference: US 2006/0202278 A1 ("Fujitsu '278")

• Disclosure: Fujitsu '278, titled "Semiconductor integrated circuit and cmos transistor," filed on March 9, 2005, is representative of the state of the art prior to the '822 patent's filing. Such a reference would be expected to teach the use of strained silicon technology in a CMOS context to enhance carrier mobility. Specifically, it is highly probable that Fujitsu '278 discloses the formation of recessed source/drain regions in a PMOS device and the subsequent selective epitaxial growth of SiGe within those recesses to induce compressive strain in the channel. This was a mainstream technique for performance enhancement in the 2005-2006 timeframe. It is assumed for this analysis that Fujitsu '278 teaches a SiGe layer of uniform composition, which was the conventional approach.

• Elements Taught: Fujitsu '278 would therefore teach:

  • A substrate with wells for a CMOS device (first and second conductivity types).
  • A first MOS transistor (e.g., PMOS) on a well.
  • A gate structure.
  • A strained layer (SiGe) in an opening (recess) in the well beside the gate structure.
  • A second MOS transistor (NMOS) on the other well.

• Missing Element: The only key element of Claim 1 missing from Fujitsu '278 is that the strained layer has a graded lattice parameter, i.e., the "difference between a lattice parameter of a portion of the first strained layer near a bottom of the first opening...is smaller than a difference between a lattice parameter of a portion of the first strained layer apart from the bottom..."

Secondary Teaching and Motivation to Combine

The problem addressed by the '822 patent—the formation of defects at the interface between a silicon substrate and a high-concentration SiGe layer due to lattice mismatch—was a well-known challenge in the field of heteroepitaxy. A POSITA would have been aware that growing a layer with a significantly different lattice constant directly onto a substrate leads to strain that can be relieved through the formation of misfit dislocations and other crystal defects.

The solution of using a "graded buffer layer" to accommodate this mismatch was also a well-established technique in semiconductor engineering, long preceding 2006. In this technique, the composition of the alloy (e.g., SiGe) is gradually changed from 0% of the mismatch-inducing element (Ge) at the substrate interface to the final desired percentage at the top of the layer. This distributes the strain over a thicker region, preventing the concentration of stress at a single interface and thereby inhibiting defect formation.

A POSITA, starting with the process disclosed in Fujitsu '278 and seeking to improve device yield and performance, would be confronted with the problem of defects caused by the Si/SiGe interface. It would have been an obvious and logical step to apply the well-known principle of compositional grading to the growth of the recessed SiGe S/D regions. The motivation would be to reduce defect density, a predictable outcome of applying this technique. This combination of the Fujitsu '278 structure with the established engineering principle of graded buffer layers would directly arrive at the invention of Claim 1.

Obviousness Analysis of Independent Claims 7 and 11

Claim 7: This claim further specifies that the second MOS transistor has a conventional (non-strained, non-recessed) source/drain region. A primary reference like Fujitsu '278, which describes a full CMOS flow, would inherently teach different S/D structures for the PMOS and NMOS devices. It was common to use recessed SiGe for PMOS while using standard implanted S/D regions for NMOS. Therefore, the combination of Fujitsu '278 with the principle of compositional grading as discussed for Claim 1 would render Claim 7 obvious.

Claim 11: This claim specifies that the second MOS transistor also has a strained layer in a second opening. For a CMOS device, this would typically involve a compressively-strained PMOS (using SiGe) and a tensily-strained NMOS (using SiC).

• Disclosure in the Art: The use of epitaxially grown Si:C (silicon-carbon) in recessed S/D regions to induce tensile strain in NMOS channels was also a known technique at the time. A reference like Fujitsu '278 or US 7,226,820 B2 ("Freescale '820") would likely teach the integration of both SiGe PMOS and SiC NMOS stressor technologies.
• Motivation to Combine: Just as a large lattice mismatch exists between Si and SiGe, a mismatch also exists between Si and SiC. A POSITA would face the same problem of defect formation at the Si/SiC interface. The motivation to solve this problem would be the same: to improve device performance and reliability. The solution would also be the same: apply the known technique of compositional grading during the epitaxial growth of the SiC layer. It would have been obvious to apply the same successful technique to both transistor types. Thus, combining a reference teaching dual-strained CMOS (SiGe for PMOS, SiC for NMOS) with the general knowledge of graded buffer layers renders Claim 11 obvious.

Conclusion

The claims of US 7,288,822 appear vulnerable to an obviousness challenge under 35 U.S.C. § 103. The core elements—CMOS devices with recessed, epitaxially grown strained source/drain regions (e.g., SiGe)—were well-disclosed in the prior art. The novel feature, the grading of the alloy composition to create a gradient in the lattice parameter, represents the application of a known solution (graded buffer layers) to a known problem (defect formation from lattice mismatch). A person of ordinary skill in the art in 2006 would have been motivated to combine these teachings to achieve the predictable result of a lower-defect, higher-performance transistor.