Derivative works — US Patent 7288822

Defensive Disclosure: Graded-Strain Semiconductor Structures and Applications

Publication Date: May 13, 2026
Subject: This document discloses novel derivative works, applications, and integrations of semiconductor structures incorporating graded-strain source/drain (S/D) regions, particularly those described in U.S. Patent 7,288,822. The purpose of this disclosure is to place these concepts in the public domain, thereby establishing prior art against future patent applications claiming these or obvious variations thereof.

Axis 1: Material & Component Substitution

Derivative 1.1: Graded-Strain Realization via Digital Alloy Superlattice

Enabling Description: Instead of achieving a continuous concentration gradient by ramping gas flow rates during epitaxy, the strained layer is constructed as a superlattice of alternating, atomically thin layers. For a compressive SiGe layer, a stack of Si/SiGe/Si/SiGe... is grown. The gradient is achieved by varying the thickness of the SiGe layers (e-g., from 1 monolayer to 10 monolayers) or by varying the Germanium concentration in each discrete SiGe layer while keeping the layer thickness constant. This "digital alloy" approach provides angstrom-level control over the strain profile, allowing for non-linear gradients (e.g., parabolic, exponential) that can be optimized to minimize threading dislocation propagation. The fabrication uses standard Molecular Beam Epitaxy (MBE) or Atomic Layer Epitaxy (ALE) techniques.

Diagram:

graph TD
    subgraph S/D Recess
        A[Substrate: Si] --> B(Layer 1: Si/SiGe 5% Ge);
        B --> C(Layer 2: Si/SiGe 10% Ge);
        C --> D(Layer N: Si/SiGe 40% Ge);
        D --> E[Cap Layer: Si];
    end
    E --> F[Metal Silicide Contact];
    style A fill:#f9f,stroke:#333,stroke-width:2px
    style E fill:#ccf,stroke:#333,stroke-width:2px

Derivative 1.2: Graded III-V Compound Semiconductors in S/D Recesses on Silicon

Enabling Description: For high-mobility NMOS channels, the silicon substrate in the S/D recess is replaced with a graded buffer layer of InxAl1-xAs, culminating in a final layer of high-Indium content InxGa1-xAs (x > 0.53). The grading of the InAlAs layer, from x=0 at the Si interface to x=0.52, accommodates the significant lattice mismatch between Si and InGaAs. This is achieved via Metal-Organic Chemical Vapor Deposition (MOCVD) by precisely controlling the flow of Trimethylindium, Trimethylaluminum, and Arsine precursors. This structure provides a high-mobility electron injection source directly into the silicon channel, drastically reducing on-resistance (Ron).

Diagram:

sequenceDiagram
    participant Substrate as Silicon Substrate
    participant MOCVD as MOCVD Reactor
    participant S_D_Region as S/D Recess
    MOCVD->>S_D_Region: Deposit Graded InAlAs Buffer
    Note right of MOCVD: Vary Trimethylindium flow
    MOCVD->>S_D_Region: Deposit high-mobility InGaAs
    S_D_Region->>Substrate: Induce high tensile strain

Derivative 1.3: Ternary and Quaternary Graded Alloy Systems (SiGeSn, SiC:P)

Enabling Description: This disclosure extends the concept to ternary SiGeSn alloys for PMOS and phosphorus-doped SiC (SiC:P) for NMOS. For PMOS, a Si1-x-yGexSny layer is grown in the S/D recess. The gradient is achieved by first ramping the Ge concentration (x) and then introducing and ramping the Sn concentration (y). The larger Sn atoms provide a more efficient way to induce compressive strain than Ge alone. For NMOS, a Si1-yCy layer is grown while simultaneously flowing a phosphorus precursor (e.g., PH3). The phosphorus co-doping alters the lattice constant, providing an additional mechanism to control the tensile strain gradient beyond just carbon concentration.

Diagram:

stateDiagram-v2
    [*] --> Epitaxy_Start
    Epitaxy_Start: Gas Flow: SiH4
    Epitaxy_Start --> Ge_Ramp: Introduce GeH4
    Ge_Ramp: Flow(GeH4) = k1 * t
    Ge_Ramp --> Sn_Ramp: Introduce SnCl4
    Sn_Ramp: Flow(GeH4) = const, Flow(SnCl4) = k2 * t
    Sn_Ramp --> Epitaxy_End: Stop all precursors
    Epitaxy_End --> [*]
    note right of Ge_Ramp: Creates SiGe gradient
    note right of Sn_Ramp: Creates SiGeSn gradient

Axis 2: Operational Parameter Expansion

Derivative 2.1: Cryogenic-Optimized Graded Strain for Quantum Computing

Enabling Description: A semiconductor structure for hosting spin qubits, designed for operation at sub-1 Kelvin temperatures. The S/D regions of the control FETs are formed from a graded SiGe alloy. The gradient profile is specifically calculated using finite element analysis (FEA) to counteract the anisotropic thermal contraction of the silicon crystal lattice during cooldown from 300K to <1K. This pre-compensates for thermally-induced stress, resulting in a near-zero stress state at the Si/SiGe interface at operating temperature. This minimizes charge noise and potential fluctuations in the quantum dot region under the gate, increasing qubit coherence times (T2*).

Diagram:

graph LR
    A(Room Temp: 300K) -- Cool-down --> B(Cryo Temp: <1K);
    subgraph Transistor
        C(Si Substrate)
        D(Graded SiGe S/D)
    end
    A -- FEA Model --> E{Optimized<br>Ge Gradient};
    B -- Strain State --> F(Minimized Interface<br>Stress & Charge Noise);
    E --> D;
    C --- D;

Derivative 2.2: Nanoscale Application in Vertical GAA Nanosheet Transistors

Enabling Description: The principle of graded strain is applied to the source/drain regions of a vertically-stacked Gate-All-Around (GAA) nanosheet transistor. After the sacrificial layers between the Si or SiGe channel nanosheets are removed, recesses are etched at the source and drain ends. A graded epitaxial process fills these recesses, merging the contacts for all nanosheets in the stack. For a PMOS device, a graded SiGe layer is grown, with the gradient optimized to exert uniform compressive stress along the vertical axis of all stacked nanosheets. This ensures consistent performance (Ion/Ioff ratio) across all channels in the 3D structure.

Diagram:

classDiagram
    direction BT
    class V_GAA_FET {
      +GateMaterial
      +Dielectric
      +StackedNanosheets[]
      +MergedSource
      +MergedDrain
    }
    class StackedNanosheets {
      +Material: SiGe
      +Thickness
    }
    class MergedSource {
      +Material: Graded SiGe
      +GradientProfile: Vertical
    }
    class MergedDrain {
      +Material: Graded SiGe
      +GradientProfile: Vertical
    }
    V_GAA_FET *-- "2" MergedSource
    V_GAA_FET *-- "N" StackedNanosheets

Axis 3: Cross-Domain Application

Derivative 3.1: Aerospace - Self-Calibrating Piezoresistive Gyroscope

Enabling Description: A MEMS gyroscope for spacecraft attitude control utilizes piezoresistive sensing elements made from graded SiGe. The gradient in the SiGe is engineered to create a temperature-invariant piezoresistive coefficient at a specific point within the layer. A separate, on-chip heater cycles the device temperature, and the system measures the response from different depths of the graded layer (using biased contacts). By comparing these signals, the system can self-calibrate, compensating for temperature-induced drift and the effects of long-term radiation exposure on material properties. The low-defect interface provided by the gradient ensures a low-noise floor for high-precision measurements.

Diagram:

flowchart TD
    A[Coriolis Force<br>on MEMS Mass] --> B{Strain in Piezoresistor};
    B --> C[Resistance Change<br>in Graded SiGe];
    D[On-Chip Heater] -- Modulates Temp --> C;
    C --> E{Multi-Depth Sensing};
    E --> F[Calibration Algorithm];
    F -- Corrected Signal --> G[Angular Rate Output];

Derivative 3.2: AgTech - Multiplexed Ion-Selective FET (ISFET) for Hydroponics

Enabling Description: An array of ISFETs on a single probe for monitoring nutrient levels (NO₃⁻, K⁺, Ca²⁺) in a hydroponics system. Each ISFET is an NMOS device fabricated with graded SiC:P S/D regions for enhanced electron mobility and chemical robustness against fertilizer salts. The gate dielectric of each transistor in the array is functionalized with a different ionophore-doped membrane, making it selectively sensitive to a specific ion. The graded strain S/D reduces 1/f noise, which is critical for detecting small concentration changes. The entire probe operates continuously, providing real-time data to an automated nutrient dosing system.

Diagram:

erDiagram
    PROBE ||--o{ ISFET_ARRAY : contains
    ISFET_ARRAY {
        string TransistorID
        string TargetIon
    }
    ISFET_ARRAY ||--|{ NMOS_TRANSISTOR : uses
    NMOS_TRANSISTOR {
        string S/D_Material "Graded SiC:P"
        string Gate_Membrane "Ion-Selective"
    }
    PROBE }|--|{ CONTROLLER : reports_to
    CONTROLLER ||--o{ NUTRIENT_DOSER : controls

Axis 4: Integration with Emerging Tech

Derivative 4.1: AI-Driven Dynamic Strain Control

Enabling Description: The semiconductor structure incorporates a back-gate or embedded micro-heaters adjacent to the graded SiGe S/D regions. The device is integrated into a system with an AI inference engine (e.g., a neural network accelerator). The AI monitors the transistor's real-time performance (e.g., ring oscillator frequency, leakage current). Based on the application's demands (e.g., high-performance vs. low-power mode), the AI dynamically adjusts the voltage on the back-gate or the power to the micro-heaters. This applies a piezoelectric or thermoelectric stress, respectively, which adds to or subtracts from the built-in strain from the graded S/D, actively "tuning" the carrier mobility of the transistor in real-time for optimal power-performance trade-offs.

Diagram:

sequenceDiagram
    participant App as Application
    participant AI as AI Controller
    participant Transistor as Graded-Strain FET
    loop Real-Time Operation
        App->>AI: Request Performance State (e.g., Turbo)
        AI->>Transistor: Apply Back-Gate Bias
        Note over Transistor: Piezoelectric effect<br>modifies channel strain
        Transistor-->>AI: Feedback (Leakage, Temp)
        AI->>AI: Adjust Bias based on Model
    end

Derivative 4.2: IoT Sensor Mesh for Structural Health Monitoring

Enabling Description: A flexible polymer sheet is embedded with a high-density mesh of CMOS circuits, where each node contains a PMOS transistor with graded SiGe S/D regions. This sheet is bonded to a critical engineering structure, such as an aircraft wing or bridge support beam. When the structure flexes, it imparts stress onto the transistors. The inherent piezoresistive properties of the strained SiGe cause a measurable change in the transistor's I-V characteristics. Each node in the mesh periodically wakes up, measures its local strain, and transmits the data wirelessly to a central hub. This creates a high-resolution, real-time 3D map of the structure's stress and fatigue state. The graded S/D is critical for device durability under mechanical cycling.

Diagram:

graph TD
    subgraph AircraftWing
        A(Node 1: Strain Sensor)
        B(Node 2: Strain Sensor)
        C(Node ...N)
    end
    subgraph Node
        P[PMOS w/ Graded SiGe S/D]
        M[Microcontroller]
        R[Radio Transceiver]
    end
    P -- I-V Curve Shift --> M;
    M -- Strain Data --> R;
    A --> X[Central Hub];
    B --> X;
    C --> X;
    R -- Wireless Tx --> X;
    X --> Y[Structural Health<br>Dashboard];

Axis 5: The "Inverse" or Failure Mode

Derivative 5.1: Controlled Failure via Strain-Induced Phase Transformation

Enabling Description: A transient electronic device designed for secure data applications, where the device must be verifiably and rapidly disabled. The S/D regions are constructed from a graded metastable alloy, such as a specific composition of Vanadium Dioxide (VO₂) integrated with silicon. Under normal operation, the strain keeps the VO₂ in its semiconducting phase. A trigger signal (e.g., a voltage pulse to an embedded heater) provides a small amount of thermal energy. This energy, combined with the high potential energy stored in the strained lattice, initiates an irreversible, exothermic semiconductor-to-metal phase transition. The transition propagates rapidly through the S/D regions, shunting the gate and permanently destroying transistor function in microseconds. The gradient ensures the trigger energy is low and the failure is predictable.

Diagram:

stateDiagram-v2
    [*] --> Active
    Active: Metastable, Strained<br>Semiconducting Phase
    Active --> Triggered: Receive Erase Pulse
    Triggered --> Destroyed: Irreversible Phase<br>Transition to Metal
    Destroyed: Low impedance,<br>transistor non-functional
    Destroyed --> [*]

Combination Prior Art Scenarios with Open-Source Standards

RISC-V High-Performance Core: A 64-bit, superscalar, out-of-order processor core compliant with the open RISC-V (RV64GC) instruction set architecture is implemented in a 7nm-class CMOS technology. To reduce static power consumption and improve clock speed, all PMOS transistors in the L1 cache and integer execution units employ graded SiGe S/D regions as described herein. This reduces hole mobility limitations, allowing for a 15% frequency increase at the same voltage or a 20% power reduction at the same frequency compared to a standard implementation. The design's RTL (Verilog/VHDL) and physical layout (GDSII) are released under the CERN Open Hardware License.
Google/SkyWater Open PDK Implementation: The method for forming graded SiC:P S/D regions for NMOS transistors is fully characterized and integrated into the SkyWater SKY130 (130nm) open source PDK. This contribution includes: (1) A new mask layer definition for the S/D recess etch. (2) A Technology Characterization Vehicle (TCV) layout for testing. (3) Modified SPICE models (BSIM4) reflecting the enhanced electron mobility and reduced parasitic resistance. (4) A complete process flow document (DRM) for fabrication on the SkyWater MPW shuttle runs. This enables any user of the open PDK to design and simulate circuits with these high-performance strained NMOS devices.
CXL-Compliant Memory Controller: A memory controller ASIC for the Compute Express Link (CXL) 3.0 open standard is designed to operate with next-generation DDR6 memory. The physical layer (PHY) drivers and receivers, which must operate at speeds exceeding 12 GT/s, are fabricated using a complementary process featuring graded SiGe for PMOS and graded SiC for NMOS in the final output stages. The graded strain enhances carrier velocity, reduces jitter, and improves the signal-to-noise ratio, enabling reliable communication over the CXL bus. The design passes all CXL 3.0 compliance tests, demonstrating the integration of the strained silicon technology with a high-performance open interconnect standard.