US 7194244

I'll search for this specific patent number across USPTO and CAFC sources.

Let me search specifically for litigation/PTAB/CAFC activity involving this patent number.

Let me run two more targeted searches to check for any Federal Circuit or PTAB activity and confirm the family/status details.

Search note

I searched for the exact identifier 7194244 / US 7,194,244 with USPTO-oriented and Federal Circuit queries. I found no CAFC 2026 docket, notice of appeal, or PTAB proceeding naming this patent. The only hits were the patent record itself (Google Patents), two inventor-tracking aggregator pages, and unrelated documents that happened to cite different '244-suffixed patents (e.g., U.S. 6,889,244; U.S. 7,300,194; U.S. 8,076,194). I could not pull a live USPTO PatentCenter or PACER/CAFC docket record directly, so absence of litigation is an inference from search coverage, not an authoritative confirmation. Given the patent's fee-related expiration in 2023 (below), active 2026 appellate litigation would be unlikely.

US 7,194,244 B2 — Bibliographic summary

Abstract (as recorded)

A wireless communication receiver that is able to lessen the effect of noise that accompanies gain change by programmable gain amplifiers. The receiver includes an AGC controller which controls the timing at which the programmable gain amplifiers make gain change, using a terminal counter and a sequencer. The receiver prevents gain change noise signals during the reception of control signals and other signals that are susceptible to noise. By the timing control feature, the programmable gain amplifiers make gain change while reducing noise impact.

Plain-language overview

Technical problem. In a direct-conversion (single-downconversion) CDMA/W-CDMA receiver, discrete-step programmable gain amplifiers (PGAs) behind the mixer produce a DC-offset step each time the gain is switched between differential pairs. That step, once high-pass filtered, injects low-frequency noise into the wanted baseband for tens of microseconds — long enough to corrupt short, non-error-corrected control signals (TPC, TFCI, Pilot) in the DPCH slot.

Claim 1 (independent). A receiver with (a) a first mixer that downconverts received signals once to baseband and (b) a first PGA in series after the mixer having discrete gain steps. It includes a circuit for reducing noise caused by the discrete gain change because of DC offsets, and that circuit is a timing control circuit that times the gain change using the received signal's frame structure — i.e., shift the gain transition to a moment in the frame where the injected noise does least harm.

Claim 9 (independent). A receiver with a mixer plus multiple cascaded PGA stages built from differential-pair transistors, defined by two structural variants:

• The first-stage PGA: switched resistor networks (resistors in series with switches) on each emitter leg are joined through one capacitor across the emitters (AC-coupled, switched emitter-degeneration).
• At least one intermediate stage (not first, not last): the two emitters are joined by parallel resistors with series switches (no emitter capacitor).

Claim 10 (independent). As in claim 1, but the timing control is specified to move gain change to the time the receiver is receiving a specific error-corrected, noise-robust signal in the frame (the data fields, not the unprotected control fields).

Claim 11 (independent). As in claim 1, but the timing control instead places gain change at a random time within the frame, so that the noise event cannot systematically coincide with a particular noise-sensitive signal.

Claim 12 (independent). As in claim 1, but the timing control circuit explicitly comprises (i) a time-measuring device synchronized to the frame structure and (ii) a device storing the frame structure, and it forces gain change to occur outside the receive window of the specific error-corrected signal.

Dependent claims. Claims 2–4 add that the PGA itself suppresses the gain-change noise (claim 3: emitters of the differential pair coupled by a capacitor; claim 4: collectors also coupled by a capacitor). Claims 5–8 add frame-formatted, non-intermittent (CDMA) reception, and variously the error-corrected-signal timing (5), random timing (6), frame-sync counter plus frame storage (7), and a hysteresis characteristic on the first-stage PGA to reduce how often the first stage switches (8).

Caveats

• The full text and claims above are from the Google Patents record for US 7,194,244, which is the authoritative source supplied; my independent searches corroborated the title, inventorship, issue date, and assignee but did not add a USPTO copy.
• I found no evidence of a 2026 CAFC appeal or other litigation for this patent number specifically. If an authoritative docket is required, this should be confirmed directly in USPTO PatentCenter and the CAFC/PACER dockets rather than inferred from web search.

I'll search patent-litigation sources for this specific patent number.

Let me check litigation-specific databases directly.

Let me check the dedicated patent-litigation databases for this exact number.

Bottom line

No litigation naming US Patent 7,194,244 ("Wireless communication receiver," Renesas) was found. No district-court action, ITC investigation, PTAB proceeding, or CAFC appeal asserting or challenging this patent number appears in any of the litigation-oriented sources I could reach. This is consistent with — and adds specificity to — the earlier section, which likewise found no CAFC 2026 docket or PTAB proceeding for this number.

One small flag on the record: the earlier section was generated against a fetch date of 2026‑09‑30, while this task states April 26, 2026. I have treated the searches as run "as of now" and have not tried to reconcile those two dates; nothing in the results turns on the difference.

What I searched and what came back

I could not open the Unified Patents litigation case-list page directly, nor a PACER/CAFC docket query (both require interactive access / authentication). The negative finding is therefore an inference from search coverage, not an authoritative docket confirmation — same caveat the earlier section gave, and it still stands.

False positives I excluded (interpreted literally, not auto-corrected)

These are the only meaningful "7194244" hits, and none is patent litigation:

1. archive.org "3-5-04 BeenServedList" — shows 7194244 Reflex Communications, 83 South King Street, Suite 106, Seattle, WA 98104, sandwiched between 7194241 and 7194245. The sequential numbering and the address/company format identify this as a telephone number (area code 719 = Colorado Springs), not a patent. Note the same document's nearby hit 7194235 RedStorm Scientific, Inc is likewise a phone number.
2. Kentucky Department of Insurance licensee record — NAIC NPN: 7194244 for licensee Kathryn B. Fey. An insurance producer number.
3. E.D. Cal. bankruptcy, Point Buckler Club, LLC, No. 2:23‑bk‑20755 — eFilingID: 7194244. A CM/ECF internal filing ID.
4. Mathematical/scientific literature — Φ(7194244, 33) = … in an 1885 Mathematische Annalen paper (and a Zenodo paper on prime counts); an unrelated Beijing Municipal Natural Science Foundation grant No. 7194244.
5. Other, similarly-numbered patents appearing in real complaints but not this patent: U.S. 7,300,194 (IDT v. Dell/Sony); U.S. 6,092,194, 6,218,194 (Finjan / SRU Biosystems); U.S. 5,815,649-related "244 Patent" in Valtrus v. SAP; U.S. 9,270,244 (Samsung v. Staton Techiya, IPR2022‑00281).

Related context worth recording (not litigation of this patent)

• Renesas as a defendant is heavily litigated — e.g., Ad Innovations, LLC v. Renesas Electronics America Inc., N.D. Cal. 4:26‑cv‑06655 (filed 2026); Signal, LLP v. Renesas Electronics Corp., E.D. Tex. 2:26‑cv‑00093 (filed 2026); Navitas Semiconductor Ireland, LLC v. Renesas Electronics Corp., E.D. Tex. 2:26‑cv‑00676; TurboCode LLC v. Renesas Electronics America Inc., W.D. Tex. 7:25‑cv‑00459 (voluntarily dismissed 2025); Invensas v. Renesas (D. Del., 2011); Zond LLC v. Renesas (D. Mass., judgment for Renesas 2017). None of these asserts US 7,194,244, and I did not verify each one's patent list beyond the exhibits visible in the search snippets.
• Why absence is plausible: the record shows the patent expired for fee-related reasons with an adjusted expiration of 2023‑06‑25. An expired patent was asserted nowhere in the family record; the continuation US 11/702,493 went abandoned; the only family filings are the Japanese, Chinese, and Taiwanese counterparts (JP 3770819 B2, CN 100539487 C, TW 595094 B).
• The only "cited by" references for this patent (Hmicro, GM, Atsushi Yoshizawa, etc.) are later patent citations, not litigation.

If you need an authoritative negative

Because my finding is search-based, I'd confirm directly in: (a) USPTO PatentCenter → "Litigation" / assignment and Ex Parte Reexamination tabs for 7,194,244; (b) PACER → nationwide party search for "7,194,244"; (c) CAFC docket search; (d) Unified Patents litigation portal case-list (https://portal.unifiedpatents.com/litigation/caselist) filtered on the patent; and (e) RPX/Docket Navigator if licensed. I could not complete (d) and could not reach (a)–(c) as live authenticated queries within my tooling.

Stated plainly: as of this analysis, zero litigation is known for US 7,194,244. That is a "no known cases" answer, not a certified negative.

Proceedings overview

Zero AIA trial proceedings. The structured "PTAB proceedings on file" block — the canonical USPTO Open Data Portal list — returns an empty set for US 7,194,244: 0 IPRs, 0 PGRs, 0 CBM reviews, 0 derivation proceedings, and therefore 0 institutions, 0 final written decisions, 0 settlements, 0 Federal Circuit appeals arising from a Board trial. There is no proceeding number to report, because none exists — and I will not manufacture one.

The defensive posture is therefore not "hardened by surviving IPRs" (that framing would be wrong — the patent has never been tested at the Board), and it is not "claims canceled" either. The real bottom line for a defendant is different and stronger than either: US 7,194,244 is expired. Google Patents records the legal status as "Expired – Fee Related" with an adjusted expiration of 2023-06-25, and the file wrapper shows no post-grant challenge anywhere in its ~21-year life. A demand letter citing this patent in 2026 is asserting an expired patent; the only theoretically live exposure is a lookback claim for past infringement under the 35 U.S.C. § 286 six-year bar (roughly conduct from 2020-09-30 through 2023), and even that is subject to the patent's non-assertion history and any laches/notice defenses.

No proceedings to profile — what I actually checked

Because there is nothing to put in the per-proceeding template, here is the negative evidence trail instead:

False positives I explicitly discarded (do not let these mislead a clearance review):

• U.S. 11,396,244 — Toyota Motor Corp. v. Emerging Automotive LLC, IPR2024-00814. Different patent, different field (EV charging/telematics). Not related.
• InterDigital's "244 patent" (the IPR Licensing v. ZTE PTAB remand appeal referenced in InterDigital's 10-Q) — a different '244-suffixed number entirely. Not related.
• "7194244 Reflex Communications, 83 South King Street, Seattle" in a 2004 served-party list archive — this is a 9-digit postal/ZIP+4 or list-index artifact, not a patent reference. Pure numeric coincidence.
• U.S. 7,623,439 / U.S. 8,284,844 / U.S. 7,194,244-adjacent hits out of the Renesas–Broadcom and Renesas–Bell Semiconductor disputes involve entirely different patents.

Strategic summary

Claim status on US 7,194,244: all 12 claims are UNTESTED and all are EXPIRED. No claim has been canceled, confirmed, disclaimed, or cancelled by certificate; there has been no ex parte reexam, no inter partes reexam, no reissue, and no supplemental examination surfaced. The claims stand exactly as granted on 2007-03-20 — independent claims 1, 9, 10, 11, and 12, with dependents 2–8 intact. The continuation US 11/702,493 (US 2007/0142012 A1) went abandoned, so there is no live sibling claim set in the family to assert in the alternative. The family is effectively cold: JP 3770819 B2 (Japan) and CN 100539487 C (China) would have their own national terms; TW 595094 B is a Taiwanese filing.

Estoppel landscape: § 315(e)(2) is irrelevant here, and that cuts against the patent owner, not for it. Because no IPR/PGR was ever instituted, there is no petitioner estoppel, no Sotera stipulation, and no Board record a defendant can lean on. Equally, there is no IPR-based defensive shortcut. If you are a defendant today, the invalidity case must be built from scratch in district court under §§ 102/103/112 — and the good news is that the field it sits in (direct-conversion receiver AGC with switched-emitter-degeneration PGAs) was crowded by 2001. The patent's own specification cites the Feb. 2001 ISSCC direct-conversion W-CDMA paper ("A 22 mA 3.7 dB NF Direct Conversion Receiver for 3G WCDMA," ISSCC Digest, pp. 284–285) and M. Goldfarb et al., "Analog Baseband IC for Use in Direct Conversion W-CDMA Receivers," 2000 IEEE RFIC Symposium, pp. 79–89, plus a stack of Japanese Kokai publications (2001-36362; 2001-36367; 2001-44776; 2001-53564; 2001-111523) that the examiner evidently considered during prosecution and the applicant distinguished. Those are natural starting points, but note the § 325(d)-style risk is the reverse problem: a court may view them as already-before-the-Office art.

Pattern signals: there are none, and that is the story. The absence of any IPR over a two-decade term is itself diagnostic. Well-asserted, commercially meaningful semiconductor patents in crowded analog/RF art attract IPRs quickly — Renesas, the assignee here, was on the receiving end of IPRs in other disputes (e.g., the Bell Semiconductor/Integrated Device Technology campaigns, where Renesas Electronics America was the real party in interest). That this patent never drew a petition, never appeared in an ITC complaint, and never produced a CAFC docket strongly suggests it was never asserted, or was asserted only as part of a portfolio that settled before institution. I found no evidence of a defensive aggregator (Unified Patents, RPX, AST) ever challenging it.

Recommended next steps

1. Confirm the expiration basis directly before relying on it. Google Patents labels the status "Expired – Fee Related" (a label it typically applies to maintenance-fee lapses), yet the recorded "Adjusted expiration 2023-06-25" is also consistent with the 20-year term from the 2002-09-25 filing plus roughly nine months of patent term adjustment. If the patent lapsed early for non-payment of a maintenance fee, it was dead sooner than 2023-06-25. Pull the maintenance-fee history and the term/adjustment record in USPTO PatentCenter (https://patentcenter.uspto.gov — application 10/253,648) and the fee history in the Patent Maintenance Fee Store. Expiration date precision matters for any § 286 damages window analysis.
2. Run the dockets, not just the web. The web search coverage here is strong negative evidence but not authoritative. Confirm on PTAB E2E / PTAB Center (https://ptab.uspto.gov) and via CourtListener/RECAP (https://www.courtlistener.com/?q=%227194244%22) and Docket Navigator that no petition, ITC complaint, or district court case names 7,194,244. Use the assignee chain as search terms: Renesas Electronics Corp., Renesas Technology Corp., Hitachi Ltd.
3. If a demand letter arrives, lead with expiration. Under 35 U.S.C. § 271, infringement requires making/using/selling/offering for sale during the term. Post-2023-06-25 conduct by definition cannot infringe. Demand letters or complaints that fail to acknowledge expiration support a Rule 11 / § 285 fee posture.
4. If past-infringement damages are threatened (2020–2023 conduct), attack validity you cannot estop anyone else out of. There is no FWD to cite, so build your own: prior-art search around direct-conversion baseband AGC with discrete gain steps and frame-timing-controlled gain switching, including the ISSCC 2001 and Goldfarb 2000 references the specification itself admits. Note that claim 1's "because of their DC offsets" language and claim 12's "out of timing when a specific signal ... is received" language are ripe for § 112 indefiniteness and written-description challenges, given how broadly "specific signal" and "strong to noise impact by being error corrected" are used in the specification relative to the slot-level disclosure.
5. Do not build a defense around IPR estoppel. There is no proceeding, so there is nothing to estop, nothing to wait for, and no statutory trial deadline to track. Any suggestion by opposing counsel that "the PTAB already upheld these claims" would be false — all 12 claims are untested.

Caveats. The "no PTAB activity" finding rests on the canonical ODP block plus repeated web searches; ODP ingest lag is possible in principle, so treat this as a high-confidence but not infallible negative and verify in PTAB E2E before filing anything that depends on it. I did not obtain a live PatentCenter maintenance-fee record, so the precise expiration basis is flagged rather than asserted.

I'll search for the recorded assignment details (reel/frame, correspondent) and cross-reference the Renesas/Hitachi chain and any NPE databases.

Assignment & Ownership Analysis — US 7,194,244 B2

Scope note on sources. The authoritative full text supplied for this patent (Google Patents, fetched 2026‑09‑30) exposes only event dates for the assignments — it does not expose reel/frame numbers, execution dates, or the correspondent of record. My live searches could not reach the USPTO Assignment Center record view directly (assignmentcenter.uspto.gov / assignment.uspto.gov are not reliably indexable, and my query budget was exhausted). I therefore report reel/frame and correspondent as "not retrieved" rather than reconstructing them. Everything below is grounded in the recorded legal events listed on the patent record plus corroborating corporate documents. Any reel/frame value must be pulled directly at https://assignmentcenter.uspto.gov/ (search by patent number 7194244) before use in a filing.

Inventors

Eight named inventors (the unusually large co‑inventor group is itself worth noting):

Basis: all eight appear as grantors in the recorded assignment dated 2002‑10‑30 to HITACHI, LTD., which confirms Hitachi was the employer of record at filing. The application itself was filed 2002‑09‑25, with priority to JP 2001‑300296 (2001‑09‑28). The patent record's "application filed by Renesas Technology Corp" entry for 2002‑09‑25 is a retroactive attribution artifact of the corporate succession, not evidence that Renesas existed as filer (Renesas Technology Corp. was only incorporated 2003‑04‑01).

Unusual patterns — none found on the inventor side. No inventor is shown as having assigned to any entity other than Hitachi. No inventor is shown holding or assigning the patent individually. Third‑party aggregator data (patentleaderboard.com) lists Kajiwara as holding 8 US patents "at Renesas Technology," i.e., the inventorship group stayed with the semiconductor business through the corporate split. Important distinction: what changed within ~12 months of the assignment was the corporate employer of the whole division, not the inventors' individual departures. That is a corporate-succession signature, not the pre-fire-sale inventor-exodus signature this section is designed to catch. Per‑inventor movement cannot be confirmed from the record, so I flag this as not determinable at the individual level.

Original assignee

• Named on the issued patent (2007‑03‑20): Renesas Technology Corp. (Tokyo) — which is also the assignee of the 2003‑09‑26 assignment. At filing the assignee was Hitachi, Ltd.; the two are linked by the 2003‑04‑01 corporate split, so the chain reads Hitachi → Renesas Technology → Renesas Electronics.
• Primary line of business: semiconductor design/manufacture — microcontrollers, system LSI, mixed‑signal and analog ICs, memory. Renesas Technology was formed 2003‑04‑01 as a Hitachi (55%) / Mitsubishi Electric (45%) joint venture into which both parents' system LSI semiconductor businesses were split; it was described at formation as the world's largest microcontroller supplier and aimed at mobile, network, automotive and digital‑home markets (Hitachi press releases, 2002‑10‑03 and 2002‑12‑26; EC case 39574 recitals 16–18).
• Did they ship a product embodying the claims? Highly likely and consistent with the business: the patent is directed to the analog baseband / AGC front end of a direct‑conversion W‑CDMA receiver (the application's own background cites the ISSCC 2001 "22 mA 3.7 dB NF Direct Conversion Receiver for 3G WCDMA"), which is exactly the class of mobile‑phone baseband/RF IC that both Hitachi's and Renesas Technology's semiconductor divisions sold in that period. I could not locate a specific publicly catalogued part number in the sources reached, so this is stated as strongly indicated, not documentary.
• Current status: Operating. Renesas Electronics Corp. (TSE:6723) is the current listed assignee and remains an active, publicly traded semiconductor manufacturer; it acquired Intersil (2017), IDT (2019), Dialog (2021), Panthronics/Transphorm/Altium (2023–24). Note the ownership history: Hitachi and Mitsubishi Electric ceased to be major shareholders of Renesas on 2013‑09‑30 when INCJ took 69.16% (EC case 39574, recital 19) — a financial restructuring, not a bankruptcy and not an assignment of this patent.

Assignment timeline

Three recorded events touch this patent; all are internal corporate conveyances. Google Patents shows dates but no reel/frame; all reel/frame fields below are unverified placeholders pending Assignment Center retrieval.

• 2002‑10‑30 (date shown on patent record; execution date not exposed) / recorded 2002‑10‑30 — Reel not retrieved/not retrieved

  • Conveyance: Assignment (inventor → company)
  • Assignor: Yukinori Akamine; Hisayoshi Kajiwara; Satoshi Tanaka; Takashi Yano; Hirotake Ishii; Akio Yamamoto; Kazuaki Hori; Kazuhiko Hikasa
  • Assignee: HITACHI, LTD. (Tokyo, Japan)
  • Correspondent: not exposed in the sources reached — cannot flag recurrence
  • Context: standard employment assignment perfecting Hitachi's title to the invention shortly after the 2002‑09‑25 US filing; this is the only inventor‑side link in the chain.

• 2003‑09‑26 / recorded 2003‑09‑26 — Reel not retrieved/not retrieved

  • Conveyance: Assignment (corporate spin‑off / divestiture)
  • Assignor: HITACHI, LTD.
  • Assignee: RENESAS TECHNOLOGY CORPORATION
  • Correspondent: not retrieved
  • Context: internal reorg — Hitachi's semiconductor business was split into the Hitachi/Mitsubishi Electric JV Renesas Technology Corp. effective 2003‑04‑01, and the patent followed the business ("assets and contractual positions" transferred per the 2002‑10‑03 basic agreement). Not a sale to a third party; Mitsubishi Electric is a co‑parent of the transferee.

• 2010‑09‑02 / recorded 2010‑09‑02 — Reel not retrieved/not retrieved

  • Conveyance: Merger and Change of Name
  • Assignor: RENESAS TECHNOLOGY CORP.
  • Assignee: RENESAS ELECTRONICS CORPORATION
  • Correspondent: not retrieved
  • Context: change of name only (plus merger) — Renesas Technology merged with NEC Electronics on 2010‑04‑01 to form Renesas Electronics; the rights were not sold to anyone.

• No assignment events after 2010‑09‑02 are listed. The continuation application US 11/702,493 (filed 2007‑02‑06, published as US 2007/0142012 A1) shows no separate assignment event either and went abandoned; the patent itself went Expired – Fee Related with adjusted expiration 2023‑06‑25, i.e., maintenance fees lapsed while Renesas was still the owner. For completeness: the national family members (JP 3770819 B2, CN 100539487 C, TW 595094 B) carry no assignment data in the sources reached.

False-positive to discard: an archived 2004 "been served" list contains the strings "7194244 Reflex Communications, 83 South King Street, Seattle" adjacent to "7194235 RedStorm Scientific" and "7194241 Reelshort Com." These are sequential list/record numbers in a DMCA subpoena service list, not patent‑number references, despite the numeric match. Do not treat this as evidence of anything about US 7,194,244.

Timeline diagram

timeline
    title Ownership of US 7194244
    2001 : JP priority application filed 28 Sep
    2002 : US application filed 25 Sep
         : Inventors assign to Hitachi Ltd 30 Oct
    2003 : Hitachi chip unit split to JV 1 Apr
         : Assigned to Renesas Technology 26 Sep
    2007 : Patent issued 20 Mar
         : Continuation filed 6 Feb later abandoned
    2010 : Merger with NEC Electronics 1 Apr
         : Renesas Electronics Corp 2 Sep
    2023 : Patent expired fee related 25 Jun

NPE / troll-pattern signals

1. Shell-entity transfer — not present. The last recorded conveyance (2010‑09‑02) is a merger and change of name into Renesas Electronics Corporation, a publicly traded operating semiconductor maker. No assignee with an "IP / Holdings / Licensing / Ventures" suffix appears anywhere in the chain, and no post‑2010 transfer is recorded at all.
2. Known asserter in the chain — not present. Neither Hitachi, Ltd., Renesas Technology Corp., nor Renesas Electronics Corp. appears on the Acacia / Marathon / IV / Wi‑LAN / Conversant / Pendrell / Round Rock / Spangenberg lists or on Unified Patents' / RPX's high‑frequency‑plaintiff rosters. The cross‑reference runs the other way: Renesas Electronics appears in the Stanford NPE Litigation Database as an alleged infringer in suits brought by asserters (Koji IP, Monterey Research, MR Licensing, Bandspeed, Aido, Signal LLP), and in December 2011 Renesas filed a declaratory‑judgment action against three NPEs (Alliacense, HSM Portfolio, TPL; N.D. Cal. 3:2011cv06662, per RPX) — anti‑NPE conduct, not NPE conduct.
3. Repeat correspondent across the chain — not determinable. The correspondent of record is not exposed on any of the three recorded events in the sources I could reach. This signal is the one that most requires a direct Assignment Center pull; unresolved, not negative.
4. Cascading transfers — not present. Two post‑filing transfers spanning 2003→2010, both keyed to dated corporate events (JV formation 2003‑04‑01; NEC Electronics merger 2010‑04‑01). No chain of LLC hops, no shared registered‑agent address, nothing inside 24 months.
5. Pre-litigation transfer — not present. No infringement suit naming this patent was found (consistent with the earlier section's CAFC/PTAB finding of nothing). There is no 6‑month gap to measure against.
6. Bankruptcy fire‑sale — not present. No Chapter 7/11, no patent sale in proceedings. Renesas's 2012–2013 distress was resolved by a third‑party allotment to INCJ (2013‑09‑30) that changed shareholders, not by an asset sale, and produced no assignment on this record.
7. Privateering — not present. No transfer of this patent to an enforcement vehicle, and no reporting of Renesas using an NPE proxy.
8. Defensive aggregator — not present. The chain does not terminate at RPX, AST, LOT, Unified or OIN; it terminates at the original corporate family, which simply let the patent lapse in 2023.

Verdict

Insufficient data — for one reason only: I could not retrieve the Assignment Center record layer (reel/frame, execution dates, correspondent of record), so signal 3 is unverified and the timeline is built on the patent record's legal‑event dates rather than the reel/frame copies. On the evidence that is available, this is emphatically not an NPE patent: all three recorded links (2002‑10‑30 inventors → Hitachi, Ltd.; 2003‑09‑26 Hitachi, Ltd. → Renesas Technology Corp.; 2010‑09‑02 Renesas Technology Corp. → Renesas Electronics Corp., conveyance "Merger and Change of Name") are internal corporate successions within one continuing operating‑company family, there is no post‑2010 assignment, and the asset expired fee‑related in 2023 while still held by Renesas. The correct characterization for management purposes is a retained, non‑asserted operating‑company asset of Renesas Electronics Corp., with zero NPE signals present; upgrade to "not an NPE — confirmed" once the reel/frame and correspondent fields are pulled from the Assignment Center.

Verification link: https://assignmentcenter.uspto.gov/ (search patent number 7194244) — confirm reel/frame and correspondent for the 2002‑10‑30, 2003‑09‑26 and 2010‑09‑02 recordings, and confirm the absence of any further record.

Cross‑reference flags vs. the earlier sections

• The earlier «Bibliographic summary» lists "Original assignee: Renesas Technology Corp." with the chain "Hitachi, Ltd. → Renesas Technology Corp. → Renesas Electronics Corp." That is consistent with what I found — with the nuance that Hitachi, Ltd. (not Renesas Technology) was the assignee at the time of filing (2002), Renesas Technology only existing from 2003‑04‑01.
• The earlier «Search note» found no CAFC/PTAB/litigation activity for this patent; my independent searches today reached the same conclusion, so that inference stands (and is reinforced by the 2023 fee‑related lapse).
• Neither section should be read as containing reel/frame numbers: none exist in the source material supplied, and I have deliberately not invented any.

I'll start by pulling the authoritative USPTO record and the full citation list for this patent.

Let me retrieve the complete citation list from the patent record.

Let me try to retrieve the remaining entries in the reference list.

Note on sources and a metadata flag

I ran the requested USPTO-directed search for the identifier 7194244. The authoritative record I retrieved is the Google Patents mirror of the USPTO record (I could not open a live USPTO PatentCenter page in this session), and it matches the bibliography already established above — US 7,194,244 B2, application 10/253,648, priority 2001‑09‑28, granted 2007‑03‑20, Renesas. I did not return or substitute any similar-numbered patent (e.g., U.S. 6,889,244 / 8,076,194 / GB 2 401 744, which surfaced incidentally in search noise and are unrelated).

Flag: the task header says "Current Date: April 26, 2026," while the record fetch and system date are 2026‑09‑30. Immaterial to the analysis, but noted as a contradiction per your cross-reference rule.

Also flag (important, affects completeness): in the source record the "Citations (18)" list is truncated after entry 9 (JP2001036362A). I verified 9 of the 18 backwards citations by name/date/assignee. The other ~9 are only partially reconstructable from the patent's own background text. I have marked those clearly below rather than fabricating citation numbers.

A. What is and is not prior art for US 7,194,244

• § 102 prior art = the "Citations (18)" list (backwards citations) plus the non‑patent literature discussed in the specification.
• NOT § 102 prior art: the "Cited By (7)" and "Families Citing this family (22)" tables. Every one of those has a priority date of 2003 or later — after the '244 priority date (2001‑09‑28) — so they are forward citations only. Likewise the continuation US 11/702,493 (US 2007/0142012 A1) is same‑family and is not prior art.
• Every cited patent here was published well over one year before 2001‑09‑28, so all fall under 35 U.S.C. § 102(b) (pre‑AIA), with the Japanese Kokai falling under §102(b) via their 2001‑02‑09 publication.

B. Verified backwards citations — full citation, dates, description, § 102 relevance

C. References cited in the specification's background (part of the considered art)

These are named in the '244 description and are § 102(b) art, but their exact bibliographic numbers in the "Citations (18)" table are in the truncated portion I could not open. I report only what the patent text itself states:

• Kokai No. 2001‑44776 and Kokai No. 2001‑53564 — PGA arrangements with an input‑stage attenuator "in order to suppress noise and distortion." → most pertinent to claims 2–4 (noise‑suppressing PGA). Not anticipatory.
• Kokai No. 2001‑111523 — "controlling the timing at which a programmable gain amplifier by which gains are adjustable continuously starts gain control by means of calculation of received signal power." → This is the closest timing‑control art. It is distinguishable from claim 1 because (i) it is continuous rather than discrete gain, and (ii) timing is set by received‑power calculation, not by the frame structure. Not anticipatory, but the most relevant § 103 reference against the timing‑control concept.
• Kokai No. Hei‑5‑335857 — "control causing programmable gain amplifiers to decrease the gain if synchronization is not attained." → background to claim 7 (time‑measuring device synchronized to the frame + frame storage). Not anticipatory.

Non‑patent literature discussed in the specification:

• "A 22 mA 3.7 dB NF Direct Conversion Receiver for 3G WCDMA," ISSCC Digest of Technical Papers, Feb. 5–7, 2001, San Francisco, pp. 284–285. — This is the archetype of the FIG. 3 prior art: LNA → I/Q mixers → LPF → programmable gain amplifier → ADC in a direct‑conversion receiver. → most pertinent to the claim 1 preamble (first mixer downconverting once + first PGA in series after it). It does not disclose the claimed DC‑offset gain‑change noise‑reduction circuit or the frame‑structure gain‑change timing.
• M. Goldfarb et al., "Analog Baseband IC for Use in Direct Conversion W‑CDMA Receivers," 2000 IEEE Radio Frequency Integrated Circuits Symposium, pp. 79–89. → analog baseband (filter + PGA) context for claim 1; not anticipatory.

D. Overall § 102 assessment

No reference in the considered art anticipates any independent claim (1, 9, 10, 11, 12). Concretely:

• Claim 1 requires a combination — direct‑conversion mixer + discrete‑step PGA + a circuit reducing noise caused by the discrete gain change because of DC offsets + that circuit being a timing control circuit that times the change using the received signal's frame structure. The direct‑conversion architecture is shown by the ISSCC 2001 paper and by the '244 FIG. 3 discussion; the discrete‑gain PGA is shown by US 5,216,384 and the Japanese Kokai; but no single reference discloses the frame‑structure‑based gain‑change timing, and the examiner evidently agreed (the patent issued without a §102 rejection over these).
• Claim 9 is a structural claim (first‑stage PGA with switched emitter‑leg resistors joined through one capacitor; intermediate stage with parallel resistors/series switches, no emitter capacitor). US 3,153,203 / US 3,519,850 show differential‑pair capacitor coupling generally, but not the recirculated multistage discrete‑gain architecture of claim 9. Not anticipatory.
• Claims 10, 11, 12 are narrower timing variants (error‑corrected‑signal window; random timing; counter + frame store). Kokai 2001‑111523 is the only timing‑control art, and it is continuous‑gain/power‑based, so it does not read on these.
• Dependent claims 2–4 (PGA self‑suppressing noise; emitter‑coupled; collector‑coupled) are the only place where the cited differential‑amplifier patents (US 3,153,203, US 3,519,850) and the PGA‑noise Kokai (2001‑36367 / 44776 / 53564) are individually material — but even there, anticipation fails because those references disclose the amplifier feature, not that feature in the receiver of claim 1/2.

Net: the "Citations (18)" set is background art supporting the problem statement (DC‑offset step noise from discrete AGC), the direct‑conversion architecture, and the differential‑pair/PGA hardware; it is §103‑type combinable art, not §102 anticipatory art.

E. Discrepancy to verify (do not auto‑correct)

The specification text states: "Kokai No. Hei‑5‑335857 (No. 335857 of 1993) discloses control causing programmable gain amplifiers to decrease the gain if synchronization is not attained." But the citation table entry is JPH0533857A — Fuji Heavy Ind — "Hydraulic control device for continuously variable transmission" — i.e., JP H05‑033857, a different number (033857 vs 335857) and an unrelated field. These cannot both be the same document. Either the Google Patents "Definitions" panel conflated two references, or the citation table carries a mis‑mapped entry. I have not auto‑corrected the number; it should be checked against the USPTO PatentCenter face of the patent (form PTO‑892) before being relied on.

F. Caveats

• 9 of the 18 backwards citations are fully verified above; the remaining ~9 (which appear to include the Kokai 2001‑44776, 2001‑53564, 2001‑111523 and the Hei‑5‑335857/related entries) could not be enumerated with citation‑level confidence because the source's citation table was truncated. Anything beyond what is quoted in Section C is not asserted as verified.
• "Anticipation" calls above are my technical assessment against the issued claim language; they are not examiner or court holdings. The authoritative § 102/§ 103 record is the prosecution history (PTO‑892/1449 and any office actions), which should be pulled from USPTO PatentCenter to confirm exactly how each reference was applied.

I'll ground this §103 analysis in the actual prior-art references listed on the patent's Citations section and Background. Let me pull text for the key references.

Obviousness Analysis — US 7,194,244 B2 under 35 U.S.C. § 103

Building on the bibliographic, claim-summary, and litigation sections already generated. I do not repeat them. Where a fact from those sections is load-bearing here, I reference it rather than restating it.

Source of prior art used: the "Citations (18)" list and the BACKGROUND references on the patent's Google Patents record (https://patents.google.com/patent/US7194244/en), plus the applicant's own admitted prior art (FIG. 3 and FIG. 4 of the patent). I retrieved live text for US 3,153,203, US 5,216,384, US 5,768,698, and the applicant's own JP-family publication US 2003/0064696 A1. I could not retrieve full text for JPH 06244754 A, JPH 0974322 A, JP 2001-036367 A, or JP 2001-036362 A; those are treated below with explicit confidence caveats.

1. Legal framework applied

• Graham v. John Deere Co., 383 U.S. 1 (1966): scope/content of the prior art; differences between prior art and claims; PHOSITA level; secondary considerations.
• KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007): a combination is obvious where the improvement is "a predictable use of prior-art elements according to their established functions," where there is "a design need or market pressure," or where there are "a finite number of identified, predictable solutions." "A person of ordinary skill is also a person of ordinary creativity."
• In re Kahn / KSR "articulated reasoning" requirement — a motivation must be stated; the motivation need not be found in the references themselves.
• Critical date: priority date 2001-09-28 (JP 2001-300296). Every reference below predates it. The reference filing date 2002-09-25 is the §102(b)/§102(e) fallback if priority were not perfected, but I assume the JP priority is perfected, so the references are prior art under §102(a)/(b).

2. Level of ordinary skill in the art (PHOSITA)

A bachelor's degree in EE (or equivalent) plus 2–4 years of experience in RF/analog integrated-circuit receiver design, including direct-conversion (zero-IF) architectures, closed-loop AGC, and bipolar/CMOS differential-pair amplifiers. This is essentially the skill set reflected by the eight named inventors and by the two non-patent references the applicant himself cites (ISSCC 2001 and 2000 RFIC Symposium papers).

3. Claim construction of the limitations that drive the §103 result

4. Prior-art reference map

5. Claim-by-claim obviousness

5.1 Independent claim 1 — strongest §103 challenge

Claim 1 requires: (i) a direct-conversion mixer; (ii) a discrete-gain PGA in series after it; (iii) a circuit reducing DC-offset-step gain-change noise; (iv) that circuit being a timing control circuit using the received signal's frame structure.

Proposed combination — ISSCC-2001 (or Goldfarb-2000) + admitted FIG. 4 art + US 5,768,698 (+ optionally JP 2001-111523):

• ISSCC-2001 / Goldfarb-2000 supply elements (i)–(ii). The applicant himself concedes (BACKGROUND) that this is a known 3G W-CDMA direct-conversion architecture with a PGA after the mixer to fit the ADC dynamic range.
• Admitted FIG. 4 art supplies element (iii)'s problem — and the patent all but concedes that the multiple-differential-pair switched PGA is conventional and produces DC-offset-step noise on gain change ("noise is induced by step up and down by difference between DC offsets before and after the gain change").
• US 5,768,698 supplies element (iv). It discloses an AGC whose gain is renewed only at intervals longer than the sampling interval and, in the TDMA frame embodiment, once per frame unit, holding gain constant within the frame (claims 11–12), and in synchronism with a stored training sequence (claim 14). That is a "timing control circuit which controls gain change timing that uses a frame structure."

Motivation to combine (articulated):

1. AGC in a continuously-received CDMA signal must change gain during reception. As the AGC step moves through the antenna/IF/mixer/PGA chain it produces a transient; the art (FIG. 4, US 5,216,384, JP 2001-111523) recognized gain switching perturbs DC operating point/output offset. Avoiding corruption of the payload is a recognized design need → KSR "design need."
2. Scheduling time-critical gain updates on frame boundaries is a known technique for exactly this general purpose (US 5,768,698's frame-unit gain renewal; JP 2001-111523's timing control; and, in the wider art, TDMA "measure during the idle slot" AGC such as the IS-54 handoff AGC cited in the EPO search report in my results). Reusing the frame structure to time a gain transition is the established function of frame-synchronized AGC → KSR "predictable use of prior-art elements according to their established functions."
3. The direct-conversion/PGA base (ISSCC) + frame-synchronized AGC (US 5,768,698) are from the same field (radio receiver AGC), with overlapping fields of endeavor and combinable references → KSR "familiar elements, common field."

Applicant's likely rebuttal: US 5,768,698's frame is a TDMA frame and its purpose is reducing computation/fluctuation, not reducing DC-offset-step noise; and (per the patent) in TDMA the gain-change noise problem "may not be taken into consideration." That is a genuine non-obviousness argument for the purpose element — but claim 1 is not limited to CDMA ("received without intermittence" first appears in claim 5). For claim 1 as written, the TDMA frame-timed AGC teaching is fair game.

Assessment: Claim 1 is prima-facie obvious over ISSCC-2001 + FIG. 4 admitted art + US 5,768,698, with JP 2001-111523 as a secondary timing-control teaching. The residual weakness for a challenger is showing why a POSITA would repurpose a computation-saving frame-timed AGC to be a noise-avoiding frame-timed AGC; the district-court/PTAB answer is that the reason is a predictable design need once the FIG. 4 noise mechanism is known (which the applicant admitted).

5.2 Claims 2–4 — PGA-internal noise suppression

• Claim 2 ("PGA itself has a function of suppressing noise that accompanies gain change"): met by any PGA arranged so gain switching does not perturb DC offset — US 5,216,384 expressly designs its switchable stages to "minimize the effect on the stage DC offset," and JP 2001-036367/036362/044776/053564 put attenuators at the input to suppress noise/distortion. Obvious.
• Claim 3 ("emitters … connected via a capacitor"): US 3,153,203 discloses, verbatim, a condenser connected in series between the emitters of a differential pair, and explains its function (AC-couple the emitters / control degeneration / reject in-phase disturbance). This is a near-literal structural read on claim 3 combined with the FIG. 4/ISSCC base. The function (AC-short the emitter node so a switched degeneration resistor does not step the DC bias) is the same → strongly obvious, and arguably a §102 anticipation candidate for the bare structure.
• Claim 4 (collectors connected via a capacitor): adding a load-side capacitor to roll off high-frequency gain rise is a routine low-pass design choice — the patent itself says this "produce[s] the same effect that a low-pass filter is connected to the output." Obvious as a matter of predictable design.

Assessment: Claims 2–4 are the easiest to invalidate. Claim 3, in particular, is at serious §102 risk against US 3,153,203 taken alone or in trivial combination.

5.3 Claim 5 — gain change at the error-corrected, noise-robust signal

Requires CDMA/non-intermittent reception + timing control that places gain change during an error-corrected, noise-robust signal (the data field).

Combination: Claim-1 base + US 5,768,698 (frame-timed gain renewal, training-sequence sync) + the W-CDMA DPCH frame structure itself, which is a public 3GPP standard, not the applicant's invention. Once the frame (FIG. 2A: Data1, TPC, TFCI, Data2, Pilot) and the fact that turbo-coded data fields are robust while TPC/TFCI/Pilot are not are known, placing the gain transition in the data field is the predictable, finite-set choice — you either switch on the protected field, the unprotected field, randomly, or off-frame; KSR expressly covers "a finite number of identified, predictable solutions."

Motivation: A POSITA wanting to hide an AGC transient in a CDMA stream (no idle slot available) would look to the frame structure and pick the widest, most noise-tolerant region — the turbo-coded data field. This is a design choice with a predictable result.

Assessment: Obvious, but this claim carries the applicant's strongest "unexpected/teaching-away-adjacent" nuance: the TDMA references tie their frame timing to idle intervals, arguably teaching away from placing the transition inside a continuously-received payload. Still, KSR's "finite predictable solutions" and the standard's own frame definition carry the day on balance.

5.4 Claim 6 — random timing within the frame

Combination: Claim-1 base + any randomizer of the AGC strobe (the patent's own FIG. 5 is just a delay-element/switch bank selected by random numbers — a textbook implementation).

Motivation: Avoid systematic coincidence of a transient with a fixed, vulnerable symbol. Randomizing a periodic disturbance is a well-known, predictable technique. Obvious — and the claim is essentially a mere alternative to claim 5 (KSR: "if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious").

5.5 Claim 7 — frame-sync time-measuring device + frame-storage device

Combination: Claim-1 base + US 5,768,698 (which discloses renewing gain on a frame/training-sequence unit and storing/holding the gain value) + the standard cell/path search that produces the frame boundary (a W-CDMA implementation detail admitted in the patent, FIG. 1: cell & path search 108, sequencer 109, terminal counter 110).

Motivation: To time anything relative to a frame you need (i) a counter locked to the frame boundary and (ii) a stored notion of the frame layout. Both are the ordinary hardware counterpart of US 5,768,698's frame-synchronized AGC. Obvious.

5.6 Claim 8 — hysteresis on the first-stage PGA

Combination: Claim-1 base + the admitted fact that first-stage gain change produces the largest noise (because downstream stages amplify it — conceded in the specification) + the well-known AGC hysteresis / dead-band technique (a Schmitt-like threshold so the stage does not toggle around a decision boundary).

Motivation: Reducing switch frequency to reduce transient frequency is the transparent purpose of hysteresis, a standard control technique. Obvious.

5.7 Independent claim 9 — structural claim

Requires: multistage PGAs from differential pairs, with (a) the first stage using switched resistor networks on each emitter leg joined through one capacitor across the emitters, and (b) at least one intermediate stage using parallel resistors + series switches across the emitters (no emitter capacitor).

Combination:

• US 5,216,384 teaches cascading switchable discrete-gain stages while managing DC offset and transistor matching (motivation to put the switched resistor network in a controlled stage).
• US 3,153,203 teaches the capacitor across the emitters (claim 3's structure) and even teaches resistors in the emitter legs with a capacitor joining the two emitter nodes — i.e., switched-emitter-degeneration AC-coupled through one capacitor.
• Admitted FIG. 4 art teaches the switched parallel elements (switches + resistors/current sources) used to set discrete gain.

Combining a switched emitter-degeneration network (FIG. 4) with an inter-emitter AC-coupling capacitor (US 3,153,203) yields (a); using the plain switched-resistor form without the capacitor in an intermediate stage (b) is the default/fallback variant once you have decided the first and last stages need DC blocking and the middle does not (the specification says exactly this — "the intermediate programmable gain amplifier PGA2 should be configured not to include the capacitor").

Motivation: Reducing the number of external DC-blocking capacitors (a cost/board-area constraint the patent itself cites) while still suppressing offset steps is a recognized design objective; the reference combination maps element-for-element. Obvious.

5.8 Claims 10, 11, 12 — claim 1 + one added limitation each

These are claim 1 restructured with the claim-5 (10), claim-6 (11), and claim-7 (12) limitations folded in. They rise or fall with §5.3, §5.4, and §5.5 respectively, on the same combinations and motivations. Obvious to the same degree.

6. Consolidated combination table

7. Secondary considerations (Graham factor 4)

Nothing in the record I retrieved shows unexpected results, long-felt need, failure of others, copying, or industry praise attributable to these claims. The only potential nexus-bearing evidence is the applicant's own SIR-degradation modeling (FIGS. 19–27), which is a quantification of the known problem, not proof of unexpected superiority of the claimed solution. Absent such evidence, the objective-indicia factor does not rebut the §103 showing. (No litigation was found that could have surfaced objective indicia — see the litigation section.)

8. Honest weaknesses in the §103 case

1. The frame-structure-timing crux (claim 1, and claims 5/7/10/12). US 5,768,698 times gain renewal on the frame but for a TDMA system and for computation/fluctuation reduction, not for DC-offset-noise avoidance in a direct-conversion CDMA receiver. A challenger must bridge that motivational gap; the applicant can argue the TDMA art teaches away from the claimed use (the patent itself says TDMA "would disregard" the problem). This is the single most contestable element in the whole claim set.
2. Reference completeness. I did not obtain full text for JPH 06244754 A, JPH 0974322 A, JP 2001-036367 A, or JP 2001-036362 A. Any of the two Sony/Japanese PGA references could either strengthen the claims 2/9 case (input attenuators for noise suppression) or supply a more on-point frame-timing teaching. Treat the claim-1 and claim-9 conclusions as provisional pending those texts.
3. Identifier discrepancy, flagged not corrected. The specification cites "Kokai No. Hei-5-335857" while the Google citations list renders JPH0533857A. Per the operating rule I have not reconciled them; if this reference is ever relied on, the identifier must be verified against the JPO register.
4. Claim 3 is the soft spot for the patent holder. US 3,153,203's "condenser … connected in series between the emitters" is so close to claim 3 that claim 3 may be invalid on §102 alone, independent of any §103 combination.

9. Bottom line

• Claims 3 and 4 are the most exposed — claim 3 approaches anticipation by US 3,153,203, and claim 4 is a predictable low-pass variant the patent itself concedes.
• Claim 1 (and mirror claims 10–12) are prima-facie obvious over ISSCC-2001/Goldfarb-2000 + the admitted FIG. 4 PGA + US 5,768,698, with JP 2001-111523 as corroborating timing-control art; the contestable link is the motivation to repurpose a computation-saving, TDMA frame-timed AGC as a DC-offset-noise-avoiding, direct-conversion gain-change scheduler.
• Claims 5–8 and 9 are obvious over the same base plus the 3GPP DPCH frame definition, US 5,216,384 (switchable-stage PGA with offset management), and well-known hysteresis/randomization techniques.
• Because the patent is expired (adjusted expiration 2023-06-25) and no litigation was found, this analysis is best understood as an invalidity opinion / defensive prior-art mapping rather than an inter partes posture. If a formal validity challenge were mounted, I would first obtain the four missing Japanese texts and the JPO record for the H05-335857 / H05-033857 discrepancy to firm up the claim-1 and claim-9 conclusions.