US 7030004

I'll search for authoritative information on US 7,030,004, including any 2026 litigation or CAFC activity.

Let me check for any litigation or CAFC 2026 docket activity involving this specific patent.

US 7,030,004 B2 — Summary

Important caveat on scope: I verified the patent bibliographic data and text below against Google Patents, FreePatentsOnline, and the USPTO/Google-hosted patent PDF. However, I found no authoritative evidence of this patent appearing in any CAFC 2026 docket (or any litigation). My searches for litigation/docket records returned nothing responsive; I cannot confirm or deny pending 2026 activity from these tools alone. Treat the litigation statement as "not found," not as "confirmed none."

Bibliographic data

Abstract (as issued)

The invention provides a method for forming bond pad openings through a three-layer passivation structure, which protects the semiconductor device prior to bonding and packaging. Two passivation layers are formed over a semiconductor device with bond pads formed thereon. Openings are formed through the passivation layers to expose the bond pads. The openings are then filled with a photoresist material before depositing a polyimide layer over the passivation layers. Openings are formed in the polyimide layer so as to expose the filled openings. The photoresist material in the filled openings is subsequently removed to expose the bond pads.

Plain-language overview of the independent claims

The patent has 6 claims total, with two independent claims (1 and 6). Both are method claims in the "bond pad opening formation" art, and both follow the same core sequence; the difference is the number of passivation layers recited.

Claim 1 (two-layer passivation version):

1. Form a lower passivation layer over a semiconductor device that has at least one bond pad.
2. Form an upper passivation layer over the lower one.
3. Etch an opening through both passivation layers to expose the bond pad.
4. Coat photoresist over the upper passivation layer so the opening is substantially filled.
5. Strip the photoresist outside the opening, leaving photoresist only inside the opening (a "plug").
6. Deposit a polyimide layer over the upper passivation layer, covering the filled opening, until its top surface is substantially planar.
7. Form a photoresist mask on the polyimide with an opening that aligns with the filled opening.
8. Etch the polyimide through the mask opening to expose the filled opening (i.e., stop at the photoresist plug).
9. Strip the photoresist mask.
10. Remove the photoresist plug in the opening to expose the bond pad.

Claim 6 (single-layer passivation version): Identical in substance to claim 1, except it recites forming a single passivation layer (not a lower/upper pair) over the device, with the opening formed through that one layer. The rest of the sequence — photoresist plug, planarizing polyimide, aligned mask, polyimide etch to expose the plug, mask strip, plug removal — is the same.

The inventive point common to both independent claims: the opening in the passivation is temporarily plugged with photoresist before the polyimide is deposited, so the polyimide never contacts the bond pad. The plug acts as an etch stop for the polyimide etch and is then stripped away. This directly addresses the stated problem in the Background — "If residual polyimide remains in the bond pad openings, the testing process is greatly hindered."

Dependent claims

• Claim 2 — upper passivation layer comprises doped silicon nitride.
• Claim 3 — lower passivation layer comprises silicon oxide or PSG.
• Claim 4 — mask strip and plug removal are performed simultaneously.
• Claim 5 — mask strip and plug removal are performed separately (claim text reads "in separately" — a typographical artifact in the granted text; I am interpreting it literally as written).

Specification highlights (for context)

• Lower passivation: silicon oxide or PSG; upper: doped silicon nitride; both deposited by PECVD.
• Bond pad metal: aluminum or an alloy thereof.
• Sacrificial photoresist coating: thickness less than about 1000 Å.
• Polyimide: preferably 4 μm thick; example is "PIQ" from Hitachi Chemical Co., Ltd. of Japan; wet-etched with an organic etchant such as aqueous tetra methyl ammonium hydroxide.
• Figures 1–7 show the process sequence; final structure labeled a contact via 8 over the lower metal pattern 1.

Prior art cited on the face of the patent (6 references)

US 5,242,864 (Intel, 1993); US 5,960,306 (Motorola, 1999); US 6,451,681 (Motorola, 2002); US 6,660,624 (TSMC, 2003); US 6,677,226 (Motorola, 2004); US 6,873,047 (Seiko Epson, 2005).

Sources

• Google Patents: https://patents.google.com/patent/US7030004/en
• Patent PDF (USPTO/Google-hosted): https://patentimages.storage.googleapis.com/ad/c7/63/cd20e3a0e73461/US7030004.pdf
• FreePatentsOnline: https://www.freepatentsonline.com/7030004.html

Uncertainty statement

The bibliographic data, abstract, claims, and specification details above are drawn directly from the authoritative full patent text and are reliable. Two items are not established by my searches: (1) any 2026 CAFC or district-court docket involving US 7,030,004 — nothing was found, and given the patent's expired status (Sept. 24, 2024) active 2026 appellate litigation is unlikely but not affirmatively ruled out; and (2) the exact full attorney/agent-of-record data (sources differ between "Pyprus Pte Ltd" and a truncated firm name on the PDF face). I have not fabricated either.

I'll search for litigation involving US patent 7030004 across the specified sources.

Let me search more targeted litigation databases.

Let me try more specific searches for the patent on litigation databases.

Litigation Search Results: US Patent No. 7,030,004

Bottom line: I found no evidence of any litigation (district court, CAFC, or PTAB) involving US Patent No. 7,030,004 ("Method for forming bond pad openings").

I searched for the specific patent number (both 7030004 and 7,030,004) across general web and litigation-oriented sources, including the Unified Patents portal form (portal.unifiedpatents.com/litigation/caselist?...), CAFC opinion/order databases, PTAB document repositories (ptacts.uspto.gov), and general docket aggregators. No case list, docket entry, complaint, IPR/PGR petition, or CAFC appeal naming this patent surfaced.

What I was able to confirm about the patent itself

• Title: Method for forming bond pad openings
• Patent number: US 7,030,004 B2 (Application No. US 10/703,482)
• Filing/Priority date: 2003-11-10
• Grant date: 2006-04-18
• Inventor: Su Hyun Kim
• Original assignee: 1st Silicon (Malaysia) Sdn Bhd; later X-FAB Sarawak Sdn. Bhd. (change of name, effective 2006-11-02, recorded 2008-01-24)
• Status: Expired – Lifetime (adjusted expiration 2024-09-24)
• Subject matter: A semiconductor process patent (forming bond pad openings through a passivation/polyimide stack) — a manufacturing-method patent, not a consumer-facing product patent, which is consistent with there being no assertion history.

The Google Patents record shows citations by the examiner (6 U.S. references, e.g., US5242864, US5960306, US6451681, US6660624, US6677226, US6873047) but no "Litigation" or "Cases" section, and no third-party litigation citations.

Caveats and limits on my search

• I was not able to directly load the Unified Patents case-list page filtered by patent 7030004, the CAFC docket, or PACER. My external-search step limit was reached before those targeted queries could complete. So this is a negative result from the sources I could reach, not a positive verification that no case exists in PACER.
• Unified Patents' portal typically only tracks assertions of patents its members are targeted with; the absence of a listing there is weak evidence, since a Malaysian foundry process patent would be an unlikely NPE target.
• Litigation involving a patent that expired in 2024 could exist in older dockets that are not well indexed by open web search.

Recommendation for definitive verification

To confirm a true negative, the following authenticated sources should be checked directly (I could not complete queries against them):

1. Unified Patents litigation portal: https://portal.unifiedpatents.com/litigation/caselist?patents=7030004
2. PACER / CourtListener RECAP for district court complaints citing "7,030,004"
3. USPTO PTAB (Patent Trial and Appeal Board) proceeding search for the patent number
4. CAFC docket search for appeals from any underlying case

If you can run those live queries, I can analyze any hits. Based on everything I could retrieve, the most defensible current answer is that there is no known litigation involving US 7,030,004.

Proceedings overview

Zero AIA trial proceedings on file. The USPTO Open Data Portal structured record for US 7,030,004 returns 0 IPRs, 0 PGRs, and 0 CBM reviews — no active proceedings, no claims invalidated, no claims sustained in a trial, no settlements, and no institution denials, because no petition has ever been filed. The defensive posture this gives a defendant is unusual and worth stating carefully: the patent is not "hardened" by trial wins — it is simply untested at the PTAB. That is a materially different signal, and in this case the more important fact is that the patent is expired.

No proceedings to report

Because the canonical list from the USPTO ODP is empty, there is no {PROCEEDING_NUMBER} heading to populate. I am not going to invent one. What I can document is the search record behind that conclusion and the surrounding facts that bear on whether an IPR/PGR would even be available today.

Search record (negative results):

• USPTO ODP structured "PTAB proceedings on file" block supplied with this task: no AIA trial proceedings as of most recent ingest.
• Web searches for US7030004 IPR PTAB, "7030004" PTAB X-Fab bond pad openings, "US 7,030,004" IPR petition, and "IPR2015/2016/2017" "7030004" X-FAB Sarawak returned no PTAB dockets, no petition documents, and no PTAB Final Written Decisions referencing this patent. Results were limited to the Google Patents / FreePatentsOnline bibliographic pages.
• No Federal Circuit appeal exists, because there is no PTAB decision to appeal.

I could not locate any district-court assertion of this patent either, which is consistent with the absence of IPRs: the IPR bar is reactive, and this patent appears never to have been asserted.

Strategic summary

Claim status: all six claims are UNTESTED, and now unassailable by administrative route. US 7,030,004 issued 2006-04-18 with claims 1–6 (claims 1 and 6 independent; 2–5 dependent on claim 1). No claim has been canceled, narrowed, or confirmed by the PTAB, because no AIA trial was ever instituted. There is therefore no claim-level outcome to report — no FWD to cite, no canceled independent claim to hang a § 315(e)(2) argument on. If you were hoping for an invalidity estoppel shortcut, it does not exist here.

The decisive fact is expiry, not validity. Per the structured legal-status data, the patent is "Expired - Lifetime" with an adjusted expiration of 2024-09-24 (the Google Patents record carries a terminal-disclaimer-adjusted term running from the 2003-11-10 filing). Today is 2026-10-01. Whatever residual value this patent had has run out; the maintenance-fee history (4th year 2009-10-08, 8th year 2013-09-16, 12th year 2017-10-08) is consistent with a full-term patent that simply aged out. A defendant receiving a demand letter citing US 7,030,004 today should first check the term — a demand premised on an expired patent is, at minimum, a serious Rule 11 / § 285 exposure problem for the sender.

Estoppel landscape. Section 315(e)(2) estoppel is keyed to grounds a petitioner "raised or reasonably could have raised" in an instituted IPR. With no petition ever filed, no § 315(e)(2) estoppel attaches to anyone, and correspondingly there is no petitioner-privity ring to worry about. Equally, there is no beneficiary of a prior petitioner's work — you cannot piggyback on someone else's claim charts. All prior-art grounds remain theoretically available to any future challenger: the six references cited by the examiner are all fair game, as is any art not before the examiner during prosecution.

Pattern signals. Two things stand out, and both cut against any narrative of aggressive enforcement. (1) No defensive aggregator in the chain. Unified Patents and similar entities are not present in the assignment history. The chain is clean and internal: invented by Su Hyun Kim, assigned to 1st Silicon (Malaysia) Sdn Bhd (assignment effective 2003-10-31, recorded 2003-11-10), then a change of name to X-FAB SARAWAK SDN. BHD. effective 2006-11-02 and recorded 2008-01-24. X-FAB Sarawak is a functioning foundry, not a licensing vehicle. (2) No repeat-petitioner pattern — because there are no petitioners. A patent asserted against multiple defendants reliably attracts serial IPRs; this one attracted none, over a full 20-year term including the entire post-AIA era (2012–2024). That absence is the signal.

Recommended next steps

• If you are a defendant and someone asserts 7,030,004 against you today: lead with the term, not with invalidity. The structured record shows status "Expired - Lifetime," adjusted expiration 2024-09-24. A patent that expired before the accused conduct cannot support infringement. Verify the term against the USPTO PatentCenter file for US 10/703,482 and the PTA/terminal-disclaimer certificate before responding on the merits.
• If a demand letter quotes claims 1–6 as live: note that no PTAB proceeding exists, so the sender cannot claim any claim has been "confirmed" by the Board — but also that no claim has been canceled. The claims read as issued. Your first-line defense is expiry and non-infringement, not an IPR-based invalidity shortcut.
• If you nonetheless need an invalidity position (e.g., a pre-expiry damages window is asserted): you are not estopped by anything — no § 315(e)(2) bar on any ground. The examiner-cited art is a starting point, not a ceiling: US 5,242,864 (Intel, polyimide process for protecting ICs), US 5,960,306 (Motorola), US 6,451,681 (Motorola), US 6,660,624 (TSMC), US 6,677,226 (Motorola), and US 6,873,047 (Seiko Epson). Any of these, alone or in combination with art the examiner never saw, remains available in district court under §§ 102/103.
• If you are contemplating an IPR petition: recognize it is almost certainly unavailable and/or pointless. An expired patent generally cannot be the subject of a commercially meaningful IPR, and the Board's statutory one-year trial clock runs from institution — there is nothing left to protect by canceling claims in 2026.
• Do not cite a Final Written Decision — there isn't one. Any reference to an FWD, a judge panel, an institution decision, or a Federal Circuit appeal for US 7,030,004 would be fabricated. The correct and defensible statement is: no PTAB activity on file.

Note on sourcing: the negative conclusion rests on (a) the USPTO ODP structured block supplied with this task and (b) web searches that surfaced no PTAB dockets or decisions. If you have a specific litigation or demand-letter matter, the belt-and-suspenders check is a party-name search in PTAB E2E for "X-FAB Sarawak" and "1st Silicon (Malaysia)" and a PatentCenter "Patent Litigation" tab review for US 10/703,482 — but nothing I found suggests those searches will change the answer.

I'll reconstruct the assignment record from the authoritative patent text provided, then verify details (correspondents, assignee history) with targeted searches.

Let me try to surface the recorded correspondents and any litigation/assertion history.

I've hit the tool-call limit, so below is the reconstruction based on the authoritative patent text you supplied plus the assignment data and merger announcements I was able to verify. Where a field is not exposed by the sources I could access, I say so rather than guess.

Inventors

• Su Hyun Kim — sole named inventor. Employer at time of filing: 1st Silicon (Malaysia) Sdn Bhd (Kuching, Sarawak, Malaysia). This is determinable from the assignment itself: the inventor executed an assignment of rights to 1st Silicon on 2003-10-31 (effective date), and the application was filed 2003-11-10 under US App. 10/703,482. An inventor who assigns to an employer the day before filing is a standard "hired-to-invent" employee-assignment pattern.

Departure / anomaly check: No unusual pattern detectable. There is a single inventor, so "all inventors departing" is trivially one person, and the record shows no re-assignment away from the employer, no license-back, and no co-inventor drop-off. I found no evidence regarding when (or whether) Kim left 1st Silicon. Not a finding — just an absence of adverse data.

Original assignee

1st Silicon (Malaysia) Sdn Bhd — the entity named on the issued patent (US 7,030,004 B2, granted 2006-04-18).

• Line of business: Pure-play semiconductor foundry (contract wafer fabrication) in Kuching, Sarawak, Malaysia; founded 1998. Backed by the State of Sarawak. Offered logic, mixed-signal, embedded non-volatile/flash memory, HV, CMOS image sensor and CCD processes. (Sources: SemiIP Hub and EE Times merger coverage listed below.)
• Did it ship a product embodying the claims? Yes — indirectly. The patent claims a process for forming bond pad openings through a two-passivation + polyimide stack. 1st Silicon was an operating foundry; this bond-pad-opening module is a manufacturing-process step practiced in its fab, not a discrete product. The claimed method would be used in producing wafers for third-party customers.
• Current status: Operating, but not under this name. 1st Silicon merged with X-FAB Semiconductor Foundries AG; the transaction became effective 2006-09-01, and "1st Silicon will operate in the future as X-FAB Sarawak Sdn. Bhd." Today it is X-FAB Sarawak, the Malaysian 200-mm fab within the X-FAB group (Belgian holding X-FAB Silicon Foundries N.V.; XTRION N.V. ~58%, Sarawak state ~35% at the time of merger). Not dissolved and not in bankruptcy.

Assignment timeline

Two recorded events exist in the chain — the original employer assignment and a change of name. No third-party or NPE transfer has ever been recorded. Note that the sources I could access (Google Patents legal events) do not expose the recorded correspondent field; I could not retrieve it, so I do not fabricate it.

• 2003-10-31 (executed) / recorded 2003-11-10 — Reel 014688/0991

  • Conveyance: Assignment (ASSIGNMENT OF ASSIGNORS INTEREST)
  • Assignor: Kim, Su Hyun (inventor)
  • Assignee: 1st Silicon (Malaysia) Sdn Bhd
  • Correspondent: Not disclosed in the sources available to me. (Reel 014688/0991 free-format text is "ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KIM, SU HYUN" with effective date 20031031. The correspondent/filer of record is not exposed by the Google Patents legal-events feed and was not retrievable from the indexed assignment text.) Flag: cannot assess recurrence — only one link of this type in the chain.
  • Context: Standard employee/inventor-to-employer assignment of rights at filing.

• 2006-11-02 (effective) / recorded 2008-01-24 — Reel 020444/0743

  • Conveyance: Change of Name (not a transfer to a new owner)
  • Assignor: 1st Silicon (Malaysia) Sdn Bhd
  • Assignee: X-FAB Sarawak Sdn. Bhd.
  • Correspondent: Not disclosed in the sources available to me (reel 020444/0743 free-format text is "CHANGE OF NAME;ASSIGNOR:1ST SILICON (MALAYSIA) SDN. BHD." with effective date 20061102). Flag: single occurrence; no basis to allege a repeat-player filer.
  • Context: Internal corporate renaming following the completed 1st Silicon / X-FAB merger (effective 2006-09-01); the same legal entity, same fab, new name. This is why the change-of-name was recorded a full ~14 months after the merger effective date.

Post-issuance maintenance activity (no ownership effect): FPAY year 4 (2009-10-08), FPAY year 8 (2013-09-16), MAFP 12th-year maintenance fee (2017-10-08). Current legal status per Google Patents: Expired – Lifetime, adjusted expiration 2024-09-24. The patent term has run out, which independently forecloses any future assertion.

Timeline diagram

timeline
    title Ownership of US 7030004
    2003 : Application filed
         : Inventor assigns to 1st Silicon
    2006 : Patent issued
         : 1st Silicon renamed X-FAB Sarawak
    2024 : Patent expires

NPE / troll-pattern signals

1. Shell-entity transfer — not present. The only recorded instruments are the inventor→employer assignment (Reel 014688/0991, 2003) and a change of name (Reel 020444/0743, effective 2006-11-02). No "IP / Holdings / Licensing / Ventures" entity appears; the terminal owner, X-FAB Sarawak Sdn. Bhd., is a physical foundry with a Kuching fab, not a registered-agent mail drop.

2. Known asserter in the chain — not present. Neither 1st Silicon (Malaysia) Sdn Bhd nor X-FAB Sarawak Sdn. Bhd. matches any entity on the public NPE lists cited (Acacia, Marathon, IV, Wi-LAN/Conversant, Pendrell, Round Rock, etc.), nor did I surface them in RPX/Unified high-frequency-plaintiff coverage. X-FAB is a known operating analog/mixed-signal foundry (Erfurt, Plymouth, Lubbock, Kuching).

3. Repeat correspondent across the chain — unclear / not observable. Only two recorded links exist, and the correspondent field is not exposed by the sources I could access, so I cannot show recurrence. That is an evidence gap, not a negative finding — but on a two-link chain with no common filer visible, there is nothing to flag.

4. Cascading transfers — not present. Two events, ~3 years apart by execution and ~6 years apart by recording, with no chained LLCs, no shared correspondent address and no common-principal pattern. The second event is a name change, not a transfer of beneficial ownership.

5. Pre-litigation transfer — not present. No infringement litigation naming US 7,030,004 was found in the searches I was able to run. There is no suit against which the change of name could have been timed; the rename in fact predates any conceivable assertion by over a decade.

6. Bankruptcy fire-sale — not present. 1st Silicon was described as "struggling" in contemporary trade press, but the 2006 transaction was a stock-swap merger with X-FAB (XTRION N.V. and the Sarawak State Financial Secretary as the major shareholders), not a Chapter 7/11 liquidation or a court-supervised patent sale. There is no Kodak/Nortel-style auction here.

7. Privateering — not present. No evidence in SEC-type disclosures, Patent Progress or EFF-style coverage that X-FAB transferred this patent to an NPE to assert against competitors. The patent remains with the operating fab.

8. Defensive aggregator (anti-NPE) — not present. The chain does not terminate at RPX, AST, LOT Network, Unified Patents or OIN. So the "neutralized by aggregator" inverse signal does not apply either.

Verdict

Insufficient data. The ownership chain contains no NPE or assertion activity to classify: it consists solely of the inventor-to-employer assignment (Reel 014688/0991, executed 2003-10-31, recorded 2003-11-10) plus a same-entity change of name (Reel 020444/0743, effective 2006-11-02, recorded 2008-01-24) resulting from the 1st Silicon / X-FAB merger. The terminal owner, X-FAB Sarawak Sdn. Bhd., is an operating semiconductor foundry — not a licensing shell — and no third-party, NPE, litigation, or fire-sale event appears anywhere in the record.

Both the Kuching fab's operation and the patent's Expired – Lifetime status (adjusted expiration 2024-09-24) independently confirm this is not an assertion vehicle. I deliberately stopped at "Insufficient data" rather than "Operating-company assertion" because the verdict category requires the current assignee to be suing actual competitors, which is not the case here.

Caveats: (i) The recorded correspondent for both reel/frame entries could not be retrieved from the sources available to me, so signal #3 is unassessable rather than negative — that is the single biggest evidence gap in this analysis. (ii) No litigation search was exhaustive; I found no suit, but absence in the searches I ran is not proof none exists.

Verify at: https://assignmentcenter.uspto.gov/ (search patent number 7030004; also indexed at https://assignment.uspto.gov/patent/index.html) — pull Reels 014688/0991 and 020444/0743 directly to obtain the correspondent-of-record fields.

I'll verify the patent details and investigate each cited prior-art reference.

Let me investigate the remaining cited references.

Prior-Art Analysis — US 7,030,004 B2

1. Patent identification (literal, as retrieved)

Source: https://patents.google.com/patent/US7030004/en and the granted-PDF front page https://patentimages.storage.googleapis.com/ad/c7/63/cd20e3a0e73461/US7030004.pdf

Scope of the claims (the anticipation target):

• Claim 1 (independent): lower passivation → upper passivation → open both to expose bond pad → coat photoresist and substantially fill the opening → strip photoresist outside the opening → deposit polyimide covering the filled opening until planar → photoresist mask over polyimide with aligned opening → etch polyimide to expose the filled opening → strip mask → remove photoresist from the opening to expose the pad.
• Claim 6 (independent): identical sequence, but the opening is through a single passivation layer.
• Claims 2, 3: upper layer = doped silicon nitride; lower layer = silicon oxide or PSG.
• Claims 4, 5: strip of mask and plug "simultaneously" / "in separately" [sic].

The heart of the invention is the ordering/inversion: the bond-pad opening is made through the passivation first, plugged with sacrificial photoresist, and only then is the polyimide deposited and opened. The patent's own stated problem is that "if residual polyimide remains in the bond pad openings, the testing process is greatly hindered."

2. The six examiner-cited references ("Patent Citations (6)")

The authoritative citation table from the patent record:

Reference-by-reference analysis

① US 5,242,864 A — Intel, "Polyimide process for protecting integrated circuits" (1993-09-07)
Full text verified at https://patents.google.com/patent/US5242864 and https://www.freepatentsonline.com/[5242864](/patent/5242864).html

• Disclosure: A bonding pad 22 on a substrate, a silicon nitride insulating layer 21 over the pad, polyamic acid 25 deposited over the nitride, a two-step cure (≈90 °C then ≈145 °C) to lower its etch rate, photoresist 27 deposited and developed to define an opening 29. The developer (TMAH-based, "NSDTD-2X") permeates the polyamic acid beneath the opening to form a salt region 30; a subsequent hard bake selectively imidizes the surrounding regions 31 into polyimide. Photoresist and the salt region are removed, leaving polyimide; then "etching the insulative layer in alignment with the openings exposes the bonding pads."
• Potential §102 relevance: Discloses a polyimide protective overcoat over a nitride passivation layer, and formation of a pad-revealing opening in the insulative layer aligned to a polyimide opening (elements (a)/(b) partly, (f) polyimide-over-passivation, (g)–(h) conceptually). It teaches the inverse order — the passivation opening is etched last, not first, and there is no sacrificial photoresist plug filling a pre-formed opening, and no patterned photoresist-based etching of the polyimide (the polyimide is defined by selective imidization/salt removal, not by etching through a mask opening).
• Anticipation conclusion: Does not anticipate claim 1 or claim 6 — element (c) before (f), and every element of the fill-plug sequence (d)(e)(j), are absent. It is relevant background for claims 2 (nitride) and the general polyimide-over-passivation architecture, and is a plausible §103 combination reference.

② US 5,960,306 A — Motorola (Hall et al.), "Process for forming a semiconductor device" (1999-09-28)

• Disclosure (as far as verified): Cited by the examiner and classified in the same bond-pad-opening art (USPC 438/612, per the printed front page of US 7,030,004: "5,960,306 A * 9/1999 Hall et al. 438/612"). I was not able to retrieve the full specification text in my searches, so I cannot quote its disclosure with confidence.
• Honest statement: I do not know with high confidence the specific process steps of US 5,960,306. Based only on its title and its classification in the same subclass as the '004 patent, it is a process-flow reference for semiconductor (likely bond-pad/passivation) formation, but I will not fabricate a claim-by-claim mapping. It should be pulled and read in full before any anticipation assertion is made.

③ US 6,451,681 B1 — Motorola (Greer), "Method of forming copper interconnection utilizing aluminum capping film" (2002-09-17)
Full text verified at https://idiyas.com/patent/badge/[6451681](/patent/6451681) and via the description of it in EP 1 842 233 B1 (https://patents.google.com/patent/EP1842233B1/en): "US6451681 discloses a transitional metallurgy structure covering an exposed portion of a bond pad. After forming the transitional metallurgy structure, a passivation layer is formed overlying the transitional metallurgy structure. The passivation layer is then lithographically patterned and etched to form an opening that exposes portions of the transitional metallurgy structure. An optional polyimide (die coat) layer is then formed over the passivation layer. The polyimide layer is lithographically patterned and then etched (or developed) to form a die coat opening that exposes the opening defined in the passivation layer…"

• Potential §102 relevance: Discloses the same layer stack and geometry recited in claim 1: bond pad → passivation → opening through passivation exposing the pad region → polyimide over the passivation → polyimide opening patterned/etched to expose the passivation opening. Elements (a)–(c), (f)–(h) are approximated.
• Missing elements: No photoresist coating that substantially fills the passivation opening (d), no stripping outside the opening to leave a plug (e), and no subsequent removal of a plug to expose the pad (j). The passivation opening here is made before polyimide deposition but left open/empty, which is precisely the situation the '004 patent seeks to avoid.
• Anticipation conclusion: Does not anticipate claim 1 or 6. It is the strongest reference for the layer stack and would be a natural §103 combination candidate if another reference supplied the photoresist-plug step.

④ US 6,660,624 B2 — TSMC (Tzeng et al.), "Method for reducing fluorine induced defects on a bonding pad surface" (2003-12-09)
Full text verified at https://patents.google.com/patent/[US6660624B2](/patent/US6660624B2)/en

• Disclosure: Addresses fluorine contamination produced by plasma etching during formation of the passivation-layer opening over a bonding pad; the process involves a passivation layer (claim 46 refers to "passivation layer"), a polyimide, plasma etching, and a heating/soaking step to drive off fluorine so residual contamination does not degrade the bond-pad surface.
• Potential §102 relevance: Uses the same field (pad-opening etch through passivation with polyimide present) and shares elements (a)–(c) (passivation opening over a pad) and the presence of polyimide (f). It says nothing about filling the opening with photoresist, planarizing polyimide over a plug, or stripping a plug to expose the pad.
• Anticipation conclusion: Does not anticipate any of claims 1–6. Its only realistic role is as a secondary §103 reference on the "residue in the pad opening" problem, which is the same technical problem the '004 patent recites.

⑤ US 6,677,226 B1 — Motorola (Bowen et al.), "Method for forming an integrated circuit having a bonding pad and a fuse" (2004-01-13)

• Disclosure (from title/art): Directed to forming, on an integrated circuit, a bonding pad and a fuse (the fuse typically formed from a metal layer, with an opening in overlying dielectric/passivation so the fuse can be blown).
• Potential §102 relevance: Shares with claim 1 the generic steps of forming a conductive pad, passivation over the pad, and an opening through the passivation to expose the pad, and possibly a polyimide/overcoat. It is not directed to the sacrificial-photoresist-plug bond-pad-opening method.
• Anticipation conclusion: Does not anticipate claims 1–6. I did not retrieve the full specification; my description above rests on the title/classification and should be confirmed against the full text before relying on it. It is at most a background reference on passivation-opening formation.

⑥ US 6,873,047 B2 — Seiko Epson (Wada et al.), "Semiconductor device and manufacturing method thereof" (2005-03-29; filed 2003-02-28)

• Disclosure (from title/art): A semiconductor-device manufacturing method in the bump/electrode-formation field, using a resin (typically polyimide) layer as a mask/insulator over passivation with openings down to electrode pads, then forming conductive bumps.
• Date relevance: Its US filing date (2003-02-28) precedes the '004 filing date (2003-11-10), so despite issuing later (2005-03-29) it is a potential §102(e) reference (pre-AIA); it is not §102(a)/(b) art on its publication date.
• Anticipation conclusion: The claimed subject matter (bump/electrode formation with a resin mask) is different from the '004 fill-plug sequence; it does not disclose elements (d), (e) or (j). Does not anticipate claims 1–6. (I did not retrieve its full text; my characterization rests on the title and field and should be verified.)

3. § 102 determination summary

Important caveat: the '004 patent was filed 2003-11-10, i.e., under pre-AIA 35 U.S.C. §§ 102(a)/(b)/(e). Applying those provisions to the six examiner-cited references:

Bottom line: On the record I retrieved, none of the six examiner-cited references individually anticipates claim 1 or claim 6, because none discloses the two-step that defines the invention: (i) coating photoresist to substantially fill the already-formed passivation opening and stripping it outside the opening to leave a plug, and (ii) later removing that plug to expose the bond pad. US 5,242,864 teaches the reverse order (polyimide defined first, passivation etched last), and US 6,451,681 teaches polyimide-over-passivation openings that are left empty.

The realistic invalidity theories would be § 103 combinations, e.g., US 6,451,681 (layer stack + polyimide die-coat opening) with a plug-forming/sacrificial-layer reference (note that the examiner's own search class had pending-art such as US 5,158,910 "sacrificial plug" and US 6,024,026 / US 5,272,973 sacrificial-material metallization processes cited in the family), rather than pure anticipation. Note also that the record lists "Similar Documents" such as US 5,731,243 ("Method of cleaning residue on a semiconductor wafer bonding pad," 1998-03-24) and US 6,878,642 ("Method to improve passivation openings by reflow of photoresist to eliminate tape residue," 2005-04-12), which address the same residue-in-the-pad-opening problem and may be worth checking as secondary art — though they were not among the six "Patent Citations."

4. Caveats

• The only fully verified texts in this analysis are US 7,030,004, US 5,242,864, US 6,660,624, and the description of US 6,451,681 (as quoted in EP 1 842 233 B1). I was unable to retrieve the full specifications of US 5,960,306, US 6,677,226, and US 6,873,047 within my search budget; statements about those three are based on title, assignee, dates and classification and are flagged as unverified. Do not treat them as confirmed disclosures.
• I did not locate an express USPTO Office Action in which the examiner characterized these references against the claims, so the §102 mappings above are my own element-by-element analysis, not the examiner's.
• The literal patent number is 7,030,004; I did not substitute any similar number (e.g., 7,030,004 is distinct from the "Similar Documents" and from the cited references), per the instruction to interpret identifiers literally.
• This is a technical prior-art analysis, not a legal opinion or a validity/FTO conclusion.

I'll research the prior-art references cited on this patent page to ground the obviousness analysis, then build combinations.

Obviousness Analysis — US 7,030,004 B2 under 35 U.S.C. § 103

Scope note: This builds on the earlier litigation section; I do not repeat the patent's bibliographic data here. Everything below is keyed to the claim text and the "Patent Citations (6)" / "Similar Documents" lists shown on the Google Patents page (https://patents.google.com/patent/US7030004/en). Where I could not fully retrieve a reference's disclosure, I say so rather than assume it.

1. Governing law and framing

US 7,030,004 was filed 2003-11-10 with no earlier priority claim, so pre-AIA §§ 102/103 govern (the AIA "first-inventor-to-file" provisions do not apply). Obviousness is assessed under the Graham v. John Deere framework — scope/content of the prior art, differences between the prior art and the claims, PHOSITA level, and secondary considerations — as refined by KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007): a combination is obvious if a PHOSITA would have had a reason to combine with a reasonable expectation of success, including combining "known elements according to known methods to yield predictable results."

Level of ordinary skill (assumed): a B.S. in materials/electrical/chemical engineering or equivalent, with 2–4 years of semiconductor back-end/wafer-fab process experience, familiar with PECVD passivation (oxide/nitride/PSG), polyimide protective overcoats, and standard photolithographic wet/dry patterning. The specification itself sets this tone (e.g., "a conventional etching technique," "a conventional developing solvent," "a conventional organic etchant").

2. The claim limitations that matter

Claim 1 is a ~10-step process. Reduced to its distinct technical content, the elements are:

Claims 2–5 are material/process variants (upper = doped silicon nitride; lower = silicon oxide or PSG; strip mask and plug simultaneously, or in separate steps). Claim 6 is a broader species of claim 1 with a single passivation layer (steps A–B collapsed into one), i.e., it recites no SRO/nitride sub-layers.

The single point of novelty is the use of a sacrificial photoresist "plug" (lift-off mandrel) to protect/define the bond-pad opening before polyimide deposition, so that the polyimide is wet-etched back to the plug and the plug — not the polyimide — is the last thing removed from the pad. Everything else (passivation stack, polyimide overcoat, photoresist masking, etching, stripping) is a textbook back-end sequence.

3. The prior art of record and its teaching gaps

References cited by the examiner (all § 102(b)/(e)-eligible):

US 5,242,864 A — Intel, "Polyimide process for protecting integrated circuits" (1993-09-07). Fully reviewed. Discloses a polyimide layer deposited over an insulative (passivation) layer that covers bonding pads, a photoresist layer deposited over the polyimide, developing to define openings, selective imidization, removal of the photoresist, removal of the salt regions, and then etching the insulative layer "in alignment with the openings [to expose] the bonding pads." Critically, it expressly frames the same problem the '004 patent frames: prior art processes leave "pieces of photoresist … deposited on the surface of the bonding pads" and produce "spikes of unetched passivation layer … left behind on the bonding pad," and require "consistent polyimide edge profiles which are relatively defect-free." (https://patents.google.com/patent/US5242864 ; https://www.freepatentsonline.com/[5242864](/patent/5242864).html)
Gap: Intel removes the resist/salt before or as part of defining the polyimide and does not deposit a sacrificial resist plug that survives under the polyimide.

US 5,960,306 A — Motorola, "Process for forming a semiconductor device" (1999-09-28). Fully reviewed. This is the closest single art to the problem the '004 patent addresses. It concerns forming openings within passivation layers, and is expressly directed to "bond pad staining, particularly when a polyimide die coat layer (72) is subsequently formed over the semiconductor device." Its figures show a passivation layer with a patterned resist (FIG. 4), a bond pad opening formed through the passivation layer (FIG. 5–6), then coating a layer including polyamic acid over the device (FIG. 7), developing it (FIG. 8), and curing the polyamic acid to form a polyimide die coat (FIG. 9). (https://patentimages.storage.googleapis.com/4f/02/dd/7c1375b2e53d24/US5960306.pdf ; equivalent EP 0779654 A3.)
Gap: Motorola's solution is an RF-power etch recipe (low-power step when the pad is first exposed, then high power), not a sacrificial plug. It forms the polyimide over the already-formed opening and does not teach filling the opening first.

US 6,667,226 B1 — Motorola (2004-01-13); US 6,451,681 B1 — Motorola (2002-09-17); US 6,660,624 B2 — TSMC (2003-12-09); US 6,873,047 B2 — Seiko Epson (2005-03-29). These are of-record but peripheral to the plug concept: US 6,660,624 is a bonding-pad-surface defect treatment (its keyword set — passivation layer / bonding pad / polyimide / fluorine / heating — shows it works on a polyimide-over-passivation pad stack); US 6,873,047 is a semiconductor-device manufacturing method from a different (Epson) context. I could not fully retrieve the full text of US 6,667,226 and US 6,451,681 within my search budget, so I do not rely on them as teaching the plug step; I flag that a complete file history/claim chart would need their full text.

"Similar Documents" (listed on the page — a filter/boost for the surrounding art, not necessarily of record):

US 6,878,642 B1 — "Method to improve passivation openings by reflow of photoresist to eliminate tape residue" (2005-04-12). Fully reviewed. Discloses the exact stack-and-sequence skeleton of the '004 claims minus the plug: passivation layer over metal 64 → organic photoresist 72 deposited over the passivation → pattern the resist → etch the passivation layer through to form the bonding-pad opening → strip the photoresist. It also confirms the field's awareness that residue in/near the bond-pad opening (adhesive, resist-derived polymer) destroys wire-bond yield, and that sloping/clean opening profiles are the goal. (https://patents.google.com/patent/US6878642.)

US 5,731,243 A — "Method of cleaning residue on a semiconductor wafer bonding pad" (1998-03-24) and US 6,924,172 B2 — "Method of forming a bond pad" (2005-08-02) reinforce that the residue/clean-pad problem in passivation openings was a well-developed art by the 2003 priority date. (I did not fully retrieve US 6,924,172; treat it as corroborating context only.)

The undisputed common knowledge: sacrificial-mandrel / lift-off processing — filling or covering a feature with a removable material, depositing a permanent layer over it, then removing the mandrel to define the permanent layer's opening — was a decades-old, ubiquitous semiconductor technique by 2003. The '004 specification itself calls the resist a "sacrificial photoresist coating," confirming the technique was conventional nomenclature.

4. Proposed obviousness combinations

Combination A (primary): US 5,960,306 + US 5,242,864 + US 6,878,642 → renders claim 1 obvious

Mapping:

• A/B (two-layer passivation): US 5,960,306's FIG. 1–4 shows a deposited insulating/oxide layer (10) with subsequently deposited passivation over an aluminum-containing pad (22); US 6,878,642 discloses nitride passivation (and the art generally pairs oxide/PSG + doped silicon nitride). See § 5 for claims 2–3.
• C (opening through the stack): US 5,960,306 FIGS. 5–6 and US 6,878,642 FIG. 8 each form the bond-pad opening through the passivation.
• D/E (resist fills opening; strip outside to leave a plug): This is the only element not squarely shown in one reference. It follows from applying standard lift-off/mandrel practice to the US 6,878,642/US 5,960,306 resist-patterning step: a PHOSITA patterning resist in a step that must cover an opening would either clear it or leave it filled depending on exposure polarity; the specification's own claim language ("strip the photoresist material outside of the opening leaving only the photoresist material in the opening") is the direct complement of the ordinary develop step and uses no non-conventional materials. Under KSR, using a known masking material as a temporary mandrel in a known opening is a predictable variation.
• F (polyimide until planar): US 5,960,306 FIGS. 7–9 (polyamic acid → cured polyimide die coat) and US 5,242,864 (polyimide overcoat over passivation) both teach depositing the polyimide overcoat over the passivated device; the "substantially planar" limitation is an inherent/desired property of spin-coated polyimide and is not argued in the specification as critical.
• G–I (resist mask over polyimide; etch; strip): US 5,242,864 teaches photoresist-over-polyimide, developing openings, and removing resist; US 6,878,642 teaches strip-and-etch of the same stack. The '004 patent's wet TMAH etch of polyimide is a conventional organic etchant by its own admission.
• J (remove plug to expose pad): this is the concluding strip step, conventional and expressly disclosed in US 5,242,864/US 6,878,642.

Motivation to combine (the KSR "articulated reason"):

1. All references are in the same field (back-end semiconductor passivation/polyimide overcoats) and address the same problem — protecting the device while keeping the bond-pad opening clean. US 5,960,306 states verbatim that its aim is reducing bond-pad staining "particularly when a polyimide die coat layer is subsequently formed," and US 5,242,864 warns of "pieces of photoresist … on the bonding pads" and passivation spikes.
2. The '004 specification's stated problem — "If residual polyimide remains in the bond pad openings, the testing process is greatly hindered" — is the same defect these references identify (residue/polymer/stain in the opening hurting probing and wire bonding). A PHOSITA seeking to eliminate polyimide residue in the opening would predictably choose to keep the pad covered by a removable material until the polyimide is fully patterned, which is exactly the plug step.
3. Combining known resist-masking (US 6,878,642/US 5,242,864) with known polyimide-overcoat deposition (US 5,960,306) is "arranging old elements with each performing the same function" → predictable result (KSR).

Reasonable expectation of success: high — every individual step (spin resist, image, develop, spin polyimide, wet etch, strip) is routine and the references each demonstrate their sub-sequences working on the same class of device.

Combination B (alternative): US 5,242,864 + US 5,960,306 (two-reference) → claim 1 obvious

Intel alone supplies the polyimide-over-passivation-with-bond-pad-opening architecture and the photoresist patterning + removal teaching; Motorola supplies the "form the passivation opening first, then lay down the polyimide die coat" ordering. Combining only these two yields all of claim 1 except the explicit plug-fill, which is supplied by ordinary lift-off knowledge (and by reading the claimed "strip outside / leave inside" as the routine complement of developing a resist that had covered the opening). This is a tighter but slightly more vulnerable combination because the plug step must be imported from common knowledge rather than a third reference.

Combination C (for the broader claim 6): add US 6,878,642 → claim 6 obvious

Claim 6 drops the lower/upper split and recites a single passivation layer. This removes the only structural distinction between the '004 process and US 6,878,642's single-passivation + resist + etch + strip flow. With US 6,878,642 (single passivation, resist over it, etch passivation, strip resist) plus the polyimide-deposition teaching of US 5,960,306/US 5,242,864, claim 6 is the weakest claim and the most exposed to a § 103 challenge.

5. Dependent claims

• Claim 2 (upper layer = doped silicon nitride) and Claim 3 (lower = silicon oxide or PSG). These are the default passivation materials of the era. US 6,878,642 expressly discloses silicon-nitride passivation (LPCVD/plasma-assisted, 3,000–15,000 Å); US 5,960,306 discloses oxide (doped/undoped) insulating layers over the aluminum pad. Selecting nitride for hermeticity and oxide/PSG for stress/compatibility is a routine design choice with predictable results → obvious. No unexpected result for these materials is attributed anywhere in the specification.
• Claim 4 (simultaneous strip) and Claim 5 (separate strip). The specification itself states the two resists "may be stripped simultaneously or in separate steps using a conventional photoresist stripper." Claims 4 and 5 therefore recite both known alternatives in the alternative, which is classic "obvious to try"/obvious-variation territory — a mere choice of process sequencing with no asserted criticality. Highly vulnerable.
• Claim 6. Discussed above — broadest, and obvious over US 6,878,642 + US 5,960,306/US 5,242,864.

6. Counter-arguments a patent owner would raise (and my assessment)

1. No single reference teaches "fill the passivation opening with resist before depositing polyimide." True as a literal matter — US 5,960,306 etches the opening and lays polyimide over it; Intel removes resist/resist-salt before the final pad exposure. The obviousness case therefore depends on the plug step being obvious in view of lift-off/mandrel knowledge combined with the references' shared anti-residue motivation. This is the strongest defense in the case, but KSR cuts against it because the plug is a known technique applied to a known problem.
2. Teaching away / added cost. A patent owner could argue extra process steps (deposit plug, extra strip) counsel against the combination and that the references solve the residue problem by other means (RF power in US 5,960,306; sloped profiles in US 6,878,642; selective imidization in US 5,242,864). Assessment: these are alternative solutions to the same problem, not teachings away from using a sacrificial layer; alternative approaches in the art generally support (not defeat) obviousness of another predictable option absent a critical teaching.
3. Secondary considerations. The specification asserts no unexpected results, no commercial success data, no long-felt-need/long-felt failure narrative, and no copying/licensing evidence. On the present record there is nothing to rebut a prima facie § 103 case. (The patent has been Expired – Lifetime since its 2024 adjusted expiration, so there is also no ongoing commercial nexus to develop.)
4. Hindsight caution. A rigorous case would test whether the specific plug-fill step was actually practiced in the art before 2003-11-10. I have not definitively identified a pre-2003 reference that literally fills a passivation bond-pad opening with resist before polyimide deposition; that would be the decisive art. I mark this as the one factual gap in the analysis.

7. Bottom line

• Claim 1 is reasonably likely obvious over US 5,960,306 + US 5,242,864 + US 6,878,642 (Combination A), or over a two-reference combination plus the conventional lift-off/mandrel technique (Combination B). The motivation is strong and documented: all three references are in the same field and target the identical defect (residue/stain in the bond-pad opening, especially with a polyimide die coat). The only element not literally shown is the sacrificial-plug fill, and that is a known, predictable technique used to produce predictable results — the KSR paradigm.
• Claim 6 (single passivation) is the weakest claim and most clearly obvious over US 6,878,642 + US 5,960,306/US 5,242,864.
• Claims 2–5 are strongly obvious: conventional materials and a mere choice of stripping order, both admitted as conventional in the specification itself.
• Principal uncertainty: the definitive § 103 case turns on whether the specific "resist-filled bond-pad opening before polyimide deposition" step is shown or fairly suggested in the art; I could not fully retrieve US 6,667,226 and US 6,451,681 (of record) or US 6,924,172 (similar document), and a complete claim chart should verify those. KR 100286291 B1 — "Bonding pad formation method of two-layer structure device" (listed under Similar Documents) is a two-layer passivation bond-pad-opening reference that should be examined closely for the plug step before finalizing the invalidity position.

Caveat on sources: I relied on the Google Patents page and full text for US 5,242,864, US 5,960,306, and US 6,878,642; I did not obtain full text for US 6,667,226, US 6,451,681, US 6,873,047, US 5,731,243, US 6,924,172, or KR 100286291, and I do not assert their contents beyond what is stated above.