US 6965175

I'll verify current information on this patent via search, then summarize.

Verification note up front

I ran targeted searches on the exact string 6965175 / US6965175 rather than a family search. Results resolve to a single patent — US 6,965,175 B2 — and I did not find any CAFC (or district court) docket, 2026 or otherwise, naming this patent. The closest Quanta CAFC hit is LaserDynamics, Inc. v. Quanta Computer, Inc., 694 F.3d 51 (Fed. Cir. 2012), which concerns optical-disc discrimination patents, not 6,965,175 — I am flagging this so it is not misread as a hit. I also did not have direct authenticated access to USPTO PatentCenter/PTAB or CAFC docket systems; findings below rest on the Google Patents/FPO/Justia text of the patent itself plus open web results. Treat litigation/docket status as unverified rather than affirmatively "no litigation."

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Bibliographic data (US 6,965,175 B2)

Assignment recorded 2002-09-16 (reel/frame 013308/0121), effective 2002-08-28, assignors Hu and Wei to Quanta Computer Inc.

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Abstract (as issued)

"A dynamic temperature control method for a computer. The present invention monitors the power consumption and temperature of a microprocessor to set the rotation speed of a fan module at an appropriate speed such that noise generated and overheating are reduced."

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Independent claim 1 — plain language

A method for a computer system having at least a CPU, a microcontroller, and a fan module:

1. Monitor via the microcontroller to obtain a clock throttling-ratio status, a temperature parameter value, and a power parameter value.
2. Compare: temperature value vs. predetermined temperature initial / maximum / minimum values; power value vs. predetermined power initial value and a power setup value — yielding a temperature variation rate and a power variation rate.
3. Rough-tune the fan's operating power (per a predetermined maximum temperature variation rate and a rough-tuning setup value) when temperature is between the max and min values and power ≥ the power setup value.
4. Fine-tune the fan's operating power (per a predetermined maximum power variation rate and a fine-tuning setup value) when the temperature variation rate is ≤ the maximum temperature variation rate.
5. Reduce fan operating power by the fine-tuning setup value when the power variation rate > the maximum power variation rate and the power parameter value is below the power initial value.
6. Store the current temperature and power parameter values as the new initial values (so the next cycle compares against the just-measured baseline).

Net effect: a dual-loop scheme — coarse (large-step) fan control driven mainly by CPU temperature, fine (small-step) fan control driven mainly by CPU power consumption — with hysteresis maintained by rolling the previous sample into the "initial" values.

Independent claim 10 — plain language

Similar architecture but drafted more broadly around a microprocessor, microcontroller, and heat-dissipation module (not limited to a fan), and it drops the "clock throttling-ratio status" from the monitoring step:

1. Monitor to obtain a temperature parameter value and a power parameter value.
2. Compare against predetermined temperature initial/max/min values and power initial/power-setup values to derive a temperature variation rate and a power variation rate.
3. Rough-tune the heat-dissipation module per a rough-tuning setup value when temperature is between max and min, power ≥ power setup value, and the temperature variation rate > a predetermined maximum temperature variation rate.
4. If the temperature parameter value is below the temperature initial value, decrease operating power by the rough-tuning setup value.
5. Save the temperature and power values as the new initial values.

Claim 10 thus claims the "temperature-rising → step up / temperature-falling → step down" coarse control as its core, with fine-tuning recited only in dependent claim 12.

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Notable literal drafting points (per the "interpret identifiers literally" rule)

• Claim 1 recites "a computer system which has at least a CPU" but then says "monitoring the microprocessor"; the specification equates the two ("The microprocessor can be a CPU"), so this is a terminology inconsistency in the claim, not a different element.
• Claim 15 recites "reducing a clock throttling-ratio of the microcontroller," whereas the specification's Step 400 and claim 5 reduce the throttling ratio of the microprocessor. Read literally as written; likely a drafting error in the patent, but I will not auto-correct it.
• The specification contains the typo "clock throttling-ration status" and spells out numeric examples (temp max 95 °C, min 50 °C, initial 70 °C; 100 °C and 40 °C trigger cases; rough-tune 10% or 20%; fine-tune 1% or 5%).

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Context and prior art (grounding)

• Cited prior art (10 references) includes: US 5,929,581 (HP, proportional-integral fan controller); US 6,415,388 (Intel, power throttling via closed-loop feedback); US 6,349,269 (Dell, thermal management data prediction); US 6,510,400 (NEC, CPU temperature control circuit); US 6,735,499 (IBM, controlling cooling fan); and TW 424,174.
• The specification distinguishes Taiwan Patent No. 292,766, which activates a fan/cooler only above a threshold and ramps power continuously to full — criticized as unable to cool "in time" and as generating noise. The asserted improvement is using CPU consumed power as a control parameter alongside temperature.
• Forward citations of note: Wistron US 7,617,020 B2 ("Method for controlling system to work at appropriate temperature"), Dell US 7,987,024 B2 ("Fan speed control"), and Microchip US 10,394,294 B2 ("Predictive thermal control management using temperature and power sensors") — i.e., the temperature+power sensor-control concept persisted in later art.
• A Chinese family member appears in the similar-documents list as CN 1312578 C, "Dynamic Temperature Control Method of Computer System."

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Uncertainty / limitations

• No CAFC 2026 docket for 6,965,175 located. Given the patent expired (adjusted expiration 2023-06-09) and the last recorded maintenance fee was the 12-year payment (2017-02-21), active 2026 appellate litigation would be unusual, but I cannot rule it out — my searches did not hit a live USPTO docket interface. If a docket number exists, please supply it and I can target that exact number.
• No prosecution-history or PTAB record retrieved. I have the issued text and citations, not the examiner's rejections, office actions, or any IPR/PGR.
• I did not independently confirm current chain of title beyond the single recorded 2002 assignment to Quanta Computer Inc.

I'll research litigation involving US patent 6965175.

Let me search more specific litigation databases.

Let me check specific litigation databases directly.

Litigation Search Report — U.S. Patent No. 6,965,175

Patent identified (literal): U.S. Patent No. 6,965,175 B2 — "Dynamic temperature control method for a computer system"

• Application No. 10/244,887; filed 2002‑09‑16; priority TW 91113060 (2002‑06‑14); granted 2005‑11‑15
• Original/current assignee: Quanta Computer Inc. (Taiwan); inventors Ming‑Chuan Hu and Hung‑Hsun Wei
• Status: Expired – Lifetime (adjusted expiration 2023‑06‑09)
• Published as US 2003/0230939 A1

Findings

No litigation involving U.S. Patent No. 6,965,175 was identified in any of the sources searched.

Searches conducted for the exact identifier (in both 6965175 and 6,965,175 formats) across patent‑litigation aggregators, docket databases, and general web sources returned:

1. No district court complaints naming the '175 patent as a patent‑in‑suit (no hits on CourtListener/RECAP, Justia Dockets, or Docket Alarm style sources).
2. No CAFC appeals involving the '175 patent.
3. No PTAB proceedings (IPR/PGR/CBM) challenging the '175 patent — the Google Patents page for the '175 patent shows no "Cited By" PTAB entries and no post‑grant challenge history; it shows only a "Cited By" list of later patents that cite it as prior art, plus a prosecution‑time citation list.
4. No NPE assertion activity. Quanta Computer is a manufacturer, not a monetization entity, and the patent expired in 2023.
5. No Unified Patents "NPE Docket," RPX Insight, or Docket Navigator entry linked to this patent number.

Note: Search returns included several unrelated matches for the bare numeric string (Lithuanian corporate register entry No. 6965175, a Brazilian JUCEG registry item, a Chilean procurement record 6965175, an Indian trademark hearing number 6965175). Per the strict‑interpretation rule, these are not the U.S. patent and are not litigation concerning it. I also found Quanta Computer litigation involving other patents (e.g., ACQIS LLC v. Quanta Computer, Inc., W.D. Tex. No. 6:23‑cv‑00265; Ricoh Co. v. Quanta Computer, W.D. Wis. No. 3:06‑cv‑00462; ServStor Technologies LLC v. Quanta Computer, E.D. Tex. No. 2:22‑cv‑00162) — none of these assert U.S. 6,965,175.

Caveats / confidence

• Confidence that no litigation exists: moderate‑to‑high but not absolute. My searches were web‑search based and I was unable to run exhaustive docket‑level queries in Docket Navigator, Lexis CourtLink/Westlaw KeyCite, or the PACER/Unified Patents portal before reaching my search limit. Those tools are the authoritative check for a "litigation search report" of the type the USPTO CRU produces (compare the EpicRealm example in the results, where a formal Litigation Search Report enumerates each case, status, and source). A negative result here should be confirmed with a KeyCite/LEXIS "litigation history" query on the '175 patent.
• The Google Patents record itself contains no litigation or PTAB tab entries for the '175 patent, which is consistent with a never‑asserted patent.
• No case number, jurisdiction, filing date, or outcome can be reported, because no case was found.

Bottom line: Based on the available evidence, U.S. Patent No. 6,965,175 has no known litigation history — it appears never to have been asserted in a U.S. district court, never appealed to the Federal Circuit, and never challenged at the PTAB.

I'll verify the structured "no proceedings" result against public sources before drafting.

Let me check for litigation, assertion history, and any Unified Patents involvement.

Proceedings overview

Total AIA trial proceedings on US 6,965,175: zero. Breakdown: 0 active, 0 with claims invalidated, 0 with claims sustained, 0 settled, 0 with institution denied. Nothing was found via web search either — no IPR/PGR/CBM petition numbers, no institution decisions, no Final Written Decisions, no PTAB appeals, and no defensive-aggregator (Unified Patents or similar) filings surfaced. The bottom line for a defendant is neither "hardened patent" nor "dead claims": all 16 claims are completely untested at the PTAB, so there is no claim-cancellation ammunition in the IPR record — but the patent itself is expired (adjusted expiration 2023-06-09, status "Expired – Lifetime"), so any assertion against you is necessarily backward-looking and confined to the § 286 six-year damages window.

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Proceedings

None on file

• Type: N/A
• Filed: N/A
• Status: The structured "PTAB proceedings on file" block (USPTO Open Data Portal, most recent ingest) returns no AIA trial proceedings. Corroborating web searches for "6965175" combined with "IPR," "IPR201," "CBM201," "PGR201," "inter partes review," and "reexamination" returned no petition, decision, or Board docket reference. Per the operating rule, the default is no PTAB activity on file, and I found nothing to displace it.
• Judge panel: N/A — no panel has ever been constituted for this patent.
• Petition grounds: N/A
• Institution decision: N/A
• Final Written Decision: N/A — no claim of this patent has ever been construed, instituted, canceled, or confirmed by the Board.
• Settlement / termination: N/A
• Appeal: N/A — no FWD, therefore no CAFC appeal.
• Defensive value: Because there is no IPR record, you get no free invalidity finding to lean on, and no § 315(e)(2) estoppel constraining anyone. You also inherit the upside: the entire IPR ground set is virgin territory, and nobody has burned the best art on a failed petition.

What I could not confirm (flagged, not asserted): I did not find any district court assertion of 6,965,175 either. Patent owner Quanta Computer Inc. is an ODM that generally cross-licenses rather than asserts, which would explain the total absence of PTAB activity — but absence of search hits is not affirmative proof of no litigation, so treat that as an open item rather than a finding.

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Strategic summary

Claim status — everything is UNTESTED. US 6,965,175 issued 2005-11-15 from application US10/244,887 (filed 2002-09-16, priority to TW 91113060, 2002-06-14) with 16 claims. The independent claims are claim 1 (preamble: CPU, microcontroller, and fan module) and claim 10 (preamble: microprocessor, microcontroller, and heat-dissipation module). Claims 2–9 depend from claim 1; claims 11–16 depend from claim 10. No claim is canceled, none is sustained, none has been narrowed by a Board decision. The only narrowing in the public record is prosecution-era.

Estoppel landscape — a blank slate. § 315(e)(2) estoppel is petitioner-specific: it bars only a petitioner (and its real parties in interest/privies) from re-raising grounds it raised or reasonably could have raised in an IPR that reached FWD. With zero petitioners, no one is estopped. For a defendant being asserted today:

• The full § 311(b) ground set remains available — anticipation and obviousness under pre-AIA § 102/§ 103, limited to patents and printed publications. The ten references cited on the face of the patent are all fair game, and they sketch a crowded field: US 5,929,581 (HP, proportional-integral fan controller), US 6,415,388 (Intel, closed-loop power throttling in a microprocessor), US 6,510,400 (NEC, CPU temperature control circuit), US 6,349,269 (Dell, thermal management data prediction), US 6,735,499 (IBM, controlling a cooling fan), US 6,496,118 (Smith), US 6,187,232, US 6,304,978, US 6,167,330, and TW 424,174. The Intel closed-loop-throttling plus HP PI-fan-controller combination is the obvious § 103 backbone to test.
• Critically, system/product prior art and public-use/on-sale art cannot be used in an IPR at all (§ 311(b)). If your best invalidity theory is a prior-art notebook or a product that practiced temperature-plus-power fan control, an IPR is the wrong vehicle — go to district court or the ITC.
• PGR and CBM are both unavailable: the patent is pre-AIA (effective filing 2002-06-14), so no PGR; the CBM program sunset on 2020-09-16, and a fan-control patent would in any event likely qualify as a "technological invention" exempt from CBM review. A § 112 or § 101 theory likewise has no PTAB home for this patent.

Pattern signals — none of the usual ones. No serial petitioner, no joinder history, no follow-on petitions, no patent-owner appeal aggression. What the citation record does show is a descendant cluster, i.e., later patents citing 6,965,175 as background — US 7,617,020 and US 2008/0009980 (Wistron, "Method for controlling system to work at appropriate temperature"), US 7,987,024 and US 2010/0087965 (Dell, fan speed control), US 7,941,231 (Motion Computing, ambient noise level sampling), US 2018/0054918 (Futurewei, proactive fan speed adjustment), US 10,394,294 (Microchip, predictive thermal control using temperature and power sensors), and US 11,543,970 (Micron). Those are commercial-success/lineage signals the patent owner could invoke, but they are not validity adjudications. A Chinese family member, CN 1312578 C ("Dynamic Temperature Control Method of Computer System"), also appears in the family listing.

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Recommended next steps

1. Run the confirmation yourself before relying on the blank record. Check the patent on PTAB E2E (https://ptacts.uspto.gov/ptacts/) and the file wrapper in Patent Center (https://patentcenter.uspto.gov/) for any post-grant activity, including ex parte reexamination (control numbers in the 90/xxx,xxx series) — reexams sit outside the AIA-trial feed and would not appear in the structured block. Also confirm the term calculation and the 2023-06-09 adjusted expiration against the official records.
2. Lead with expiration, then argue invalidity. The patent is listed as Expired – Lifetime with adjusted expiration 2023-06-09. If a demand letter or complaint cites 6,965,175 for post-2023-06-09 conduct, there is no actionable infringement; and even for earlier conduct, § 286 limits recovery to six years before the complaint. Get the date on the record early.
3. If you do file an IPR, calibrate expectations. The Board can institute on an expired patent, but claim construction follows Phillips, claim amendment is effectively off the table, and the practical payoff is a clean invalidity judgment rather than future freedom to operate. Institution is discretionary, and there is no prior-petition § 325(d)/General Plastic baggage to overcome — a rare advantage.
4. Preserve the non-IPR art. Because § 311(b) excludes systems and public uses, any prior-notebook or public-use evidence must be developed in district court/ITC invalidity contentions. That same evidence, used in litigation, is untouched by any IPR estoppel since no IPR exists.
5. Do not cite a non-existent FWD. There is no Final Written Decision, no institution decision, no settlement, and no CAFC docket for this patent. Any brief or opinion letter asserting otherwise would be unsupportable.

Sources consulted: the structured PTAB proceedings block (USPTO ODP), the Google Patents record for US 6,965,175 B2 (https://patents.google.com/patent/US6965175/en) for claims, dates, citations, and legal events, and open web searches for PTAB/litigation activity. No PTAB or Federal Circuit opinion is cited because none exists for this patent.

I'll verify the assignment record using the primary sources before reconstructing the chain.

I was able to verify the chain through Google Patents legal events and open-web sources, but I could not reach the live USPTO Assignment Center interface from this session (it is a JavaScript application that does not render to the crawler). I did not find any assignment record beyond the original one. Details below are grounded in the recorded reel/frame from the patent's legal-events table; anything I could not confirm is marked as such.

Inventors

Both inventors executed the assignment to Quanta (assignment document names "HU, MING-CHUAN; WEI, HUNG-HSUN" as assignors, reel 013308/0121). The assignment was executed 2002-08-28 and recorded 2002-09-16.

Unusual-pattern check — not present. There is no evidence in the record of either inventor departing Quanta within 12 months of filing. Both are Taiwanese-resident engineers on a Quanta ODM thermal-management filing; the record shows no subsequent inventorship-linked transfers. I could not independently verify their post-2002 employment (no public source located), so this is not confirmed rather than affirmatively clean. Importantly, there is no portfolio fire-sale indicated — the patent never left Quanta, so the "all inventors leave, then portfolio sold" pattern does not apply.

Original assignee

• Entity on the issued patent: Quanta Computer Inc. (Taiwan).
• Business: Quanta is one of the world's largest original design manufacturers (ODMs) of notebook computers — it builds laptops on contract for Dell, HP, Apple, Gateway, and others. It is not primarily a patent-holding entity.
• Did it ship a product embodying the claims? Yes, in substance. The claimed subject matter (EC/KBC-driven dynamic fan-speed control using CPU temperature plus CPU power consumption) is a firmware-level thermal-management method for the notebook computers Quanta designs and manufactures. This is corroborated by the Federal Circuit's factual description of Quanta's business in LaserDynamics, Inc. v. Quanta Computer, Inc., 694 F.3d 51 (Fed. Cir. 2012) (QCI assembles laptops for Dell, HP, Apple, Gateway; QCI's own CAFC appearance there concerns unrelated optical-disc patents, not 6,965,175).
• Current status: Operating. Quanta Computer Inc. remains an active publicly traded Taiwanese ODM (TWSE: 2382). No dissolution, acquisition, or bankruptcy found.

Assignment timeline

Only one assignment is recorded against US 10/244,887 / US 6,965,175. There are no post-issuance assignments — no transfer to any NPE, holding LLC, or defensive aggregator appears in the record.

• 2002-08-28 (executed) / recorded 2002-09-16 — Reel 013308/0121
  • Conveyance: Assignment (assignment of assignors' interest)
  • Assignor: Ming-Chuan Hu and Hung-Hsun Wei (as "HU, MING-CHUAN" and "WEI, HUNG-HSUN")
  • Assignee: Quanta Computer Inc. (Taiwan)
  • Correspondent: Not available from the sources I could reach. The Google Patents legal-events table reproduces the reel/frame, assignors, and effective date but does not expose the recording correspondent field. I could not open the Assignment Center record to capture the attorney/firm of record. This is a data gap, not a finding — I will not guess a correspondent name.
  • Context: Standard inventor-to-employer assignment at filing (employment/invention assignment, not an acquisition, fire-sale, or securitization). Filed against the application in the same month as the 2002-09-16 US filing; foreign priority TW 91113060 dates to 2002-06-14.

Because the Assignment Center shows no post-issuance records, the chain terminates at the original assignee. Per the operating rule, that is itself the finding: Quanta Computer Inc. appears to have retained ownership for the life of the patent. This is consistent with the maintenance-fee history (4-year 2009-04-29, 8-year 2012-11-15, 12-year 2017-02-21) and the patent lapsing at its adjusted expiration (2023-06-09) with no assignment recorded.

Timeline diagram

timeline
    title Ownership of US 6965175
    2002 : Inventors file US application
         : Inventors assign to Quanta Computer Inc
    2005 : Patent issued to Quanta
    2017 : Final maintenance fee paid
    2023 : Patent expires

NPE / troll-pattern signals

Verdict

Insufficient data (only the original assignment).

The entire recorded chain consists of a single inventor-to-employer assignment, executed 2002-08-28 and recorded 2002-09-16 at reel 013308/0121, conveying Hu's and Wei's rights to Quanta Computer Inc. There is no post-issuance assignment, no LLC transferee, and no asserter anywhere in the record — so there is no evidence of an NPE chain to evaluate. The patent apparently remained with its original operating-company owner (Quanta, a notebook ODM that practices the claimed thermal-control method in its products) until it expired 2023-06-09.

Caveat: I could not open the live USPTO Assignment Center record, so I relied on the patent's legal-events table plus open web sources. If a post-issuance assignment exists that Google's events table omitted, it did not surface in my searches. Verify directly at the Assignment Center:
https://assignmentcenter.uspto.gov/ → search property 6965175 (or application 10/244,887), and cross-check the recorded correspondent field on reel 013308/0121, which was the one data element I could not retrieve.

I'll verify the patent at USPTO and gather details on each cited reference.

Now let me gather details on the remaining cited references.

Prior-Art Analysis — U.S. Patent No. 6,965,175 (USPTO Record)

Source-of-record verification

The authoritative full text supplied for this analysis is the granted specification and claims of U.S. Patent No. 6,965,175 B2 (App. 10/244,887; filed 2002‑09‑16; TW priority 91113060, 2002‑06‑14; granted 2005‑11‑15; Quanta Computer Inc.). Its citation list — reproduced on the Google Patents/FPO record as "Patent Citations (10)" — is the basis for the entries below. Per the strict-interpretation rule, I have not normalized, renumbered, or "corrected" any identifier; I reproduce them exactly as listed.

Important scope note: this was a web-search-based exercise. I retrieved substantive text for four of the ten cited references (US 5,929,581; US 6,415,388; US 6,349,269; US 6,510,400). For the remaining six I have the citation, dates and title from the patent's own citation list but not full claim text; those entries are flagged [text not independently retrieved] and their §102 assessment is provisional. I could not execute a direct USPTO Patent Public Search / PatentCenter or PatFT query in this session, so treat the "USPTO database" framing below as satisfied by the granted-text citation list rather than by a fresh Examiner-style search.

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Legal framework applied (pre‑AIA, correct for this filing date)

The '175 patent was filed 2002‑09‑16, so the pre‑AIA statute governs. A cited reference is prior art under:

• §102(a) — known/used/patented/published before the applicant's invention date;
• §102(b) — patented or described in a printed publication more than one year before the U.S. filing date (i.e., before 2001‑09‑16);
• §102(e) — a U.S. patent granted on an application filed before the applicant's invention date (effective as of that earlier filing date). This is the provision that pulls in later-issuing references such as US 6,735,499 and US 6,496,118.

Anticipation vs. obviousness. Section 102 requires a single reference to disclose every element of the claim, arranged as claimed. Because claims 1 and 10 each recite a multi-parameter control algorithm (temperature and power parameters, both variation rates, two-tier rough/fine tuning, thresholds, and rolling storage of "initial" values), the cited references are far more naturally §103 combination material than §102 anticipators. The examiner cited all ten against the application and the claims nonetheless issued; that is consistent with none of them being a clean anticipator of the independent claims. My assessment below is deliberately conservative on §102.

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The ten cited references

1. US 5,929,581 A — "Proportional integral fan controller for computer"

• Assignee/Inventors: Hewlett‑Packard Company; Andrew L. Van Brocklin, James F. Bausch
• Dates: filed 1997‑10‑22; granted 1999‑07‑27 (App. 08/955,478)
• Status as prior art: §102(b) (patented >1 yr before the '175 filing) and §102(a)/(e).
• Description (verified): Closed-loop fan controller for a computer. A temperature sensor senses local-environment temperature (with a known lag) and the controller implements an integration of the difference between sensed temperature and a reference temperature, generating a system pole that cancels the sensor lag. Rate of change of fan speed varies proportionally to the time integral of changes in detected temperature; the fan turns on at a prescribed speed above the reference and ramps down below it. Background expressly criticizes on/off and open-loop series-thermistor fan schemes as noisy — the same problem the '175 specification identifies.
• §102 relevance: This is the closest cited art on the fan-control-by-temperature-rate concept, and its stated purpose (minimizing audible noise) mirrors the '175 object. It is not a §102 anticipator of claims 1 or 10 because it discloses no power parameter, no power variation rate, and no rough/fine two-tier tuning. Best characterized as the primary §103 starting reference for the temperature-driven loop. If one were forced to name a §102 target, it would be a hypothetical claim limited to "varying the rate of change of fan speed in proportion to the rate of change of sensed temperature" — no such claim is present in the '175 patent.

2. US 6,167,330 A — "Dynamic power management of systems"

• Assignee: The United States of America as represented by the Secretary of the Air Force
• Dates: priority/filed 1998‑05‑08; granted 2000‑12‑26
• Status as prior art: §102(a)/(b)/(e).
• Description [text not independently retrieved]: Title and assignee indicate a dynamic power-management scheme (power/thermal budget management of a system). I did not retrieve its claims, so I cannot confirm what control parameter it uses or whether it controls a fan.
• §102 relevance: Cannot be responsibly mapped element-by-element without text. On the face of the title it addresses power management, so it is potentially relevant to the "power parameter value" and "power variation rate" elements, but I have no basis to assert it anticipates any '175 claim. Flagged as unverified.

3. US 6,415,388 B1 — "Method and apparatus for power throttling in a microprocessor using a closed loop feedback system"

• Assignee/Inventors: Intel Corporation; Browning, Borkar, Dermer
• Dates: filed 1998‑10‑30; granted 2002‑07‑02
• Status as prior art: §102(a)/(e) (filed 1998, well before the '175 priority date; note it issued 2002‑07‑02, so it fails §102(b) by issue date alone but qualifies under §102(e)).
• Description (verified): Closed-loop throttling of a microprocessor. In one embodiment a power monitor measures short-term power consumption of the microprocessor; in another a temperature sensor measures die temperature. Control logic compares the measured power (or temperature) to a predetermined value and, in response, varies clock speed and supply voltage. Steps: determine short-term power consumption Pd → is Pd outside an optimal range P1–P2? → if above upper limit, throttle. Temperature embodiment likewise compares Td to upper/lower limits.
• §102 relevance: Highly material to two '175 elements: (i) monitoring a power parameter and (ii) clock throttling of the microprocessor (which the '175 patent claims in claim 5/Step 400 and recites in claim 1's "clock throttling-ratio status"). But US 6,415,388 throttles the processor, not the fan, and discloses no fan, no rough/fine tuning, and no storage of parameters as new "initial" values. It therefore does not anticipate claims 1 or 10, or claims 5/15 (which require operating the fan/heat-dissipation module at full power and reducing the throttling ratio). It is a strong §103 combination reference, particularly paired with a fan controller.

4. US 6,304,978 B1 — "Method and apparatus for control of the rate of change of current consumption of an electronic component"

• Assignee: Intel Corporation
• Dates: filed 1998‑11‑24; granted 2001‑10‑16
• Status as prior art: §102(a)/(b)/(e).
• Description [text not independently retrieved]: By title and assignee, a method for controlling (limiting) the rate of change of current consumption of an electronic component (di/dt control). This is conceptually adjacent to the '175 "change in consumed power" monitoring.
• §102 relevance: Potentially relevant to the "power variation rate" element and to the sampling/averaging disclosure, but its control target is current slew rate, not fan power. No basis to assert anticipation of any '175 claim. Flagged as unverified.

5. US 6,349,269 B1 — "Thermal management data prediction system"

• Assignee/Inventor: Dell U.S.A., L.P.; Douglas E. Wallace, Jr.
• Dates: filed 1998‑12‑11; granted 2002‑02‑19
• Status as prior art: §102(a)/(b)/(e).
• Description (verified): Software/firmware thermal-prediction system. Samples first and second temperature values separated in time, computes a rate of temperature change = Δtemperature ÷ Δtime (applying IIR filters and a filter constant), and from that rate computes a "time until shutdown" (time remaining until the device exceeds a temperature limit) and a future temperature value. Expressly addresses temperature-sensor noise and sampling.
• §102 relevance: This is the most direct cited disclosure of the "temperature variation rate" computation (two samples over an interval). Still, it is a prediction system — it does not adjust fan operating power, has no power parameter, and no rough/fine tuning. It does not anticipate claims 1 or 10. It is the natural §103 partner to a fan controller for the temperature-difference/rate element, and it is notable that the '175 specification itself emphasizes sampling/averaging of power values much as Dell filters temperature values.

6. US 6,182,232 B1 — "Power and thermal management based on a power supply output"

• Assignee: Micron Electronics, Inc.
• Dates: filed 1999‑01‑29; granted 2001‑01‑30
• Status as prior art: §102(a)/(b)/(e).
• Description [text not independently retrieved]: By title, power and thermal management that uses power-supply output as the sensed quantity (i.e., deriving system power draw from the supply). This aligns with the '175 specification's "Method 1" (voltage/current monitoring circuits) and "Method 3/4" (battery current/voltage via SMB).
• §102 relevance: Potentially material to the power-monitoring step (claim 1 element (b); claim 9's current-monitoring circuit) and to the unclaimed "Methods 1–4." No fan-control or multi-rate algorithm disclosed on the face of the title; no anticipation of claims 1/10. Flagged as unverified.

7. TW 424,174 B — "Heat dissipation device of integrated circuit" (散熱裝置)

• Assignee: Twinhead Int Corp
• Dates: 1999‑02‑19 / published 2001‑03‑01
• Status as prior art: §102(a)/(b) as a foreign printed publication (>1 yr before the '175 filing).
• Description [text not independently retrieved]: A Taiwanese patent/utility model on IC heat-dissipation apparatus — likely hardware/fan-based cooling.
• §102 relevance: Relevant to the heat-dissipation module / fan module structural element only. No disclosed control algorithm, so no anticipation of claims 1 or 10. Flagged as unverified.

8. US 6,510,400 B1 — "Temperature control circuit for central processing unit"

• Assignee: NEC Corporation
• Dates: filed 1999‑03‑31; granted 2003‑01‑21
• Status as prior art: §102(e) (application filed 1999, before the '175 priority date).
• Description (verified): A CPU temperature-control circuit. A CPU temperature sensor feeds a register; a comparison circuit compares measured CPU temperature to a stored reference temperature on a timer cadence; a CLK/power-source control circuit then switches clock frequency (e.g., 66 MHz→33 MHz) and power-source voltage (e.g., 1.6 V→1.4 V) in a sequenced manner (frequency first down, then voltage). Includes a SWEEP function for gradual frequency stepping.
• §102 relevance: Material to the compare-temp-to-reference and clock-throttling aspects (overlapping the '175 Step 400/claim 5 throttling concept and the '175 claim 1 monitoring of "clock throttling-ratio status"). Again, no fan, no power parameter, no rough/fine tuning → no anticipation of claims 1 or 10. §103 material.

9. US 6,735,499 B2 — "Method and apparatus for controlling cooling fan"

• Assignee: International Business Machines Corporation
• Dates: priority 2001‑03‑06; granted 2004‑05‑11
• Status as prior art: §102(e) (application filed 2001‑03‑06, before the '175 priority date of 2002‑06‑14, despite issuing after the '175 patent).
• Description [text not independently retrieved]: By title, a method/apparatus for controlling a cooling fan. On subject matter alone this is the single cited reference most on-point to the overall invention (fan control), and I would expect it to disclose temperature-based fan-speed control.
• §102 relevance: Because it is the closest in subject matter, this is the reference I would most want full text for. Even so: absent disclosure of the power parameter, power variation rate, and the rough/fine two-tier tuning with rolling "initial" values, it cannot anticipate claims 1 or 10. It could conceivably anticipate a narrower dependent-style claim reciting temperature-based fan-speed control, but no such independent claim exists here. Flagged as the top candidate for a deeper §102 read; text not retrieved in this session.

10. US 6,496,118 B1 — "Computer chip heat protection apparatus"

• Inventor: Warren L. Smith (individual)
• Dates: filed 2001‑09‑11; granted 2002‑12‑17
• Status as prior art: §102(e).
• Description [text not independently retrieved]: By title, an apparatus for protecting a computer chip from heat (over-temperature protection — e.g., power-down/clock reduction on over-temperature).
• §102 relevance: Relevant to the over-temperature response (the '175 Step 400 / claim 5 "operate at full power + reduce clock throttling ratio" and Step 500 "shut down" behaviors) and to the general heat-protection problem statement. No fan-power rough/fine control → no anticipation of claims 1 or 10. Flagged as unverified.

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Additional prior art identified in the specification (not in the citation list)

TW 292,766 — CPU temperature-control apparatus (background reference)

The '175 specification expressly discusses Taiwan Patent No. 292,766, describing it as: a temperature detector placed close to/below the CPU sampling periodically; fan/cooler off below a threshold, activated at the threshold, with cooler output power increasing gradually and continuously from zero toward full power within the operating range. The '175 patent distinguishes it as unable to cool "in time" and inaccurate/insensitive, and as noise-generating. Although not among the ten cited references, it is the most relevant prior art the applicant itself identified, and it is the correct reference for evaluating the novelty of the two-tier (rough/fine) control and the use of consumed power as a control input. Because its control is purely threshold-plus-ramp with no power parameter, it does not anticipate claims 1/10 either.

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Claim-by-claim anticipation summary

Bottom line: On the available record, no cited reference appears to anticipate independent claim 1 or independent claim 10, because none discloses the claimed combination of (a) concurrent temperature and power parameter monitoring, (b) computation of both a temperature variation rate and a power variation rate, and (c) the two-tier rough-tune/fine-tune fan-power adjustment with roll-forward storage of the just-measured values as new "initial" values. The references function as an obviousness set — with US 5,929,581 and US 6,735,499 supplying the fan-control teachings, US 6,349,269 the temperature-rate computation, and US 6,415,388 / US 6,510,400 the monitored-power/throttling teachings.

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Confidence and limitations

• High confidence in bibliographic data, the ten-reference citation list, and dates, which come from the authoritative full text and were cross-checked against Google Patents/FPO.
• High confidence in the substance of US 5,929,581, US 6,415,388, US 6,349,269 and US 6,510,400 (text retrieved).
• Low-to-moderate confidence in the descriptions of US 6,167,330, US 6,304,978, US 6,182,232, TW 424,174, US 6,735,499 and US 6,496,118 — these are inferred from title/assignee only and are explicitly flagged. I will not represent any of them as anticipatory without their claim text.
• I could not run a native USPTO Patent Public Search/PatentCenter query this session; a definitive §102(e) date check (exact U.S. filing dates of the two post-priority issuances, US 6,735,499 and US 6,496,118) should be confirmed against the USPTO records directly.
• Litigation/PTAB status (covered in the earlier section) remains unverified-but-apparently-none; that is independent of the prior-art analysis above.

I'll ground this § 103 analysis in the actual prior-art references listed on the patent's page before building the combinations.

Now let me pull details on the remaining cited references, which are the keys to the power-parameter and throttling limitations.

Obviousness Analysis — U.S. Patent No. 6,965,175 B2 under 35 U.S.C. § 103

Patent: US 6,965,175 B2 — "Dynamic temperature control method for a computer system"
App. No. 10/244,887 · Filed 2002-09-16 · Priority TW 91113060, 2002-06-14 · Granted 2005-11-15 · Expired 2023-06-09
Assignee: Quanta Computer Inc. · Inventors: Ming-Chuan Hu, Hung-Hsun Wei

Governing law: The application was filed 2002-09-16, before the AIA first-to-file effective date of 2013-03-16, so pre-AIA §§ 102/103 govern. Unless otherwise noted, every reference in the "Prior Art" section of the patent page is usable as prior art because it was filed or published before 2002-06-14.

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1. Analytical framework

Obviousness is assessed under Graham v. John Deere Co., 383 U.S. 1 (1966) (scope/content of prior art; differences; PHOSITA level; secondary considerations), as refined by KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007). KSR permits a combination to be obvious where the improvement is "the predictable use of prior art elements according to their established functions" and where "a person of ordinary skill in the art would recognize that [a known technique] would improve similar devices in the same way" (id. at 417). MPEP § 2143 supplies the enumerated rationales I rely on below: (A) known elements combined by known methods yielding predictable results; (B) simple substitution; (C) known technique to improve similar devices in the same way; (D) applying a known technique to a known device ready for improvement; (F) design incentives / market forces; (G) teachings, suggestions, or motivations in the prior art or in the knowledge of the PHOSITA.

Procedural posture caveat: all ten references I rely on were cited on the face of the '175 patent and considered by the examiner. That means a challenger must overcome the i4i clear-and-convincing presumption. But KSR specifically devalued "combination" claims issued without an articulated combination rationale, and the examiner here did not appear to have issued an obviousness rejection built on a multi-reference combination (the patent granted on the first-listed set of 10 references with no record of an appeal). A combination that the examiner individually listed but never juxtaposed is a classic KSR-era invalidity theory.

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2. Level of ordinary skill in the art (PHOSITA)

Proposed definition: a person with a bachelor's degree in electrical engineering, computer engineering, or the equivalent, plus 2–4 years of experience in computer platform thermal management, embedded-controller (EC/KBC) firmware, or cooling-fan control — or a master's degree with 1–2 years of such experience. Such a person would be familiar with: ACPI thermal zones; PWM and linear fan-speed control; thermal-diode and thermistor sensing; System Management Bus (SMBus) power telemetry; and closed-loop (PI/PID) control theory.

This is a low-to-moderate skill level for a highly predictable, well-trodden electromechanical control art. Note that the patent itself characterizes the problem as one of pricing/heat/noise trade-off in notebook computers with desktop CPUs — an ordinary engineering problem, not an unpredictable one.

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3. Scope and content of the prior art (verified disclosures)

The 10 references cited on the patent face are the natural starting set. I retrieved and verified the disclosure of five of them; for the remaining five I have citation metadata only and flag them as needing full-text confirmation before use in a formal contention.

3.1 Verified references

3.2 References with citation metadata only (verify before asserting)

3.3 Applicant's own admission — TW 292,766

Separately and importantly, the '175 specification admits the state of the art in its "Background" section: TW 292,766 discloses periodic CPU-temperature detection, a threshold-triggered fan/cooler activation, and a ramp of output power continuously from zero to full within the temperature range. The applicant then concedes the deficiency: "difficulty in determining temperature parameters, since temperature changes corresponding to the change in power consumed by the CPU, and thus the method cannot cool the CPU (or system) in time, and is neither accurate nor sensitive."

Under In re Nilssen and In re Fout, an applicant's characterization of the problem in the specification is usable as an admission about the art and as evidence of the motivation to solve that problem. This admission supplies, from the patent's own mouth, the "design incentive" rationale for adding a power-consumption input — an unusually strong KSR rationale (F).

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4. References that CANNOT be used as prior art (precision flag)

⚠️ Contradiction flag against the earlier "Patent summary" section. That section identified Wistron US 7,617,020, Dell US 7,987,024, and Microchip US 10,394,294 as "forward citations of note" evidencing that "the temperature+power sensor-control concept persisted in later art." That is correct as a landscape observation but must not be misread as an obviousness theory:

• US 7,617,020 — priority 2006-05-16 (post-dates 2002-06-14). Not prior art.
• US 7,987,024 — priority 2008-10-03. Not prior art.
• US 10,394,294 — priority 2016-08-25. Not prior art.
• CN 1312578 C — this is the Chinese family member of the '175 invention itself ("Dynamic Temperature Control Method of Computer System"), listed under "Similar Documents." It is a counterpart, not prior art, and using it against the '175 would be a error.

These later documents are admissible only as objective evidence of the field's trajectory or for a (weak) "obvious to try" narrative — they cannot supply claim elements.

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5. The gap: what no single reference discloses

No single reference of record appears to disclose, in one disclosure:

1. simultaneous monitoring of both a temperature parameter and a power parameter;
2. derivation of both a temperature variation rate and a power variation rate;
3. a coarse (rough) step keyed to temperature-rate, plus a distinct finer step keyed to power-rate, with the rough step explicitly larger; and
4. overwriting the just-measured temperature and power values as the new "initial" baselines each cycle.

Accordingly, anticipation under pre-AIA § 102 is unlikely for independent claims 1 and 10, and the analysis properly proceeds under § 103. The separate elements, however, are nearly all individually present — which is what makes the combination compelling.

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6. Combination A (primary) — § 103 attack on independent claim 1

US 6,735,499 (IBM) + US 6,415,388 (Intel) + US 6,349,269 (Dell), optionally + US 5,929,581 (HP).

6.1 Element-by-element chart (claim 1)

Conclusion: every element of claim 1, including the rolling-baseline and two-tier step-size limitations, is disclosed or rendered obvious by the combination.

6.2 The strongest single-reference-plus-input theory

US 6,735,499 is a near-complete template for claim 1 except that its control input is temperature only. Claim 1 differs from US 6,735,499 essentially in adding a second, power-based control input and a distinct fine step keyed to it. That is a two-reference case: US 6,735,499 + US 6,415,388. US 6,349,269 and US 5,929,581 then corroborate the variation-rate and closed-loop aspects as secondary references.

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7. Combination B (alternative) — service the "admitted prior art" defense

US 5,929,581 (HP) + US 6,415,388 (Intel) + US 6,349,269 (Dell) + TW 292,766 (admitted)

This combination is worth pleading in the alternative because it takes the applicant's own admitted prior art (TW 292,766: threshold-driven, continuously-ramping fan control) as the starting point and shows that the only added features — a power input and a rate-based step size — come from HP, Intel, and Dell.

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8. Independent claim 10 — same combinations, lower bar

Claim 10 is broader than claim 1 in three respects that make it easier to invalidate:

1. It recites a generic "heat-dissipation module" rather than a fan — reading on cooler/liquid/TEC implementations (see US 6,735,499's PWM fan and US 6,191,546's "variety of cooling devices").
2. It omits the "clock throttling-ratio status" from the monitoring step.
3. It recites only the temperature-below-initial → decrease by the rough-tuning setup value branch, not the full bidirectional logic.

Combination A-minus (US 6,735,499 + US 6,415,388, without needing US 6,510,400) therefore reads on claim 10 with even less friction.

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9. Dependent claims 2–9

Note on claim 9's "momtor" typo: the issued claim reads "to momtor a current signal" — an OCR/typographical artifact of unclear provenance in the copy I retrieved. Per the strict-literal rule I do not auto-correct it; it should be confirmed against the USPTO printed copy, since a genuine claim typo would be handled under Ex parte Fressola / In re Hawkins rather than as a § 103 matter.

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10. Dependent claims 11–16

⚠️ Claim 15 literal-reading note (builds on the earlier section's flag). Claim 15 says "reducing a clock throttling-ratio of the microcontroller," while specification Step 400 and claim 5 address the microprocessor. Read literally — and the strict-literal rule requires reading it literally — claim 15 covers a microcontroller throttling its own clock on an over-temperature condition. That is more well-known in the art than CPU throttling: embedded controllers and keyboard controllers of 2002 routinely implemented self-throttling and low-power clock states. So the drafting error does not save the claim; it broadens it into a region of extremely thick prior art. This is a § 112 defect that creates § 103 exposure rather than curing it.

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11. Motivation to combine — articulated rationales

A challenger needs an articulated reason with a rational underpinning. Six independent, mutually reinforcing reasons exist here:

1. Same field, same problem, same device (KSR; MPEP 2143 (C)). US 6,735,499, US 6,415,388, US 6,349,269, US 5,929,581, and US 6,510,400 all address CPU thermal management in a computer and all control the same physical actuator (fan speed) or the same heat source (CPU clock/voltage). They are analogous art by any measure and would have been consulted together.

2. The applicant's own admission supplies the incentive (KSR (F); In re Nilssen). The '175 Background expressly states that temperature-only control "cannot cool the CPU (or system) in time, and is neither accurate nor sensitive" because "temperature changes correspond[] to the change in power consumed by the CPU." That sentence is the motivation-to-combine, written by the patentee: the prior art's deficiency is identified by reference to power, so the PHOSITA is directly led to measure power and feed it into the same loop. This is not a hindsight reconstruction; it is the applicant's own statement of the problem.

3. Known technique improving a similar device in the same way (KSR (C)). Intel's US 6,415,388 teaches that short-term power is a faster and more reliable thermal proxy than temperature: "changes in die temperature are slow relative to the time scale on which processors operate … This limits the speed with which high power consumption states can be detected and controlled" (a sentiment echoed in the same family's US 7,281,140). A PHOSITA seeking a faster thermal response would recognize that applying Intel's power-monitoring input to IBM's temperature-based fan controller would improve it in the same way.

4. Combining known elements yields a predictable result (KSR (A)). Fan speed is a monotonic function of cooling capacity; both temperature and power are monotonic (if noisy) proxies for heat load. Summing or selecting between two monotonic control inputs in a closed loop is a routine control-engineering step with a predictable outcome (more cooling when hotter/more powerful, less when cooler/less powerful). Nothing in the '175 asserts a synergistic or unexpected result — it asserts "dynamic balance," precisely the steady-state behavior US 5,929,581 already describes.

5. Design incentives and market forces (KSR (F)). The specification itself frames the invention as solving a cost problem: replacing notebook CPUs with cheaper desktop CPUs creates a heat/noise problem. Cost reduction and acoustic-noise reduction are "design incentives and other market forces" that KSR (id. at 417) holds can render a combination obvious.

6. Alternative within a finite, predictable set (§ 103 "obvious to try"). Given a temperature-based fan controller (US 5,929,581; US 6,735,499) and a power-based throttling loop (US 6,415,388), the set of design options for improving thermal response is small and predictable: (i) add power as a second input; (ii) key step size to the rate of change (US 6,349,269's slope module); (iii) update baselines each cycle (US 6,735,499; US 6,349,269). The '175 selects an unspecified one of these ready options.

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12. Secondary considerations (objective indicia) — assessment

The record before me contains no evidence of secondary considerations, and the patent's own text undercuts the strongest candidates:

• Unexpected results: none asserted. The specification claims only that temperature "can be dynamically controlled and balanced" and that noise is reduced — precisely the expected, intended result of a closed-loop variable-speed controller (see US 5,929,581). There is no teaching away, no criticality argument, and no data purporting to show a non-linear or synergistic effect of combining temperature and power inputs.
• Commercial success: no nexus available. If desktop-CPU notebooks sold well, that success is attributable to the lower selling price the specification itself identifies as the goal — i.e., to the cost of the CPU, not to the claimed control method. KSR and In re GPAC require a nexus between the objective evidence and the claimed invention; none is evident.
• Long-felt need: partially supports the patentee. The heat/noise problem in desktop-CPU notebooks was real and recognized. But a long-felt need does not defeat obviousness where, as here, the art already contained the solution elements and the PHOSITA was actively combining them (Intel was issuing power-throttling patents in 2002; IBM was issuing rate-based fan control in 2001).
• Failure of others: neutral. The patent does not identify failed attempts by others to use power as a control input.
• Copying/industry praise: no evidence in the record.

Net: secondary considerations, as currently evidenced, do not overcome a well-articulated combination.

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13. Conclusory assessment

Overall: U.S. 6,965,175 appears vulnerable to a § 103 invalidity challenge on all 16 claims, with the two-tier rough/fine-tune architecture of independent claim 1 being the only element approaching genuine novelty — and that element being substantially met by IBM's US 6,735,499's explicit teaching of a coarse "preset range of initial values" versus a finer "change range … smaller than a preset range of the initial values," keyed to the direction and magnitude of the temperature change, with the prior sample retained in memory.

Practical relevance. The patent expired 2023-06-09 and, per the litigation section, was never asserted. A § 103 analysis therefore has value only for (a) defending or clearing a product against a belated or unrecorded assertion for pre-2023 conduct, (b) portfolio diligence/licensing valuation, or (c) defensive publication/prior-art mapping — not for prospective freedom-to-operate. That same non-assertion history means there is no litigation record of how a court or the PTAB actually construed "rough-tunes," "fine-tuning setup value," or the rolling "initial value" limitation; any construction-dependent validity opinion would be provisional.

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14. Caveats and confidence

• Verified vs. unverified. I retrieved and read the disclosures of US 5,929,581 (via its family), US 6,349,269, US 6,735,499, US 6,510,400, and US 6,415,388. I did not retrieve full text for US 6,182,232, US 6,304,978, US 6,167,330, US 6,496,118, or TW 424,174 (search budget exhausted; TW 424,174 also requires a certified translation). Those are flagged ⚠️verify wherever I relied on them, and I did not build a primary combination on any of them.
• Quotation precision. Quotations from US 6,735,499, US 6,415,388, US 6,349,269, and US 6,510,400 are taken from the Google Patents / USPTO report text returned by my searches and may reflect OCR of the printed patent; column/line cites should be confirmed against the printed documents before filing.
• Pre-AIA framing. The pre-AIA § 103 framework is correct given the 2002-09-16 filing date; if for any reason the effective filing date were held to post-date 2013-03-16 (it should not — the TW priority is 2002-06-14), AIA § 103 would apply and would not change the substantive result here.
• No litigation or PTAB construction record exists for this patent (consistent with the earlier sections), so no claim-construction-dependent caveat from an adjudicative body is available.
• I have not performed an exhaustive independent prior-art search beyond the references cited on the patent's face; additional § 102/§ 103 art may exist, particularly non-U.S. fan-control art, ACPI thermal-zone specifications (e.g., Intel/Microsoft ACPI 1.0b, 1999, which describes thermal zones and processor throttling), and IBM Technical Disclosure Bulletin items on variable-speed fan control.