US 6867477

I'll verify against live sources, then summarize. Let me run searches for the patent and any litigation.

US 6,867,477 — Verification and Summary

Sourcing note / confidence: My checks were run through general web search against Google Patents, Justia, and CAFC opinion/docket-derived materials — I do not have a direct live query interface to USPTO Patent Center, USPTO Assignment, or the CAFC CM/ECF docket. Numbers below were read literally from the sources I retrieved; I did not auto-correct any identifier. Where I could not verify something, I say so explicitly.

One procedural flag: your prompt states "Current Date: April 26, 2026," while my operating context says 2026-09-28. This affects only the "current" framing of the litigation check, not any patent data.

1. Bibliographic data

2. Abstract (as issued)

"According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor might be a lateral PNP bipolar transistor and the base may comprise, for example, N type single crystal silicon. The bipolar transistor further comprises an emitter having a top surface, where the emitter is situated on the top surface of the base. The emitter may comprise P+ type single crystal silicon-germanium, for example. The bipolar transistor further comprises an electron barrier layer situated directly on the top surface of the emitter. The electron barrier layer will cause an increase in the gain, or beta, of the bipolar transistor. The electron barrier layer may be a dielectric such as, for example, silicon oxide. In another embodiment, a floating N+ region, instead of the electron barrier layer, is utilized to increase the gain of the bipolar transistor."

3. Plain-language overview of the independent claims

Claim 1 — "bipolar transistor" (electron-barrier embodiment)

In plain terms: A bipolar transistor in which the top of the emitter is deliberately left not contacted by silicide. Instead, an "electron barrier layer" sits directly on the emitter's top surface, in the opening bounded by the emitter contact layers and the emitter's top surface. The emitter is physically between that barrier layer and the base — i.e., the barrier is on the far side of the emitter from the base-emitter junction.

Four elements, read literally:

1. a base with a top surface;
2. an emitter with a top surface, the emitter situated on the base's top surface;
3. an electron barrier layer situated directly on the emitter's top surface, in an opening defined by a plurality of emitter contact layers and the emitter's top surface, the barrier layer causing base current in the base to decrease; and
4. wherein the emitter separates the electron barrier layer from the base.

Claim 3 specifies the transistor is a lateral PNP; claim 4 that the barrier layer is a dielectric; claim 5 that the dielectric is silicon oxide; claim 6 that the barrier layer increases beta; claim 7 that the base is N type single crystal silicon; claim 8 that the emitter is P+ type single crystal silicon-germanium. Claim 2 broadly recites a PNP bipolar transistor.

Claim 9 — "PNP bipolar transistor" (floating-N+ embodiment)

In plain terms: The same idea, but the electron diffusion barrier is a floating N+ region (an un-contacted, undriven N+ island) placed directly on the emitter's top surface within the emitter-contact-layer opening, again reducing base current. Notably, claim 9 omits claim 1's "emitter separates the electron barrier layer from the base" clause.

Three elements:

1. a base with a top surface;
2. an emitter with a top surface, situated on the base's top surface; and
3. a floating N+ region situated directly on the emitter's top surface in an opening defined by a plurality of emitter contact layers and the emitter's top surface, the floating N+ region causing base current in the base to decrease.

Claim 10 adds lateral PNP; claim 11 that the floating N+ region is N+ type polysilicon; claim 12 that it causes an increase in beta; claim 13 N type single crystal silicon base; claim 14 P+ single crystal SiGe emitter; claim 15 a dielectric spacer adjacent to the floating N+ region and in contact with the emitter's top surface — notably written as singular "a dielectric spacer… situated adjacent to said floating N+ region," whereas the specification's FIG. 3 discussion describes spacers "within each of two corner sections."

Technical premise common to both claims

Gain (beta) is inverse to base current at constant collector current, and base current has a space-charge recombination component plus an emitter electron-diffusion component. In a conventional device a silicide ohmic contact drives electron concentration to ~zero at the emitter's top interface, creating a steep electron-concentration gradient and high diffusion current. Both claimed structures instead let electrons pile up at that top interface, flattening the gradient and lowering base current. The specification states beta of roughly 20–50 for the invention versus about 10 conventional (a ~2×–5× improvement; the FIG. 4 discussion frames it as ~5× lower base current). The stated manufacturing advantage is that neither structure requires added process steps — the dielectric can reuse existing BiCMOS steps, and the floating N+ polysilicon can be deposited in the same step as the emitter. The specification also notes an alternative where PMOS gate oxide defines the emitter/collector and the emitter/collector are formed by the PMOS source/drain implant or diffusion.

4. Litigation / PTAB / CAFC check — result: nothing found specific to 6,867,477

I ran targeted searches for litigation, post-grant proceedings, and CAFC 2026 dockets involving 6,867,477. I retrieved CAFC materials including 2026 opinion/order and scheduled-case listings, but no result referenced US 6,867,477 — no district court action, no PTAB proceeding, and no Federal Circuit appeal.

Two important qualifiers so you don't over-read that:

• This is an absence of evidence, not evidence of absence. I could not run a direct, authoritative query against CAFC CM/ECF or Docket Navigator; I relied on web-searchable materials, which are incomplete for patent-by-patent litigation checks. Do not treat this as a certified "no litigation" finding.
• Timing cuts against finding any. The patent's term expired (anticipated expiration 2022-11-07), so enforcement today would be limited to past damages within the statutory lookback, which makes assertion in a 2026 docket unlikely as a practical matter. Separately, note that my 2026 CAFC search results were dominated by unrelated 2026 cases (e.g., Contour IP Holding LLC v. GoPro, Slingshot Printing LLC v. Canon U.S.A., ModernaTX v. BioNTech); none of these involve this patent number.

If you need a definitive litigation/assignment history, the authoritative sources are USPTO Patent Center and the USPTO Assignment database (for the '477 record) and the CAFC CM/ECF docket, plus a paid litigation database — all of which should be queried directly rather than through general web search.

I'll research litigation involving US Patent 6,867,477 (Newport Fab / Jazz Semiconductor "High gain bipolar transistor"). Let me run several targeted searches.

The general searches returned noise. Let me run targeted queries against patent litigation sources.

Let me try more specific litigation-database queries.

US Patent 6,867,477 — Litigation Search Results

Bottom line: Based on the searches I was able to run, I found no litigation that asserts or challenges US Patent 6,867,477. I cannot confirm any plaintiff, defendant, case number, or outcome for this specific patent. What follows documents (a) the patent identification, (b) the searches performed and their negative results, and (c) Newport Fab / Jazz Semiconductor litigation that does not involve this patent, which is a common source of false positives.

1. Patent identification (verified against the full text)

Two practical points on assertion history: the patent's term has already run, and it issued to a foundry (Jazz was a specialty analog/mixed-signal foundry), not to a monetization entity. Both facts make affirmative infringement litigation on this patent unlikely.

2. Searches performed and results

I searched generally across the open web and targeted litigation aggregators (Justia Dockets, CourtListener/RECAP, Unified Patents-style NPE data discussed in recent litigation reports, and ITC publications). Queries included the bare number, comma-formatted number, "patent litigation," "district court complaint plaintiff," and combinations with the assignee names.

• Every hit on the string "6867477" outside of the patent itself was a false positive and I am deliberately not treating any of them as this patent:
  • JP Patent No. 6867477 (Hewlett-Packard Development, sheet-media bail control) — a different patent office and a different invention.
  • An EUIAS paper DOI ending in 6867477; a Lithuanian company-registry notice number; a Brazilian corporate filing number; InventorID "6867477" on a patent-review site; and DAI excavation catalog numbers. None is a US patent or a litigation record.
• No docket, complaint, ITC filing, PTAB proceeding, or CAFC decision referencing US 6,867,477 appeared in any search result.

Limitations I want to be explicit about: I could not directly query the Unified Patents litigation portal, PACER, or Docket Navigator (subscription/interface barriers), and my search step budget was exhausted before I could run additional targeted queries against those systems. A negative search result of this kind is not proof of absence — it means no litigation is publicly indexed in the sources I could reach. This is not a legal conclusion, and I am not representing that no suit exists.

3. Related Newport Fab / Jazz litigation that does NOT involve US 6,867,477

These results surfaced repeatedly and are the most likely source of conflation. Neither asserts US 6,867,477, and I state them only to rule them out:

The presence of inventors Marco Racanelli and co-workers as defendants in IQE is worth noting because Racanelli is a named inventor on the '477 patent — but IQE does not involve the '477 patent.

Also note: the Jazz Pharmaceuticals narcolepsy/oxybate litigation that appears in searches is unrelated — different company entirely (Jazz Pharmaceuticals plc, not Newport Fab/Jazz Semiconductor).

4. Ancillary observations

• Assignees of record moved from Newport Fab, LLC → Jazz Semiconductor (via the 2002 assignment), and Jazz Technologies/Jazz Semiconductor was acquired by Tower Semiconductor in September 2008 (per Tower's 2008 Form 20-F). Any hypothetical suit would therefore likely be captioned Tower/Jazz. No such suit on the '477 patent was found.
• Post-issuance activity visible on the face of the record is limited to maintenance-fee payments (4th, 8th, and 12th year) and security-interest/release assignments (Wachovia/Wells Fargo, released 2023) — no reexamination, no reissue, and no litigation flag.
• Date caveat: The user message states the current date is April 26, 2026, but several search results returned are dated after that (e.g., a July 10, 2026 Federal Circuit order). I am reporting what the search results actually say rather than normalizing the dates.

Recommendation

If you need a definitive answer, the searches that would settle this are:

1. Unified Patents litigation portal (portal.unifiedpatents.com/litigation/caselist) — search by patent number, not party name.
2. PACER / Docket Navigator full-text search for "6,867,477" across all district courts and the ITC.
3. PTAB (P-TACTS) for any IPR/PGR on the '477 patent — I found none, which is consistent with a 2002-filed foundry patent nearing expiration.
4. CAFC docket search for "6,867,477."

I did not obtain access to any of these four systems directly, so the honest answer at this time is: no litigation involving US Patent 6,867,477 is known based on the sources I could reach.

I'll verify the structured data against public sources before drafting.

Let me run a few more targeted checks before concluding.

One more check on PTAB docket aggregators and any assertion history.

PTAB Proceedings Report — U.S. Patent No. 6,867,477 B2

Patent: High gain bipolar transistor | Appl. No. 10/290,975 | Filed: 2002-11-07 | Granted: 2005-03-15
Assignee of record: Newport Fab, LLC d/b/a Jazz Semiconductor (now d/b/a Jazz Semiconductor Operating Company) | Status: Expired – Lifetime (anticipated expiration 2022-11-07)

Proceedings overview

Total AIA trial proceedings on file: 0. The USPTO Open Data Portal (ODP) structured "PTAB proceedings on file" block for US 6,867,477 returns zero IPR, PGR, or CBM proceedings — so the breakdown by status is 0 active / 0 claims invalidated / 0 claims sustained / 0 settled / 0 institution denied. The bottom-line defensive posture is therefore not "hardened by IPR" and not "claims canceled" — it is: this patent was never challenged at the PTAB and was never narrowed by any AIA trial; it simply ran its full 20-year term and expired on 2022-11-07. For a defendant receiving a demand today, the operative fact is expiry, not PTAB history.

I verified the ODP default against public sources: targeted searches for an IPR/PGR/CBM number pairing with 6,867,477, for Newport Fab/Jazz Semiconductor as patent owner at the PTAB, and for litigation assertion of this patent produced no AIA trial proceeding. (One search hit, "IPR2024-00796," concerns U.S. Patent 7,483,686 — a different patent entirely — and is not relevant.)

Caveat on confidence: ABSENCE of a proceeding is harder to prove from web search than presence. I have high confidence in the ODP "zero" result as of its most recent ingest, and no public source contradicts it. I have not independently confirmed via a manual PTAB E2E docket query or a full litigation docket sweep; a defendant should treat this as "no known PTAB activity," not "certified clean."

Per-proceeding sections

Not applicable — there are no proceedings to describe. Producing "### {PROCEEDING_NUMBER}" entries here would require fabricating numbers, which I will not do.

What the record does show (the closest thing to a "proceeding" in this file)

⚠️ Number-collision warning: JP Patent No. 6867477 B2 (Hewlett-Packard Development Co., "sheet medium bail control") is an unrelated Japanese patent that shares the digits "6867477." Do not let a docket or search string conflate the two.

Strategic summary

Claim status: all 15 claims are UNTESTED and, more importantly, EXPIRED. Because no IPR, PGR, or CBM was ever filed, there is no claim-level adjudication of US 6,867,477 anywhere in the AIA record. Claims 1–8 (the electron-barrier-layer genus) and claims 9–15 (the floating N+ region genus) stand exactly as they issued on 2005-03-15. The patent was maintained to its full statutory term — fees paid at years 4, 8, and 12 — so this is not a case of a lapsed patent either. The significance is entirely different from a typical PTAB report: there is no canceled claim to point to, but there is also no post-2022-11-07 infringement exposure, because a patent cannot be infringed after expiry. The only live theory would be damages for pre-expiration conduct, i.e., making/using/selling the accused lateral PNP structure on or before 2022-11-07.

Estoppel landscape: clean. Because no IPR was ever instituted against this patent, no § 315(e)(2) estoppel attaches to anyone — not to any petitioner (there is none), not to privies, not to real parties in interest. A defendant today retains the entire universe of invalidity grounds: §§ 102, 103, and 112, in any combination, against any claim, without the "raised or reasonably could have raised" constraint that follows a Final Written Decision. Note also that § 315(b)'s one-year bar is petitioner-specific and only starts on service of a complaint; since no petition exists, no time-bar analysis applies. The one trap to avoid is the § 315(a)(1) bar: if you (or a privy) affirmatively filed a civil action challenging validity of this patent, you were already barred from IPR before it expired — now moot, but relevant if you are coordinating with co-defendants.

Pattern signals: none of the usual ones. There is no serial petitioner, no defensive aggregator in the chain (no Unified Patents or RPX filing appears in the record), and no PTAB appeal to the Federal Circuit — there could not be, absent a proceeding. Newport Fab/Jazz was itself a defendant-side player in the IQE plc v. Newport Fab litigation that produced a precedential Federal Circuit anti-SLAPP opinion (Fed. Cir., 2025-10-15, No. 22-55924 in the Ninth Circuit docket line), but that is a separate commercial dispute and does not bear on 6,867,477's validity. The absence of PTAB activity here is best explained by two mundane facts: (1) the patent is a niche BiCMOS lateral-PNP structural claim owned by a foundry rather than a serial litigant, and (2) it expired before the current assertion wave. Compare the examiner-cited art on the face of the patent — US 5,510,647 (Toshiba), US 5,654,211 (Samsung), US 5,698,890 (NEC), US 5,789,800 (NEC), US 5,786,622 (Tritech), US 6,255,716 (Samsung) — all pre-1998 bipolar structures. That art, or a SiGe-BiCMOS process-flow reference, would have been the obvious § 103 attack; nobody spent the money to make it.

Recommended next steps

1. Lead with the expiry, not the PTAB record. US 6,867,477 expired 2022-11-07 and was never adjudicated invalid. That means:

• Any demand letter asserting infringement for conduct on or after 2022-11-08 fails as a matter of law.
• Recovery is capped by 35 U.S.C. § 286 at six years pre-complaint. If a complaint were filed today (2026-09-28), the recoverable window for pre-expiration conduct runs only from roughly 2020-09-28 to 2022-11-07 — an ~13-month sliver. Demand letters in that window should be scrutinized for whether the accused product was actually made/sold in it, and whether the patentee's damages model improperly extrapolates post-expiry sales.

2. If you nonetheless prepare an invalidity defense (e.g., for a pending suit on pre-expiry conduct), you have full freedom. With zero PTAB history:

• No § 315(e)(2) estoppel, no Fintiv/§ 314(a) discretionary-denial baggage, no IPR-based issue preclusion.
• You may raise §§ 102/103/112 in district court, in an IPR (subject to expiry — the Board can institute on an expired patent, but there is little practical value), or via ex parte reexamination under 35 U.S.C. § 302, which remains available even post-expiry and is a cheap way to attack the surviving claims if the patentee is litigating the tail end.
• The prosecution amendment noted above (addition of "in an opening defined by a plurality of emitter contact layers and said top surface of said emitter" and "wherein said emitter separates said electron barrier layer from said base") is a prosecution-history estoppel and claim-scope asset. Pull the file wrapper from USPTO Patent Center for Application 10/290,975 to confirm exactly what was argued and what art forced the amendment; the pre-grant publication at justia.com versus the granted text at freepatentsonline.com shows the delta on the face of the documents.

3. Verify the negative yourself before relying on it in a filing. The authoritative checks, in order: (a) PTAB E2E / PTAB Center docket search on "6867477"; (b) the USPTO PTAB API; (c) USPTO Patent Center "Patent Trials" tab for Application 10/290,975; (d) CourtListener for any Federal Circuit or district docket citing the patent. Because PTAB FWDs and Federal Circuit Rule 36 dispositions are public, a genuinely invalidated claim would be quotable — here there is nothing to quote, and I will not manufacture a disposition that does not exist.

I'll work from the authoritative patent text first, then try to corroborate the assignment record and ownership chain with searches.

Let me try to pull the actual USPTO assignment records (reel/frame, correspondent) and check for any litigation or asserter listings.

US 6867477 — Assignment & Ownership Chain Analysis

Patent: US 6,867,477 B2 — "High gain bipolar transistor"
App. No.: 10/290,975 · Filed: 2002-11-07 · Issued: 2005-03-15 · Anticipated expiration: 2022-11-07 (patent is now expired)
Current assignee of record (per patent front page): Newport Fab, LLC (dba Jazz Semiconductor)
Verification link: USPTO Assignment Center / legacy Assignment Search — search "6867477"

Note on sourcing: The USPTO Assignment Search application could not be queried directly in this session. The reel/frame citations below are drawn from the authoritative Google Patents legal-events record (which mirrors USPTO assignment data) and, where noted, cross-checked against a sibling Newport Fab patent. The "correspondent of record" field was not exposed in any source I could retrieve — I flag that explicitly rather than guess, since a fabricated correspondent would defeat the purpose of this exercise.

Inventors

Pattern assessment — no adverse inventor-departure signal. All three inventors assigned to the employer at filing (execution dates 2002-10-21 to 2002-10-31, recorded 2002-11-07). Critically, Marco Racanelli did not leave within 12 months — he stayed with Jazz through the 2008 Tower acquisition and is today President of Tower Semiconductor Ltd. and CEO of Newport Fab LLC / Jazz Semiconductor, Inc. A 20-plus-year inventor tenure is the opposite of the "inventors bail before a fire-sale" tell. No evidence of a mass inventor exodus precedes any transfer here.

Original assignee

Newport Fab, LLC dba Jazz Semiconductor (Newport Beach, California) — the entity named on the issued patent.

• Primary line of business: A 200 mm specialty silicon foundry (Tower "Fab 3"). Its process portfolio centers on analog/mixed-signal, RF CMOS, high-voltage/BCD, and — directly relevant here — SiGe BiCMOS and SiGe bipolar technologies (source: Jazz Technologies S-1 / Tower proxy materials). The claimed lateral PNP device is a process feature embedded in that BiCMOS offering, so the assignee plainly practices the claims in commerce rather than holding them as licensing paper.
• Provenance: Prior to March 2002 the Newport Beach fab was Conexant's; it was spun out as Newport Fab, LLC, funded by Conexant and Carlyle Group affiliates, and renamed Jazz Semiconductor, Inc. (Wikipedia / OC Register).
• Ownership history of the parent (not recorded against this patent): Jazz → Acquicor Technology (blank-check co. founded by ex-Apple execs Amelio, Hancock, Wozniak) on 2007-02-16 → renamed Jazz Technologies → acquired by Tower Semiconductor Ltd. (Israel) via stock-for-stock merger, closed 2008-09-22.
• Current status: Operating. Newport Fab, LLC dba Jazz Semiconductor is a wholly owned U.S. subsidiary of Tower Semiconductor Ltd. (Nasdaq/NYSE-listed through acquisitions; Intel's 2022–2023 acquisition attempt was abandoned). Still an active wafer fab in Newport Beach, CA.

Key structural observation: The 2008 Tower merger was a parent-level stock-for-stock deal. Newport Fab, LLC survived as the same legal entity that owns the patent, which is why no change-of-ownership assignment was ever recorded against US 6,867,477 — and why the 2023 release still names "Newport Fab, LLC dba Jazz Semiconductor Operating Company."

Assignment timeline

Four recorded events exist. Only one is a true ownership assignment; two are collateral liens and one is a lien release.

• 2002-10-21 → 2002-10-31 (executed) / recorded 2002-11-07 — Reel 013487/0872

  • Conveyance: Assignment (Assignment of Interest)
  • Assignor: Jie Zheng; Peihua Ye; Marco Racanelli (individually)
  • Assignee: Newport Fab, LLC dba Jazz Semiconductor (Newport Beach, CA)
  • Correspondent: Not determinable from the sources available; the Google Patents legal-events entry records only the conveyance text and reel/frame, not the filing correspondent. Cannot be verified — not inferred.
  • Context: Standard employment invention assignment at filing. This is the only true ownership transfer in the entire chain.

• 2006-01-06 (effective) / recorded 2006-01-20 — Reel 017223/0083

  • Conveyance: Security Agreement
  • Assignor: Newport Fab, LLC
  • Assignee: Wachovia Capital Finance Corporation (Western) (Los Angeles, CA)
  • Correspondent: Not surfaced in available records (party names only: "NEWPORT FAB, LLC" / "WACHOVIA CAPITAL FINANCE CORPORATION (WESTERN)").
  • Context: Securitization / collateral lien — blanket security interest granted over Newport Fab's IP portfolio to secure a credit facility. Not an ownership change. (The identical reel 017223/0083 and counterpart 017586/0081 appear on sibling Newport Fab patent US 6,797,580, confirming this was a portfolio-wide lien, not a targeted patent-specific filing.)

• 2006-01-06 (effective) / recorded 2006-01-23 — Reel 017586/0081

  • Conveyance: Security Agreement (second, parallel lien filing)
  • Assignor: Newport Fab, LLC
  • Assignee: Wachovia Capital Finance Corporation (Western)
  • Correspondent: Not surfaced in available records.
  • Context: Securitization / collateral lien — companion filing to 017223/0083 (same effective date, same parties), part of the same financing package.

• 2023-09-29 (effective) / recorded 2023-10-18 — Reel 065284/0123

  • Conveyance: Release by Secured Party
  • Assignor (releasing party): Wells Fargo Capital Finance, LLC, as successor by merger to Wachovia Capital Finance Corporation (Western)
  • Assignee / owner named: Newport Fab, LLC dba Jazz Semiconductor Operating Company (California)
  • Correspondent: Not surfaced in available records.
  • Context: Lien release after payoff — the 2006 security interest is extinguished; ownership remains with the operating foundry. This is the last recorded event, 17 years after the lien and ~1 year after patent expiry. (Same recordation appears on US 6,797,580.)

Bottom line: There are no post-issuance ownership assignments to any third party. The chain never leaves Newport Fab, LLC. The assignee never became an "IP Holdings/Licensing/Ventures" entity.

Timeline diagram

timeline
    title Ownership of US 6867477
    2002 : Filed 2002-11-07 by Newport Fab LLC
         : Inventors assign to Jazz Semiconductor
    2005 : Patent issued 2005-03-15
    2006 : Security agreement to Wachovia
         : Second security agreement recorded
    2023 : Wachovia successor releases lien

NPE / troll-pattern signals

Verdict

Operating-company assertion — with the important caveat that no assertion is of record.

Justification: US 6,867,477 never left its original operating owner. The single true assignment (Reel 013487/0872, 2002-11-07) ran from the three inventors to Newport Fab, LLC dba Jazz Semiconductor, an active 200 mm SiGe BiCMOS foundry that practices the claimed lateral PNP device in its commercial process flows. The only subsequent recordations are collateral lien filings to Wachovia (Reels 017223/0083 and 017586/0081, effective 2006-01-06) and the release of those liens by Wells Fargo as successor (Reel 065284/0123, effective 2023-09-29) — classic securitization, not an NPE handoff. The 2007 Acquicor and 2008 Tower Semiconductor transactions were parent-level corporate mergers that left Newport Fab, LLC as the same legal owner of record, which is precisely why no change-of-ownership assignment was ever filed.

Every NPE/troll signal scores not present (with the lone unclear being the unretrievable correspondent field, a data gap rather than evidence). The patent expired on 2022-11-07 and is unenforceable, so it cannot be asserted by anyone going forward. If a stricter reading is applied — that the "Operating-company assertion" bucket requires an actual suit — then this patent is best described as operating-company ownership, non-asserted; in neither reading is it an NPE asset.

Verify at: https://assignmentcenter.uspto.gov/ (search patent number 6867477) · https://assignment.uspto.gov/patent/index.html

Caveats / data gaps (stated rather than filled)

• Correspondent names are missing from every retrievable source; the USPTO Assignment Center record would supply them if queried directly. No conclusion about repeat-player counsel is possible.
• I found no litigation naming this patent, but I did not exhaustively query PACER/Docket Navigator before the tool budget closed; absence of a found suit is not proof that none exists.
• The 2007/2008 merger lineage is supported by SEC proxy/S-1 filings and press coverage (OC Register, Tower IR), not by a recorded patent assignment — consistent with no change of the record owner.

I'll research US patent 6867477 and its cited prior art references.

Let me research the remaining cited references in detail.

Prior Art Analysis — US 6867477 B2

1. Patent Under Review

Independent claims (the only ones a §102 reference can anticipate):

• Claim 1 — a bipolar transistor comprising: a base with a top surface; an emitter with a top surface, situated on the base's top surface; an electron barrier layer situated directly on the emitter top surface in an opening defined by a plurality of emitter contact layers and the emitter top surface, the electron barrier layer causing the base current in the base to decrease; wherein the emitter separates the electron barrier layer from the base.
• Claim 9 — a PNP bipolar transistor comprising: a base with a top surface; an emitter with a top surface, situated on the base's top surface; a floating N+ region situated directly on the emitter top surface in an opening defined by a plurality of emitter contact layers and the emitter top surface, the floating N+ region causing the base current in the base to decrease.

All 15 claims depend from one of these two. The claim-1/claim-9 nexus is the structurally located diffusion barrier immediately atop the emitter (dielectric electron-barrier layer, or a floating N+ region), not merely a generic emitter/base/collector stack.

2. Identification Method / Caveat

Searches were run against Google Patents (which surfaces the USPTO/Espacenet bibliographic data) and Espacenet for the exact number 6867477. No results for adjacent numbers were substituted. The reference list below is taken from the "Patent Citations (6)" table of US 6867477 B2 itself — every one of the six is marked * = "cited by examiner."

Important interpretive caveat: all six references were before the examiner, and the patent nonetheless issued with all 15 claims intact. Therefore none of them actually anticipated claims 1–15 in the USPTO's view. The §102 mapping below is a potential mapping — i.e., what a challenger might argue — and in each case the reference is more realistically §103/background material. I flag this explicitly per reference rather than asserting anticipation the record contradicts.

3. Examiner-Cited References (the prior art of record)

4. Per-Reference Analysis

Reference 1 — US 5,510,647 A (Toshiba)

• Full citation: Kabushiki Kaisha Toshiba, "Semiconductor device and method of manufacturing the same," US 5,510,647 A; appl. 08/213,027; priority 1993-03-15; granted 1996-04-23. (Same family as EP 0 381 139 / EP 0 589 675 filings by Toshiba, inventors Momose, Maeda, Makita.)
• Brief description: Discloses a BiCMOS-style structure combining a PMOS device in an n-well (with a p-type emitter region 11 / p-type source 3 and n-type emitter 10 inside a p-type layer 201) with a vertical bipolar transistor. The work is directed to integration/isolation of bipolar and MOS devices in one substrate and to forming emitters/sources by shared implants — precisely the "compatibility with an NPN/MOS process flow" background identified in US 6,867,477 at col. 1.
• Potential §102 relevance: Very weak. It describes emitter regions formed by shared CMOS implants, which touches the process-compatibility motivation of US 6,867,477, but it does not disclose an electron barrier layer directly on the emitter top surface (claim 1) nor a floating N+ region on the emitter (claim 9). At most it is §102(b)/§103 background art for the "use PMOS source/drain implants to define the PNP emitter/collector" concept mentioned in the specification. It does not anticipate any of claims 1–15.

Reference 2 — US 5,654,211 A (Samsung)

• Full citation: Samsung Electronics Co., Ltd., "Method for manufacturing ultra-high speed bipolar transistor," US 5,654,211 A; priority 1995-06-15; granted 1997-08-05.
• Brief description: Self-aligned vertical NPN process. A double-layered sidewall (polysilicon + insulator) defines an aperture; a shallow polysilicon film at the aperture bottom is thermally oxidized to form the intrinsic base; the extrinsic base is diffused from the polysilicon sidewall. The stated object is to reduce collector–base junction capacitance and base width to raise f_T. Critically, the reference teaches an insulator (oxide/nitride) under the base polysilicon layer so that base dopant does not diffuse through it.
• Potential §102 relevance: Weak / context only. It is a vertical NPN device, not a lateral PNP, and the insulator it discloses sits under the polysilicon base electrode — not "directly on the emitter top surface." Its relevance is as a teaching that a thin dielectric can be interposed between a polysilicon electrode and underlying silicon (analogous to the thin-oxide/polysilicon approach condemned as costly in the US 6,867,477 background). A §103 combination argument (this reference + a lateral PNP) is conceivable, but it does not anticipate claims 1–15, and certainly not the "opening defined by a plurality of emitter contact layers" limitation.

Reference 3 — US 5,698,890 A (NEC) — the most structurally relevant citation

• Full citation: NEC Corporation (inventor Fumihiko Sato), "Semiconductor device having bipolar transistor free from leakage current across thin base region," US 5,698,890 A; appl. 08/526,893; JP priority 217351/94 (1994-09-12); granted 1997-12-16. (Family: EP 0 701 287 A3, same applicant/inventor/title.)
• Brief description: A bipolar transistor with a base structure formed in a hollow space on a single-crystal silicon collector region defined by a silicon-oxide layer. The base structure comprises a single-crystal SiGe intrinsic base layer that decreases in thickness from a central portion toward the outer periphery, surrounded by an extrinsic base, with a single-crystal silicon emitter region contacting the central portion of the intrinsic base to form a p-n junction. A base electrode (p-type polysilicon) overhangs the hole, and the emitter is formed in a "narrow hole" defined by an oxide sidewall.
• Why it is the closest: It contains (i) a SiGe base/emitter heterostructure, (ii) an insulating (silicon-oxide) layer that spatially defines an opening over the active region, and (iii) a sidewall-defined narrow hole over the base through which the emitter is placed. SiGe and oxide-spacer/opening architecture are the two structural ingredients the examiner was evidently tracking.
• Potential §102 relevance: Does not anticipate. It is a vertical NPN with the base in a hollow defined by oxide, and it places the emitter inside/under a narrow hole rather than placing a barrier layer on top of the emitter. Claim 1 requires the emitter to separate the barrier layer from the base — the inverse vertical ordering (barrier above emitter, emitter above base) — and NEC '890 instead has oxide beside/around the active region. Best characterization: highly relevant §102/§103 background and the closest of the six structurally, but the claimed barrier-on-emitter top-surface element is absent.

Reference 4 — US 5,786,622 A (TriTech Microelectronics)

• Full citation: TriTech Microelectronics International Ltd. (inventor Hannu O. Ronkainen), "Bipolar transistor with a ring emitter," US 5,786,622 A; appl. 08/857,959; filed 1997-05-16; granted 1998-07-28.
• Brief description: BiCMOS-compatible NPN with a ring-shaped emitter whose outer perimeter is set by a field-oxide opening and whose inner perimeter is set by an opening in a doped polysilicon layer over the intrinsic base. An oxide sidewall spacer along the polysilicon opening creates a transition band between intrinsic and extrinsic base; a central extrinsic-base contact sits inside the ring. Emitter is diffused from the polysilicon. Improves f_T by ≥20% with only one added mask.
• Potential §102 relevance: Weak. Its claims (1, 11) are directed to an emitter-base structure with ring geometry and sidewall spacers. It does disclose a polysilicon layer contacting/overlying the emitter region and a dielectric sidewall/spacer — i.e., an opening through insulating/poly layers over the emitter — which is the nearest thing in the set to the "opening defined by a plurality of emitter contact layers" language of claims 1 and 9. But there is no layer on top of the emitter that reduces base current by suppressing electron diffusion, so the essence of claims 1 and 9 is not disclosed. It is relevant as §103 art on how contact-layer openings over emitters are conventionally formed.

Reference 5 — US 5,789,800 A (NEC)

• Full citation: NEC Corporation, "Bipolar transistor having an improved epitaxial base region," US 5,789,800 A; priority 1996-01-17; granted 1998-08-04.
• Brief description (from title/bibliographic data only — the full text was not retrieved within the search budget): Directed to a bipolar transistor with an improved epitaxial base region architecture, in the same NEC vertical-bipolar design family as US 5,698,890.
• Potential §102 relevance: Honest limitation: I could not verify the disclosure text of this reference at high confidence, so I will not fabricate a specific §102 mapping. Based on its title and assignee, it belongs to the same vertical-NPN, epitaxial-base line as Reference 3 and is properly treated as general background art on base-region engineering, not as anticipating the barrier-on-emitter subject matter of claims 1–15.
• (Flagged: this is the one reference for which I lack full-text grounding; I am explicitly marking it as unverified rather than inventing an anticipation theory.)

Reference 6 — US 6,255,716 B1 (Samsung)

• Full citation: Samsung Electronics Co., Ltd., "Bipolar junction transistors having base electrode extensions," US 6,255,716 B1; priority 1997-05-28; granted 2001-07-03.
• Brief description (title/bibliographic grounding): A BJT in which the base electrode includes lateral/self-aligned base-electrode extensions so that the base region and emitter region are self-aligned to the electrode extension, reducing lateral device dimensions and reliance on critical photolithographic masking steps. (A closely related Samsung filing, US 6,287,930 B1, "Methods of forming bipolar junction transistors having trench-based base electrodes," describes the analogous family using a base electrode overlying a surface of the substrate with a lateral extension and an insulating layer between the base electrode and the intrinsic collector.)
• Potential §102 relevance: Weak / §103 at most. Its subject is base electrode geometry and self-alignment for vertical NPNs, not a diffusion barrier on the emitter of a lateral PNP. It shares no element with claim 1's "electron barrier layer situated directly on the emitter top surface" or claim 9's "floating N+ region." Does not anticipate any claim.

5. Summary Judgment on §102

Bottom line: The prior art of record for US 6,867,477 consists of six examiner-cited references, of which the NEC '890 patent (US 5,698,890) is the most structurally relevant because it combines SiGe heterostructure with an oxide-defined opening and a sidewall-defined emitter aperture. None of the six discloses the claimed point of novelty — an electron-barrier dielectric layer (claim 1) or a floating N+ region (claim 9) situated directly on the emitter's top surface, within an opening defined by the emitter contact layers, with the emitter separating the barrier from the base, so that base current is reduced. That absence is consistent with the patent having issued over all six. A stricter anticipation challenge would therefore need to locate a different reference, not any of these; these six are best used in an obviousness (§103) or motivating-background posture.

Sources

• US 6,867,477 B2 (Google Patents): https://patents.google.com/patent/US6867477/en — citation table ("Patent Citations (6)") and claims 1–15.
• US 5,510,647 A: https://patents.google.com/patent/[US5510647A](/patent/US5510647A)/en
• US 5,654,211 A: https://patents.google.com/patent/US5654211 ; http://www.everypatent.com/comp/pat5654211.html
• US 5,698,890 A: https://patents.google.com/patent/[US5698890A](/patent/US5698890A)/en ; https://worldwide.espacenet.com/publicationDetails/biblio?CC=US&NR=[5698890A](/patent/5698890A) ; (family EP 0 701 287 A3)
• US 5,786,622 A: https://patents.google.com/patent/US5786622 ; http://www.everypatent.com/comp/pat5786622.html
• US 6,255,716 B1 (title/bibliographic): as listed in the US 6,867,477 citation table; related Samsung disclosure US 6,287,930 B1 at https://patentimages.storage.googleapis.com/f8/e4/ca/f7b148ffb0378b/US6287930.pdf

Note on dates/IDs: all patent numbers, application numbers, and dates above are reproduced literally from the sources; the "priority date" and "legal status" entries are, per Google Patents' own disclaimer, assumptions and not legal conclusions.

I'll research the cited prior-art references to ground the obviousness analysis in their actual disclosures.

Obviousness Analysis Under 35 U.S.C. § 103

U.S. Patent No. 6,867,477 B2 — "High Gain Bipolar Transistor"

0. Scope, Sources, and Confidence Notes

The patent under analysis (source: https://patents.google.com/patent/[US6867477](/patent/US6867477)/en):

"The Prior Art section of this page" = the six documents listed under Patent Citations (6) (all marked cited by examiner). These are the only references used below:

1. US 5,510,647 A — Kabushiki Kaisha Toshiba — Semiconductor device and method of manufacturing the same (prior art 1993-03-15; granted 1996-04-23)
2. US 5,698,890 A — NEC Corp. — Semiconductor device having bipolar transistor free from leakage current across thin base region (1994-09-12; 1997-12-16)
3. US 5,654,211 A — Samsung Electronics — Method for manufacturing ultra-high speed bipolar transistor (1995-06-15; 1997-08-05)
4. US 5,789,800 A — NEC Corp. — Bipolar transistor having an improved epitaxial base region (1996-01-17; 1998-08-04)
5. US 5,786,622 A — Tritech Microelectronics Int'l — Bipolar transistor with a ring emitter (1997-05-16; 1998-07-28)
6. US 6,255,716 B1 — Samsung Electronics — Bipolar junction transistors having base electrode extensions (1997-05-28; 2001-07-03)

Confidence flags (strict-honesty rule):

• I retrieved full text/abstract/claims for references 2, 3, 4, and 5, and partial text for reference 1. These mappings are grounded.
• I was unable to retrieve the disclosure of US 6,255,716 B1 (search tooling limit). I therefore treat it as available art for the class of "doped polysilicon electrode/extension structures" but do not attribute any specific teaching to it. Any analysis relying on it should be re-verified.
• Documents under "Cited By," "Similar Documents," and "Applications Claiming Priority" (e.g., US 2006/0043528 A1, WO 2022/231884 A1, US 12,166,077 B2) post-date the 2002-11-07 priority date or share the same family and are not prior art. They are excluded.
• The patent expired 2022-11-07; this analysis is therefore retrospective (e.g., for damages/validity reconstruction), not a live-invalidity exercise.

1. The Claims at Issue

Claim 1 (independent) — a bipolar transistor comprising:
(a) a base having a top surface;
(b) an emitter having a top surface, the emitter situated on the base's top surface;
(c) an electron barrier layer situated directly on the emitter top surface in an opening defined by a plurality of emitter contact layers and the emitter top surface, the barrier layer causing base current to decrease;
(d) wherein the emitter separates the electron barrier layer from the base.

Claim 9 (independent) — a PNP bipolar transistor comprising elements (a) and (b) above, plus:
(c′) a floating N+ region situated directly on the emitter top surface in an opening defined by a plurality of emitter contact layers and the emitter top surface, the floating N+ region causing base current to decrease.

Dependents: 2–8 and 10–15 add: PNP / lateral PNP; barrier = dielectric / silicon oxide; barrier increases beta; base = N-type single-crystal silicon; emitter = P+ single-crystal SiGe; floating region = N+ polysilicon; floating region increases beta; dielectric spacer adjacent the floating N+ region in contact with the emitter top surface (claim 15).

Critical observation: Claims 1 and 9 are apparatus claims with no process-step limitation. The specification's own stated advantage — that the barrier "may be fabricated using existing BiCMOS process steps" and "does not require additional process steps and additional fabrication cost" — is not recited. This matters substantially below.

2. Governing Standard

Under Graham v. John Deere Co., 383 U.S. 1 (1966), and KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007), a claim is obvious if the differences between the claim and the prior art are such that the subject matter as a whole would have been obvious to a person of ordinary skill at the time of filing. Recurring KSR rationales applicable here:

• (A) Combining known elements according to known methods to yield predictable results;
• (B) Simple substitution of one known element for another to obtain predictable results;
• (C) Use of a known technique to improve similar devices in the same way;
• (D) Applying a known technique to a known device ready for improvement.

The six references are all analogous art: they are in the same field of endeavor (bipolar/BiCMOS semiconductor device design and fabrication) and are reasonably pertinent to the problem of emitter/contact engineering.

3. Level of Ordinary Skill in the Art (POSITA) — 2002-11-07

A POSITA would hold a B.S./M.S. in electrical engineering, applied physics, or materials science, plus ~2–5 years of experience in bipolar/BiCMOS device design and process integration. Such a person would be familiar with: SiGe HBTs; lateral PNPs used in BiCMOS analog blocks; polysilicon-emitter technology and the "poly-emitter effect" (an interfacial oxide/doped-polysilicon layer reduces minority-carrier back-injection and raises hFE/beta); silicide emitter contacts; sidewall/dielectric spacers; and the trade-off between beta and process cost.

4. What Each Reference Discloses

Key gap in the record: None of the six references discloses a lateral PNP transistor, and none is directed to the problem of lateral-PNP beta. The lateral-PNP architecture is supplied by the patent's own Background (FIG. 1 "conventional lateral PNP transistor 102," with base 110 of N-type single-crystal silicon, P+ SiGe emitter 112, and P-type collectors 114/116), which is applicant-admitted prior art.

5. Applicant-Admitted Prior Art in the Specification — The Central § 103 Hook

The Background section admits that the following was already known:

"One approach utilized to increase the gain of a lateral PNP transistor … is to fabricate a thin oxide layer over emitter 112 and then fabricate a polysilicon layer between the thin oxide layer and silicide layer 108. The thin oxide layer functions as an electron barrier that causes an increase in electron concentration at the interface between emitter 112 and the thin oxide layer, which results in a decrease in the steepness of the electron concentration gradient … As a result, base current decreases, which causes the gain … to increase. However, the above approach results in an undesirable increase in process steps and fabrication cost…"

This admission establishes, on the face of the patent, that as of 2002 a POSITA knew:

• to place an electron-barrier dielectric directly on a lateral-PNP emitter;
• that doing so reduces base current and raises beta — i.e., exactly the functional limitation of claims 1, 6, 9, and 12.

The inventor's stated distinction is purely process-economics ("additional process steps and fabrication cost"). Because claims 1 and 9 recite no process limitation, this admission alone supplies the invention's core technical feature, and the remaining structural language ("in an opening defined by a plurality of emitter contact layers and said top surface of said emitter") is the only arguably new geometry.

6. Proposed Obviousness Combinations

Combination 1 — Claims 1–8 (electron barrier layer)

Primary: US 5,786,622 A (Tritech) in view of US 5,789,800 A (NEC), further in view of the applicant-admitted prior art of the '477 Background.

Rationale and element mapping:

Combination 2 — Claims 9–15 (floating N+ region)

Primary: US 5,786,622 A or US 5,654,211 A in view of US 5,789,800 A, in further view of US 5,698,890 A, plus the admitted prior-art control approach.

Rationale and element mapping:

Combination 3 — Alternative for claims 1–8

US 5,510,647 A (Toshiba) in view of US 5,786,622 A and/or US 5,789,800 A. Toshiba '647 supplies dielectric-film/doped-polysilicon emitter-fabrication context; '622/'800 supply the emitter-contact-opening and dielectric-spacer geometry. This combination is the weakest of the three because I could not fully verify '647's disclosure; it should not be relied upon without re-verification.

7. Motivation to Combine (Why a POSITA Would Have Done So)

1. Same field, same problem. All references address bipolar-transistor emitter/base/contact engineering in a BiCMOS-compatible process. '622 expressly identifies the same design goal as the '477 patent: improving bipolar performance while minimizing added CMOS process steps ("with minimal alterations of the CMOS processing technology").
2. Known technique applied to a known device ready for improvement (KSR rationale D; In re Keller, 642 F.2d 413 (CCPA 1981)). The '477 Background itself states that applying an electron barrier to a lateral-PNP emitter was a known, working technique — its only drawback was cost. A POSITA seeking lateral-PNP beta would predictably look to it.
3. Reasonable expectation of success. Both the admitted prior art and the patent's own results section report the same predictable outcome (base current lower by ≈5×; beta ≈20–50 vs. ≈10). Nothing in the references teaches away from placing a barrier layer on a PNP emitter.
4. Substitution of known equivalents (KSR rationale B). Dielectrics ('800: oxide/nitride; '890: oxide; '622: oxide) and doped polysilicon ('800, '211, '622) are interchangeable, art-recognized materials for forming a surface barrier/contact over an emitter. Swapping an undriven N+ polysilicon region for a thin oxide as the barrier is a substitution of one known element for another with predictable results.
5. Sidewall/dielectric spacers in contact openings were routine ('622 spacer 18; '211 spacers 151/152; '890 sidewall 11), supplying claim 15's "dielectric spacer … in contact with the top surface of the emitter."
6. Market/packaging pressure for BiCMOS integration. The '622 and '477 documents both express the same motivation to reuse existing CMOS/BiCMOS steps, supplying a KSR "design incentive/market pressure" rationale.

Net conclusion: Claims 1–8 are, on this record, reasonably likely obvious — principally because the patent's own Background admits the electron-barrier-on-emitter feature and its base-current-reducing effect, and because claims 1–8 recite no process limitation preserving the inventor's actual point of novelty. Claims 9–15 are more vulnerable than they look but less clearly obvious, because the "floating" (undriven) character of the N+ region is not expressly disclosed by any cited reference and must be reached by substitution reasoning.

8. Counterarguments (Non-Obviousness Positions the Patent Owner Could Advance)

1. No reference discloses a lateral PNP. All six references are directed to vertical NPN devices or general BiCMOS structures. The lateral-PNP context appears only in the patent's own Background. An examiner relying solely on the six cited references would face a gap on claims 3 and 10 unless the admitted prior art is used as a § 102(a)/§ 103 base.
2. The "opening defined by a plurality of emitter contact layers and said top surface of said emitter" is a specific geometry that no cited reference squarely shows. In '622 and '800, the dielectric/opening is a contact aperture to the top of the emitter, not a gap flanked by emitter contact layers resting on field oxide with the barrier floor being the emitter's own top surface. This is the patent's narrowest structural point.
3. "Floating" is a functional/structural negative (undriven) with no express antecedent in the record. The owner can argue the cited art's polysilicon regions are all driven (emitter/base/collector electrodes), and that nothing suggests removing the electrode while retaining the region.
4. Teaching away / differing solutions. Each reference solves a different problem (leakage across a thin base; ring-emitter resistance; Cjc/Cje reduction; base-electrode extension; epitaxial base quality). None frames its solution in terms of minority-carrier back-injection in a PNP emitter, which supports a "different problem / no reason to modify" argument.
5. Secondary considerations. The record shows commercial adoption (the '477 patent is cited by later Newport Fab/Jazz Semiconductor and third-party lateral-PNP patents). If the owner can tie that to the specific claimed structure (as opposed to the general practice of BiCMOS integration), it could rebut a prima facie case — though nexus would be the battleground.

9. Claim-by-Claim Disposition (Summary)

Bottom line. On the four corners of this page's Prior Art section, the strongest § 103 case is built on the patent's own Background admission (electron barrier on a lateral-PNP emitter reducing base current), combined with US 5,786,622 and US 5,789,800 for the emitter-contact-opening and dielectric-spacer geometry. The weakest link is the "floating" limitation of claim 9 and the "opening defined by emitter contact layers" geometry of claim 1, neither of which is squarely disclosed by any one reference. US 5,510,647 and US 6,255,716 B1 should not be relied upon in any final, citable analysis until their disclosures are independently verified — I retrieved only partial text for '647 and none for '716.