US 6829728

I'll run targeted searches for this exact patent number, including any 2026 CAFC activity.

Let me try a couple more specific searches for USPTO records and any litigation/PTAB activity on this exact number.

US 6,829,728 — Confirmed Record

Bottom line: I found no CAFC 2026 docket activity, no PTAB proceeding, and no district-court litigation involving the exact number 6,829,728. I also found no evidence it was ever asserted in litigation. Two cautions on that finding are below.

1. Bibliographic data (from the USPTO record as mirrored on Google Patents / Justia)

Note the PCT application (WO 2002/039460) was filed 2001-11-09 — after the 2001-03-05 US filing, so the US filing is not itself a §371 national stage.

2. Abstract (verbatim from the patent)

"A test circuit is disclosed for testing embedded synchronous memories. A BIST controller is used to address the memory and provide reference data that is compared to the memory output. Pipeline registers are used to allow the BIST controller to perform reads and/or writes during every clock cycle. In one aspect, the BIST controller includes a reference data circuit that stores or generates data for comparison to the memory output. A pipeline register is positioned before the reference data circuit or between the reference data circuit and compare circuitry. Additional pipeline registers may be positioned between a compare capture circuit and the compare circuitry. The pipeline registers free the BIST controller from having to wait for a read to complete before starting the next read or write. To reduce the number of pipeline registers needed, a negative-edge BIST controller can be used with a positive-edge memory or vice versa."

3. Plain-language overview of each independent claim

Claim 1 — Circuit. A circuit for testing embedded synchronous memory, having four elements: (i) a memory with address, data-in, and data-out ports; (ii) a BIST controller coupled to it (a BIST address port wired to the memory address port, a BIST data port wired to the memory data port, and a finite state machine controlling the controller's state); (iii) compare circuitry coupled to the memory's output port; and (iv) at least one pipeline register coupled between the compare circuitry and the finite state machine that delays data going to the compare circuitry. The pipeline register is the core point of novelty.

Claim 16 — Method. A memory-testing method with five steps: generate an expected data value; pipeline that expected value so it is delayed by at least one clock cycle; deliver test data (expressly separate from control data and address data) to the memory; read back the actual data value; and compare the actual value to the pipelined expected value using compare circuitry.

Claim 23 — Circuit. A test circuit comprising pipelined registers between a finite state machine and compare circuitry, arranged so the circuit can read from memory on consecutive clock cycles, compare the read data to an expected value during the same clock cycle as the reads, and output results of consecutive reads on every clock cycle.

Claim 24 — Method (pipelined read/write sequence). Step-by-step: (a) cycle 1 — set up the address register for a first read; (b) cycle 2 — complete the first read and compare the data read to an expected value; (c) cycle 2 — set up the address register for a second read or a write; (d) cycle 3 — output a pass/fail indication for the first read; (e) cycle 3 — complete the second read or the write. In effect: a three-stage pipeline where setup, execution, and result-output of different operations overlap.

Claim 31 — Method (full BIST test flow). (a) Put the IC selectively into test mode; (b) BIST loads the address of the location under test; (c) BIST generates the expected data value; (d) BIST provides control signals to — or loads — a compare capture circuit that controls the compare circuitry; (e) read the actual data value from that address; (f) compare actual vs. expected; and (g) pipeline at least the compare capture circuit so the BIST controller can perform consecutive reads and compares every memory clock cycle.

Claim 39 — Circuit (opposite-edge variant). Same four elements as claim 1, but with the additional limitation that the BIST controller loads on one edge of a clock cycle and the memory performs an action (read or write) on the other edge — i.e., the half-cycle offset that lets the single pipeline register of the FIG. 8 embodiment suffice.

4. Search findings on USPTO / CAFC 2026 dockets

• CAFC 2026 dockets: No hit. I reviewed Gibson Dunn's March 2026 Federal Circuit update, the CAFC September 2026 argument calendar, and Patterson Sheridan's weekly Federal Circuit summaries for Jan/May/Jul 2026 — the number 6,829,728 does not appear. Given the patent expired 2022-07-29, meaningful 2026 appellate activity is unlikely, but I cannot rule out an unindexed or very recent docket.
• USPTO / PTAB: No IPR, PGR, or CBM involving 6,829,728 surfaced. Note the searches did surface a different Mentor Graphics-owned patent (US 6,947,882, "Regionally time multiplexed emulation system") in IPR2012-00041, and several Synopsys v. Mentor Graphics appeals (e.g., 814 F.3d 1309) — those are unrelated to 6,829,728 and I am not conflating them with it.
• Litigation/assertion: No evidence this patent was ever asserted in district court.

Two caveats on the "no results" conclusion:

1. I could not open USPTO PatentCenter directly. The bibliographic data above comes from the authoritative Google Patents full text supplied to me (which mirrors the USPTO record) plus a Justia mirror. For a definitive litigation/docket check, PAIR/PatentCenter, Docket Navigator, or a PACER/CAFC docket search would be needed.
2. Beware a same-number collision in a different jurisdiction. My search returned JP 6829728 B2 (特許第6829728号), assigned to Lesaffre et Compagnie, directed to a method for customizing the flavor of bread or pastry. That is an entirely different patent in a different country and has nothing to do with US 6,829,728 — I flag it only so the number match is not mistaken for a family member.

5. Drafting anomalies worth noting (reported literally, not corrected)

The claim set contains apparent antecedent-basis/dependency inconsistencies that I am not auto-correcting, per instruction:

• Claim 32 recites "The circuit of claim 16 further comprising…," but claim 16 is a method claim.
• Claims 40 and 41 recite "The method of claim 39," but claim 39 is a circuit claim.
• Claim 14 recites a "reference data circuit" although claim 14 depends from claim 1, which does not itself introduce a reference data circuit (that element appears in claim 2).

These are on the face of the granted claims and may bear on any invalidity or construction analysis, but they are outside the scope of a summary.

Confidence: High on bibliographic data, abstract, and claim text (drawn from the authoritative full patent text). Low-to-moderate on the negative litigation finding, given I could not query PatentCenter/PACER directly.

I'll search for litigation involving US patent 6829728 across patent litigation databases.

Let me search additional litigation-specific sources.

Summary of Findings: US Patent No. 6,829,728

No litigation involving U.S. Patent No. 6,829,728 has been identified. Based on searches of patent litigation resources (including the Unified Patents litigation portal, PACER-adjacent sources, Federal Circuit materials, Google Patents' "Cited By"/litigation data, and Justia), I could not locate any civil action, ITC proceeding, or Federal Circuit appeal in which US 6,829,728 was asserted as an infringed patent, challenged for validity, or otherwise a subject of the court's judgment.

I want to be explicit about the limits of this conclusion: absence of results is not affirmative proof that no suit ever existed. District court complaints that settled quickly or were dismissed early can be poorly indexed, and I was not able to run a direct Docket Navigator / Lex Machina / Docket Alarm query on the patent number. The statement above reflects what the searchable record shows.

Confirmed patent identity (to guard against number confusion)

The alphanumeric ID 6,829,728 as a U.S. patent is:

Source: https://patents.google.com/patent/US6829728/en

Why no litigation is unsurprising

1. The patent expired in 2022. Per the Google Patents legal-status record, the adjusted expiration is 2022-07-29, and the status is "Expired – Lifetime." Expired patents cannot support prospective injunctive relief, which sharply reduces their value as litigation assets. Note that §286's six-year damages lookback would still permit suit for past infringement in principle, but no such case appears in the record.

2. It was a design-tool vendor patent, not an NPE patent. The patent is held through Mentor Graphics → Siemens Industry Software Inc., consistent with a defensive/prosecution portfolio rather than an assertion portfolio. I did find litigation in the same corporate family (e.g., Mentor Graphics Corp. v. EVE-USA, Inc., D. Or. Nos. 3:10-cv-00954-MO, 3:12-cv-01500-MO, 3:13-cv-00579-MO, involving Synopsys and the '376, '882, '531, '176, '962, '526, and '109 patents; and Mentor Graphics Corp. v. Quickturn Design Systems, Inc.), but 6,829,728 was not among the patents asserted in any of those cases — the asserted patents were different numbers, and I am not inferring them into this case.

3. Primary use appears to be as prior art / citation, not as an asserted patent. The patent shows up in the patent literature as a reference — e.g., it is cited in EP 1 858 028 (Dialog Semiconductor, "Memory test engine") and in JP 5047496 B2. Those are citation relationships, not litigation.

Explicit non-matches (same numeral, different subject matter — NOT this patent)

To comply with the instruction to interpret identifiers literally and not auto-correct, I flag these distinct "6829728" items that are not US Patent 6,829,728 and should not be conflated with it:

• JP Patent No. 6829728 — a Japanese patent to Lesaffre et Compagnie (bread/pastry flavoring method), issued 2021-02-10.
• Canadian buoy notice MPO(6829728-01) — a Notices to Mariners chart correction reference (publications.gc.ca).
• A Pakistani bar council phone number ("0309-6829728").
• U.S. application number 6829728 references in unrelated contexts.

None of these relate to US 6,829,728 or to any litigation.

Bottom line

• Plaintiff(s): None identified.
• Defendant(s): None identified.
• Jurisdiction: N/A.
• Case number: N/A.
• Filing date: N/A.
• Outcome/status: N/A — no litigation involving US 6,829,728 was located.

If the requester needs certainty beyond an open-web search (e.g., to satisfy a diligence or freedom-to-operate requirement), I recommend running a direct query against Lex Machina, Docket Navigator, or Unified Patents' litigation portal on the exact patent number, and also checking the USPTO Patent Center / Assignment record and PACER for the patentee entity (Mentor Graphics / Siemens Industry Software). Those subscription databases index settlements and early dismissals that open-web searches miss. I cannot guarantee that this open-web search captured every case.

I'll verify the ODP default against live sources before concluding.

Let me run a couple more targeted checks before concluding.

PTAB / AIA Trial Analysis — U.S. Patent No. 6,829,728

Patent: Full-speed BIST controller for testing embedded synchronous memories
Application: 09/800,092 · Filed: 2001-03-05 · Priority: 2000-11-13 (Prov. 60/248,337) · Granted: 2004-12-07 · Claims: 41
Original assignee: individual inventors (Cheng, Hill, Kebichi) → Mentor Graphics Corp. (2001-06-11) → Siemens Industry Software Inc. (merger, 2021-06-29)
Legal status (per Google Patents / USPTO): Expired – Lifetime; adjusted expiration 2022-07-29

Proceedings overview

Total AIA trial proceedings on file: zero (0). Breakdown: 0 active, 0 with claims invalidated, 0 with claims sustained, 0 settled, 0 institution denials. The USPTO Open Data Portal returns no IPR, PGR, or CBM proceeding for US 6,829,728, and targeted web searches of PTAB materials (PTAB E2E, PTAB Decisions, Docket Alarm, CourtListener-derived sources) surfaced nothing to contradict that as of 2026-09-27.

Defensive posture for a defendant today: This is not a "hardened by IPR" patent and not a "claims canceled, troll has no case" patent — it is a clean, never-challenged-at-the-PTAB patent that has already expired (2022-07-29). Because no IPR was ever filed, there is no claim-level PTAB record to lean on: all 41 claims stand as issued, un-adjudicated by the Board, and no estoppel attaches (§ 315(e)(2) estoppel only arises from a proceeding that reached final written decision). Your practical leverage is therefore not an IPR record — it is (a) the expiration date, which caps damages and eliminates any injunctive theory, and (b) district-court invalidity/non-infringement, unconstrained by any PTAB history.

Caveat on methodology: absence of a PTAB proceeding is a negative finding. I confirmed it against the ODP structured data and multiple targeted searches, but I cannot exhaustively rule out a very recently filed, unindexed petition at a granularity finer than that. Treat this as "no proceeding on file" — the default stated in the task — rather than a certified null result.

Proceedings

None. There are no proceedings to report, so no proceeding-by-proceeding entries (type, panel, grounds, institution decision, FWD, settlement, appeal) can be generated. I will not manufacture proceeding numbers, panel names, or dispositions for this patent. Any such entry would be fabricated.

For the record, what I did find in searching, and why it is not relevant:

• Search hits for "IPR" + "6829728" returned other patents' PTAB papers (e.g., IPR2014-01197 on U.S. Pat. 6,425,035; IPR2017-01586/Advanced Bionics; IPR2021-01229/PQA v. VLSI; IPR2017-00587 on U.S. Pat. 8,671,243). None involve U.S. 6,829,728.
• The numeric string "6829728" also collides with an unrelated Japanese patent (JP 6829728 B2, a Lesaffre bakery-flavor method) and a Canadian chart-notice identifier. These are false positives, not this patent.
• Mentor Graphics / Siemens has been a PTAB party on other patents (e.g., Synopsys, Inc. v. Mentor Graphics Corp., Fed. Cir. 2016, on U.S. Pat. 6,240,376 — an unrelated EDA patent). That is ownership context only; it tells you nothing about 6,829,728's PTAB history.

Strategic summary

Claim status. All claims 1–41 remain as issued and untested at the PTAB. Because no FWD was ever issued, no claim is CANCELED; none is "SUSTAINED" in the sense of having been adjudicated valid (a PTAB survival is a different, stronger signal than never having been challenged). The claim set is a mix of independent apparatus claims (1, 23, 39), independent method claims (16, 24, 31), and dependents reciting pipeline-register placement, compare-capture pipelining, negative-edge memory/controller configurations (claims 12–13, 28–29), and a reference-data selector (claims 14–15). All of these are open; none has been construed by the Board; none has been narrowed by a PTAB or Federal Circuit validity holding.

Estoppel landscape. § 315(e)(2) is inapplicable — no petitioner, no privity chain, no FWD. That is a benefit, not a burden: every prior-art ground remains available to you, including art that would be cumulative or that a first petitioner raised (because no one raised anything). You are not riding an earlier petitioner's coattails, and you also gain nothing from an earlier petitioner's work — there is no PTAB record to borrow, no expert declaration to reuse, and no Board claim construction to cite. You will litigate validity from scratch (or file first).

Pattern signals. No repeat petitioner, no serial IPR campaign, no defensive aggregator (no Unified Patents, RPX, or similar entity appears in this patent's chain), and no patent-owner appeal activity — because there was never a proceeding to appeal. The absence is itself informative in one specific way: this patent was held by Mentor Graphics/Siemens, a large EDA operating company, not a PAE, and it was never asserted in the litigation record I could find. Well-asserted assertion-grade patents tend to attract IPRs; a patent that expires without ever drawing one usually was never a monetization target. That history is consistent with (though not proof of) an uneventful, portfolio-maintenance lifecycle.

Timing reality. The patent's adjusted expiration is 2022-07-29 (per the Google Patents/USPTO record, "Expired – Lifetime"). Any assertion today is a past-damages-only theory, subject to the 35 U.S.C. § 286 six-year lookback, and cannot support an injunction or ongoing royalty for post-expiration conduct. That is a far more potent defense posture than any IPR outcome — but note it is a damages argument, not an invalidity one, and it does not resolve whether pre-2022-07-29 conduct infringed.

Recommended next steps

1. Assume there is no PTAB shortcut, and don't build a defense deck around a nonexistent FWD. There is no Final Written Decision to link to for this patent. If you need to cite the null result, point to the USPTO's own record — PTAB E2E and the PTAB Decisions databases — and the Google Patents page for US 6,829,728, which shows no AIA trial data.

2. Lead with the expiration date (2022-07-29). Confirm it against the USPTO Patent Center / Patent Public Search record and pin down whether any terminal disclaimer or PTA changed it — this is the single most valuable fact for a current defendant and it defeats injunctive exposure outright.

3. If you are in court and want to open a PTAB front, check the § 315(b) clock. You have one year from service of a complaint alleging infringement to petition. Filing an IPR against an expired patent is legally permissible but strategically odd: the patent can no longer be amended, so a Patent Owner will defend the issued claims as-is. Weigh that against the new (2025) discretionary-denial landscape — under the current Director-controlled institution regime and the "settled expectations"/age factors discussed in Willkie's October 2025 analysis and the PTAB 2025 year-in-review, a 24-year-old patent may face heightened denial risk. If you file, treat institution as non-guaranteed.

4. Watch the sibling patent. Continuation U.S. 7,721,174 B2 (app. 10/985,539, filed 2004-11-09, also "Expired – Lifetime," same inventors/assignee chain) covers overlapping subject matter. My searches surfaced no PTAB proceeding there either, but I did not canvass it exhaustively — if the assertion letter references the '174, run the same ODP/PTAB check for both members of the family before responding. A prior-art ground invalidating one will frequently reach the other given the shared specification.

5. If you find a proceeding I could not, verify it against the source before relying on it: pull the case from PTAB E2E by patent number, confirm the FWD's claim-by-claim disposition verbatim, and check the CAFC docket on CourtListener for any appeal. Do not repeat a proceeding number from a secondary aggregator without confirming it — the "6829728" string has demonstrable false-positive collisions (see the Japanese patent above).

I'll start by cross-checking the assignment records against the source data I already have.

The searches didn't surface reel/frame data. Let me try more targeted queries on the assignment databases and the corporate history.

Let me attempt to pull the actual reel/frame records directly from the assignment databases.

Assignment & Ownership Analysis — US 6829728 B2

Patent: Full-speed BIST controller for testing embedded synchronous memories
App. No.: 09/800,092 · Filed: 2001-03-05 · Granted: 2004-12-07 · Priority: 2000-11-13 (Prov. 60/248,337)
Source of record used: Google Patents legal-events feed for the patent (https://patents.google.com/patent/US6829728/en) plus corroborating public corporate-history sources.

Data-quality caveat, stated up front: USPTO's Assignment Center (https://assignmentcenter.uspto.gov/) and the legacy index (https://assignment.uspto.gov/patent/index.html) are session- and interface-gated, and I was not able to pull the underlying reel/frame records or the named correspondent for this patent in this run. I therefore report the two recorded conveyances by date and party (corroborated by the patent's own legal-events record) and mark reel/frame and correspondent as not retrieved. I have not guessed them. Every other statement below is grounded in the patent text or the cited public sources.

Inventors

• Inventor residency data above is per the published listing (Trustoria mirror of the issued patent: https://trustoria.com/~Omar-Kebichi/4-1).
• Employer determination: All three executed an assignment of their interest to Mentor Graphics Corporation, recorded 2001-06-11 — i.e., within roughly three months of the 2001-03-05 filing. An assignment this soon after filing is the ordinary signature of an employment invention-assignment obligation, and it is the strongest available indicator that all three were Mentor personnel at filing.
• Unusual patterns: None observed. There is no evidence any inventor left the assignee within 12 months of filing, and no evidence of a pre-filing portfolio fire-sale. Cheng and Kebichi both remained associated with Mentor/Siemens EDA for years afterward (Cheng in particular is a long-tenured, prolific Mentor/Siemens DFT inventor). I found no "departing-inventor" signal — but note this is inference from absence of contrary data, not a positive verification of employment records.
• The application was filed naming the individual inventors as applicants (Google Patents legal event: "2001-03-05 Application filed by Individual"), with the corporate assignment following on 2001-06-11. That is routine sequencing, not an anomaly.

Original assignee

• Entity on the issued patent: The operative record names Mentor Graphics Corporation (assignment recorded 2001-06-11). Google Patents' "Original Assignee: Individual" field is a bibliographic artifact of the inventors being the initial applicants; it does not mean the patent was sold to a third party.
• Primary line of business: Electronic design automation (EDA) — IC design, simulation, and design-for-test / silicon test tools and IP. Mentor was NASDAQ-listed (ticker MENT).
• Did they ship a product embodying the claims? Yes, in the relevant sense: this patent is core to Mentor's MemoryBIST product family, later branded Tessent MemoryBIST (Mentor's Tessent line was formed by combining Mentor ATPG with the BIST technology Mentor acquired via LogicVision; see https://prod.chipestimate.com/Mentor-Graphics-Outlines-Strategy-to-Unify-Silicon-1257159600/Mentor/news/1910). The at-speed, pipelined BIST-controller subject matter of claims 1, 16, 23, 24, 31 and 39 is squarely the MemoryBIST architecture. Whether current Tessent releases literally read on these claims is unverified (and now moot — the patent expired).
• Current status: Acquired, then renamed — still operating. Siemens AG acquired Mentor Graphics in 2017 for ~$4.5B; the business operated as "Mentor, a Siemens business" and was renamed Siemens EDA effective January 2021, operating under Siemens Digital Industries Software (https://design-reuse-embedded.com/news/202012115; https://semiiphub.com/news/mentor-siemens-eda). No bankruptcy, dissolution, or assignment-for-the-benefit-of-creditors appears anywhere in the chain.

Assignment timeline

Two recorded conveyances in ~20 years. Reel/frame and correspondent not retrieved (see caveat above).

• 2001 (executed date not retrieved) / recorded 2001-06-11 — Reel/frame: not retrieved

  • Conveyance: Assignment (Assignment of Assignors' Interest)
  • Assignor: Wu-Tung Cheng; Christopher John Hill; Omar Kebichi (each individually)
  • Assignee: Mentor Graphics Corporation
  • Correspondent: not retrieved — cannot assess recurrence; signal unassessable in this run
  • Context: Original employee invention assignment; prosecution-phase transfer of title from the individual applicants to their employer.

• 2021 (executed 2021, exact date not retrieved) / recorded 2021-06-29 — Reel/frame: not retrieved

  • Conveyance: Merger and Change of Name
  • Assignor: Mentor Graphics Corporation
  • Assignee: Siemens Industry Software Inc.
  • Correspondent: not retrieved
  • Context: Internal corporate reorganization. Follows Siemens' 2017 acquisition of Mentor Graphics and the January 2021 Mentor → Siemens EDA renaming; the record captures the surviving legal entity's name change and/or upstream merger, not a third-party sale. The patent's current-assignee field reads "Siemens Industry Software Inc."

Related family member to check for a parallel chain: continuation US 10/985,539 → US 7721174 B2 (filed 2004-11-09, granted 2010-05-18) sits in the same family and should carry an identical two-link chain; PCT WO2002039460A2 and AU2002228873A1 are the foreign counterparts.

Timeline diagram

timeline
    title Ownership of US 6829728
    2000 : Provisional application filed
    2001 : Nonprovisional 09 800092 filed
         : Assigned to Mentor Graphics Corp
    2004 : Patent granted as US6829728B2
    2017 : Siemens acquires Mentor Graphics
    2021 : Recorded merger and name change to Siemens Industry Software Inc
    2022 : Patent expires

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. Both recorded assignees are operating entities: Mentor Graphics Corporation (NASDAQ-listed EDA vendor) and Siemens Industry Software Inc. (Siemens AG subsidiary). No "IP / Holdings / Licensing / Ventures" suffix, no registered-agent service address, no single-purpose LLC anywhere in the chain.
2. Known asserter in the chain — Not present. Neither Mentor Graphics nor Siemens Industry Software appears on the Acacia / Marathon / IV / IPNav / Wi-LAN / Conversant / Vringo / Pendrell / Round Rock / Spangenberg lists described in the brief. Siemens EDA is a practicing EDA/IP vendor, not a licensing plaintiff on this record.
3. Repeat correspondent across the chain — Unclear / unassessable. The correspondent of record was not retrievable in this run, so I cannot state whether one attorney or firm filed both the 2001-06-11 and 2021-06-29 recordings, nor cross-check the name against Unified Patents / RPX assertion lists. This is a genuine gap, not a negative finding.
4. Cascading transfers — Not present. Two conveyances across ~20 years, with the second being an intra-group reorganization. No chained LLCs, no <24-month cascade, no shared correspondent address evident.
5. Pre-litigation transfer — Not present / unclear. No infringement suit naming US 6829728 was surfaced, and none is referenced in the record. No 6-month-before-suit assignment is evidenced.
6. Bankruptcy fire-sale — Not present. Siemens acquired Mentor Graphics as a going concern in 2017; no Chapter 7/11, no USPTO sale order, no auction in the chain.
7. Privateering — Not present. No evidence Siemens conveyed the patent to a litigation vehicle to assert on its behalf. Ownership stayed inside the Siemens corporate family.
8. Defensive aggregator (anti-NPE) — Not present. The chain does not terminate at RPX, AST, LOT Network, Unified Patents, or OIN; it terminates at Siemens Industry Software Inc.

Net: zero affirmative NPE indicators; the two soft spots are (a) the unretrieved correspondent and (b) the unretrieved reel/frame numbers — both data-retrieval gaps, not evidence of an NPE structure.

Verdict

Operating-company assertion — with an explicit caveat.

The chain runs inventors → Mentor Graphics Corporation (recorded 2001-06-11) → Siemens Industry Software Inc. (recorded 2021-06-29, merger and change of name), i.e., a single operating company and its post-acquisition corporate successor, with no licensing-vehicle hop and no aggregator. Mentor/Siemens is the vendor whose MemoryBIST → Tessent MemoryBIST line is the direct commercial embodiment of the claimed full-speed pipelined BIST controller, so the current assignee is a practicing operating company rather than an NPE. Caveat: the "assertion" prong cannot be verified — I found no Siemens/Tessent litigation on this patent, and the patent already expired (adjusted expiration 2022-07-29), so the record is best characterized as a clean, non-litigious operating-company ownership chain rather than an active assertion campaign. The enumerated verdict taxonomy has no dedicated "operating company / non-asserting" bucket; this is the closest fit and the one I select.

Verification links:

• USPTO Assignment Center: https://assignmentcenter.uspto.gov/ (search patent number 6829728)
• USPTO Assignment legacy index: https://assignment.uspto.gov/patent/index.html
• Google Patents legal events: https://patents.google.com/patent/US6829728/en

Two items I could not verify and will not fabricate: the reel/frame numbers for either recording and the named correspondent on either recording. If you can supply the reel/frame pair (or a screenshot of the Assignment Center result), I can complete signal #3 and lock the citations precisely.

I'll verify several of the cited references against external sources before building the anticipation analysis.

Prior-Art Analysis for US 6,829,728 B2

Scope / method note

I searched for the literal identifier 6829728 and confirmed the record against the authoritative full text of US 6,829,728 B2 (https://patents.google.com/patent/US6829728/en). USPTO PatentCenter was not directly reachable in this session, so I grounded the reference list on the patent's own "Patent Citations (18)" table and, where possible, verified each reference's content/dates against individual Google Patents / FreePatentsOnline records. No US patent other than 6,829,728 B2 carries that number; the earlier-flagged JP 6829728 B2 (Lesaffre et Cie) is an unrelated grant and is not a family member.

Critical dates carried forward from the prior section: earliest priority 2000-11-13 (provisional US 60/248,337); actual US filing 2001-03-05; grant 2004-12-07; legal status Expired – Lifetime (adjusted expiration 2022-07-29).

Pre-AIA § 102 posture. Because the priority date precedes 2013-03-16, the pre-AIA statute governs. Applying it literally:

• § 102(b) art = published/patented more than one year before the priority date, i.e. before 1999-11-13.
• § 102(e) art = a US patent granted on an application filed before the applicant's date (here, filed before 2000-11-13), even if it published after.
• § 102(a)/(g) may also apply to intervening publications.

I assign each reference a statutory category below. Note one important structural point that shapes the whole analysis: the baseline BIST architecture (memory + BIST controller with FSM + address/data/control registers + reference-data register + compare-capture register + compare circuitry) is already shown in the patent's own FIG. 2 prior art. Therefore, for the independent claims (1, 16, 23, 24, 31, 39), the only genuinely distinguishing element over the generic BIST art is the pipeline register / pipelined architecture that lets reads and/or writes and the compare occur on consecutive clock cycles. Most of the 18 references therefore map onto the non-distinguishing elements; I flag where they touch the distinguishing element.

Master table — the 18 patent citations of record

Claim map (the independent claims to be tested)

• Claim 1 (circuit): memory w/ address, data-in, data-out ports + BIST controller (BIST address port, BIST data port, FSM) + compare circuitry on the memory output + ≥1 pipeline register between the compare circuitry and the FSM that delays data to the compare circuitry.
• Claim 16 (method): generate expected value → pipeline it ≥1 clock → deliver test data (separate from control/address) → read actual → compare to the pipelined expected value.
• Claim 23 (circuit): pipelined registers between FSM and compare circuitry so reads occur on consecutive clock cycles, compare happens in the same cycle as the read, and results are output every clock cycle.
• Claim 24 (method): the explicit 3-stage overlap — cycle 1 set up read 1; cycle 2 complete read 1 + set up read 2/write; cycle 3 output pass/fail for read 1 + complete read 2/write.
• Claim 31 (method): test-mode entry → BIST loads address → BIST generates expected value → BIST loads/provides signals to a compare-capture circuit → read actual → compare → pipeline at least the compare-capture circuit to allow consecutive reads/compares every cycle.
• Claim 39 (circuit): as claim 1, but BIST loads on one clock edge and memory acts on the opposite edge.

Reference-by-reference § 102 assessment

Tier A — references that touch the distinguishing element (pipelining / operational-speed testing)

#5 — US 5,974,579 A, "Efficient built-in self test for embedded memories with differing address spaces" (Credence), filed 1996-09-03, granted 1999-10-26 — § 102(b).
This is the single most conceptually relevant citation. Its specification (confirmed at https://patents.google.com/patent/[US5974579A](/patent/US5974579A)) expressly discusses the same problem statement as the '728 patent: serial-load BIST "reduces the maximum operational frequency … faults that appear only at normal speed operation, such as capacitive coupling faults and transition faults, are not detected." It then discloses routing read data back through multiplexers so that "data is always available for writing when a read operation is completed, the memory may be tested at operational speeds."

• Potentially relevant to: claim 1 (structure), claim 16 (operational-speed compare), claim 23, claim 24 (overlapped read/write), claim 31.
• § 102 caveat (material): the disclosed mechanism is adjacent-bit multiplexer feedback / full-width data routing, not a pipeline register that delays data to the compare circuitry. Read data is "routed back to the finite state machine BIST controller for comparison." That is a different architecture from the claimed pipeline register. On the record available this reference is best characterized as § 103 art (a strong starting point for the "test at speed" motivation), not a clean § 102 anticipation of the pipeline limitation in claims 1/23/39, and likely not of claim 16's "pipelining the generated expected data value to delay it at least one clock cycle."

#4 — US 6,085,346 A (Credence), filed 1996-09-03, granted 2000-07-04 — § 102(e).
Same background/disclosure as #5 (the two Credence filings share near-identical text — confirmed at https://patentimages.storage.googleapis.com/27/a2/7f/48bc0b31ba9013/US6085346.pdf). Identical analysis and identical caveat: full-speed testing via data routing, not a compare-delay pipeline register. Because it was filed before 2000-11-13 it qualifies as § 102(e) art.

#12 — US 6,006,347 A, "Test mode features for synchronous pipelined memories" (Cypress), filed 1997-09-17, granted 1999-12-21 — § 102(e).
Confirmed at https://patents.google.com/patent/US6006347. This reference discloses a synchronous pipelined SRAM with an address register 202, input register 216, output register, and clocked output pipeline registers, plus programmable scan/test modes (e.g., disabling the clocked output register to observe the core, programmable delay paths, external clock substitution). It is the clearest "pipeline registers in a synchronous memory" teaching among the citations.

• Potentially relevant to: claim 1 only to the extent the "pipeline register" element is construed broadly to cover a memory-side output register; claim 39 (synchronous clocking structure); the general "synchronous" preamble of all claims.
• § 102 caveat: the pipeline register here is inside the memory under test as part of normal/scan architecture, not "coupled between the compare circuitry and the finite state machine." It does not disclose a BIST compare pipeline. So it does not anticipate claims 1, 16, 23, 24, 31, or 39 as a whole; it is at most § 103 material for the "use pipeline registers to break the read timing path" concept.

#6 — US 6,011,748 A (Credence; Lepejian), filed 1997-08-21 (prov. 1996-10-03), granted 2000-01-04 — § 102(e).
Confirmed at https://www.freepatentsonline.com/[6011748](/patent/6011748).html. Discloses a BIST semiconductor device with means for comparing data written into each memory cell to data read out, independent row and column address generators clocked by separate clock signals, and selectively simultaneous/differing row/column clocking ("improves transition time between rows"). The independent row/column clocking is a timing-efficiency teaching adjacent to the '728 pipelining idea.

• Potentially relevant to: claim 39's "one edge / other edge" clocking concept (§ 103), and the general address/compare architecture of claim 1.
• § 102 caveat: no pipeline register delaying data to compare circuitry; no consecutive-cycle read pipeline. Not an anticipation of any independent claim.

#11 — US 6,182,257 B1, "BIST memory test system" (Mosaid), filed 1997-07-31, granted 2001-01-30 — § 102(e).
Confirmed at https://patents.google.com/patent/US6182257. Discloses an embedded-DRAM BIST with an input data pattern generator, address counter, expected-data pattern generator, comparison circuit, state machine control, voltage-bump test, and redundancy/repair, citing US 5,173,906 ("Built-In Self Test for Integrated Circuits") as the baseline architecture (pattern generator + address counter + expected-data generator + comparator + state machine).

• Potentially relevant to: claim 1's first three elements (memory ports + BIST controller with these registers + compare circuitry) — essentially the FIG. 2 baseline. Claim 16 to the extent it discloses generating expected data, delivering test data, reading actual data, and comparing.
• § 102 caveat: no pipeline register/pipelining; the read/compare still completes over the conventional multi-cycle sequence. Not an anticipation of claims 1, 16, 23, 24, 31, or 39 as recited.

Tier B — generic BIST-architecture references (map to the FIG. 2 baseline elements)

#1 — US 5,617,531 A (Motorola; Crouch), 1993-11-02 / 1997-04-01 — § 102(b).
A data processor with an internal self-test controller for testing a plurality of internal memories. Discloses a BIST controller (address/data/control) internally coupled to embedded memories with a comparator — again the FIG. 2 baseline.

• Potentially relevant to: claim 1's structural elements; claim 24's "setting up an address register for a read" and "completing the read" steps in isolation.
• § 102 caveat: no pipeline register delaying data to the compare circuitry; reads are not pipelined on consecutive cycles. Not an anticipation alone.

#7 — US 5,961,653 A, "Processor based BIST for an embedded memory" (IBM), 1997-02-19 / 1999-10-05 — § 102(b).
BIST driven by an embedded processor. Relevant to the Background discussion in the '728 patent (the "embedded CPU" alternative) rather than to the claimed pipeline. Not an anticipation of any independent claim.

#3 — US 6,000,048 A (Cirrus Logic), 1996-08-14 / 1999-12-07 — § 102(e).
Combined logic and memory circuit with built-in memory test; multiplexer switching between functional logic and BIST (corresponding to mux 72 / control 74 of the '728 FIG. 4). Potentially relevant to: claim 1 preamble / claim 31 step (a) (selectively configuring the IC into test mode). No pipeline teaching → not an anticipation.

#13 — US 5,995,731 A, "Multiple BIST controllers for testing multiple embedded memory arrays" (Motorola; Crouch), 1997-12-29 / 1999-11-30 — § 102(e).
Multiple BIST controllers; relevant to the '728 statement that "typically, a BIST controller tests multiple memories." Potentially relevant to: none of the pipeline limitations. Not an anticipation.

#10 — US 6,070,256 A, "Method and apparatus for self-testing multi-port RAMs" (Nortel), 1997-05-29 / 2000-05-30 — § 102(e).
Self-test of multi-port RAMs. Background/structural relevance only; no compare-pipeline. Not an anticipation.

#14 — US 6,108,252 A (Samsung), filed 1998-02-06, granted 2000-08-22 — § 102(e).
Confirmed at https://patents.google.com/patent/US6108252. Discloses a memory with a BIST portion comprising a BIST information-signal generator (outputs input data + a control signal to the memory via a switch MUX), an address generator, and a comparator that compares input data to data output from the memory to generate a fail signal; the BIST compares "data DRIN to be written … with data DROUT output," and a clock MUX supplies an external clock in BIST mode.

• Potentially relevant to: claim 1 (memory + controller + FSM-controlled state + comparator), claim 16 (generate expected, deliver test data, read actual, compare), claim 31 steps (b)–(f).
• § 102 caveat: no pipeline register / consecutive-cycle compare; the patent's own background characterization (three-cycle read) applies. Not an anticipation of the pipeline limitations.

#15 — EP 1 031 994 A1 (TSMC), 1999-02-23 / 2000-08-30 — § 102(a).
"Built-in self-test circuit for memory." Generic BIST circuit; same baseline mapping as #14. Not an anticipation.

Tier C — test-interface, pattern-generation, and self-repair references

#2 — US 5,673,271 A, "High speed pattern generator" (Advantest), 1994-08-19 / 1997-09-30 — § 102(b).
High-speed test-pattern generation for ATE. Relevant only to the '728 patent's admitted background that external ATE (FIG. 1) cannot test at operational speed. Not an anticipation of any claim; potentially § 103 background for the "test at speed" motivation.

#8 — US 5,968,192 A (Artisan Components), 1997-05-09 / 1999-10-19 — § 102(b) and #9 — US 6,044,481 A (Artisan Components), 1997-05-09 / 2000-03-28 — § 102(e).
A programmable universal test interface and its variant for "different test methodologies." These support the '728 proposition that BIST controllers are configurable/programmable; they do not disclose pipelining. Not an anticipation.

#16 — US 6,560,740 B1 (AMD), filed 1999-08-03, granted 2003-05-06 — § 102(e).
Programmable BIST and self-repair of embedded memory. Relevant to claims 14/15-adjacent repair themes (redundancy) only; the '728 claims are directed to pipelining, not repair. Not an anticipation.

#17 — US 6,587,979 B1 (Credence), filed 1999-10-18, granted 2003-07-01 — § 102(e).
Partitionable embedded-circuit test system (published as US 2003/0167427 A1, confirmed at https://patentimages.storage.googleapis.com/ed/cc/87/d7e5442a6cca72/US20030167427A1.pdf). Discloses partitioning BIST functions between on-chip and off-chip components, and a BIST controller supplying data/address/control to embedded RAMs. Potentially relevant to: the general architecture of claim 1 and claim 31 step (d) (compare-capture/provision of signals to compare circuitry). No compare-pipeline. Not an anticipation.

#18 — US 6,643,807 B1 (IBM), filed 2000-08-01, granted 2003-11-04 — § 102(e).
Array-BIST (ABIST) for efficient, fast bitmapping of large embedded arrays. This is the closest reference in the list on the "fast/full-speed ABIST" theme, but its disclosure is directed to bitmapping/diagnostic resolution, not to overlapping setup/read/compare stages via pipeline registers. Potentially relevant to: claim 23's efficiency objective; not an anticipation of the pipeline-register limitations.

Bottom line on the citations

1. No single one of the 18 cited references appears, on the record available, to anticipate any independent claim (1, 16, 23, 24, 31, or 39) in full. The reason is uniform: the references disclose the baseline BIST architecture already shown in the '728 patent's own FIG. 2 prior art (memory + FSM-driven BIST controller + address/data/control registers + reference data + compare-capture + comparator), but they do not disclose a pipeline register coupled between the compare circuitry and the finite state machine that delays data to the compare circuitry (claim 1/39's distinguishing limitation; the core of claims 16, 23, 31). That element is what distinguishes the '728 claims, consistent with the patent having issued over these references.

2. The most relevant prior art, ranked:

• (1) US 5,974,579 A (Credence) — same problem statement (undetected at-speed faults; operational-speed testing,) and a read/write overlap scheme; best § 103 starting point for the "test at full speed" motivation, but uses multiplexer data-routing, not a compare pipeline.
• (2) US 6,085,346 A (Credence) — same family/spec as the above; § 102(e) counterpart.
• (3) US 6,006,347 A (Cypress) — express teaching of pipeline registers in a synchronous memory plus test modes; the strongest reference on the pipeline concept, but the registers live inside the memory, not between BIST compare circuitry and an FSM.
• (4) US 6,108,252 A (Samsung) and US 6,182,257 B1 (Mosaid) — most complete generic BIST-controller-plus-comparator architectures; map to claim 1's non-distinguishing elements and to claim 16's/claim 31's basic steps.

1. § 103 reality check. Given that the pipeline limitation is absent from all 18 references individually, the realistic invalidity risk (if this patent were still enforceable — it is not, having expired 2022-07-29) would run through obviousness, e.g., combining a baseline BIST reference (#11, #14) with a pipelined-synchronous-memory teaching (#12) under the at-speed-testing motivation supplied by #5/#4/#2.

The four non-patent citations (also of record)

These are not in the "Patent Citations" table but are listed as Non-Patent Citations and are analytically important because they bear directly on the pipeline concept — and because of their dates:

Date significance: the three Mentor Graphics documents are dated December 2000 — after the 2000-11-13 priority date (though before the 2001-03-05 actual filing). If the '728 claims receive benefit of provisional 60/248,337, these December-2000 documents would not be § 102(b) art and would not be § 102(e) art (they are not US patent applications), so their citation value is as evidence of the state of the art / what a skilled artisan knew about "adding pipeline registers" to a memory BIST controller — i.e., § 103 context, not § 102 anticipation. The March 2000 Burgess article is likewise before the priority date and is § 102(a)/(b)-type background if treated as a printed publication. Notably, the fact that the applicant's own assignee's tool documentation discusses "Adding Pipeline Registers" is a point that a challenger could mine for an obviousness/on-sale or derivation argument.

Caveats and open items

• Source limitation: my per-reference § 102 assessment rests on the patent's own citation table, the abstracts/claim text/specification excerpts I retrieved (URLs above), and the references' titles/assignees/dates. I could not open the complete specification and all claims of each cited reference in this session; a definitive element-by-element anticipation chart would require the full text of each of the 18 references against each of the 41 claims (especially dependent claims 2–15, 17–22, 25–30, 32–41).
• Literal-number discipline applied: all identifiers were read literally; I did not substitute or "correct" any number. The US 6,82 9,728 vs. JP 6829728 vs. US 6,947,882 (Mentor Graphics, IPR2012-00041) distinctions from the prior section stand and are not conflated here.
• Legal status: the patent is Expired – Lifetime as of 2022-07-29, so the practical relevance of this anticipatory analysis is retrospective/historical and for the continuation US 7,721,174 B2 (same family, not prior art to itself).
• Antecedent-basis anomalies flagged earlier (claim 32 recites "circuit of claim 16"; claims 40/41 recite "method of claim 39"; claim 14's "reference data circuit") remain on the face of the claims and would matter to any claim-construction/invalidity exercise, but they do not change the prior-art mapping above.

I'll verify the disclosure content of the key cited references before mapping them to the claims.

§ 103 Obviousness Analysis — US 6,829,728

Grounding note: this analysis is built on the prior-art record presented on the Google Patents page for US 6,829,728 (https://patents.google.com/patent/US6829728/en) — i.e., the 18 "Patent Citations," the 4 "Non-Patent Citations," and the applicant's own admitted background art (FIG. 2). It builds on, and does not repeat, the claim-construction and family mapping in the two earlier sections. Where I retrieved a reference's actual disclosure, I cite it; where I am relying on a title/abstract only, I say so and hedge.

1. Governing law and framing

• Statute. The application was filed 2001‑03‑05 with priority to provisional 60/248,337 (2000‑11‑13). Both dates precede 2013‑03‑16, so pre‑AIA 35 U.S.C. § 103(a) governs, and pre‑AIA § 102(a)/(b)/(e) governs reference qualification.
• Standard. Graham v. John Deere, 383 U.S. 1 (1966) (scope/content of art; differences; PHOSITA level; secondary considerations), as refined by KSR Int'l v. Teleflex, 550 U.S. 398 (2007). Under KSR, an explicit teaching‑suggestion‑motivation is not required where the combination is "of familiar elements according to known methods," "a predictable variation," a use of a "known technique to improve similar devices in the same way," or reflects "design incentives and other market pressures." In re Keller / In re Merck permit combining references as a whole for what they fairly suggest. The Federal Circuit requires only a "reasonably supported" rationale, not a perfect one.
• PHOSITA. As of Nov. 2000: a B.S. in EE/CS (or equivalent) with 2–5 years in embedded‑memory design and DFT, including familiarity with memory BIST controllers, march/checkerboard algorithms, synchronous SRAM I/O register timing, and commercial MBIST insertion tools (e.g., Mentor's MBIST Architect, itself cited as NPL here).

Threshold issue the patentee will contest: the date of the most probative NPL. The Mentor Graphics Built‑in Self‑Test Process Guide, V8.9_1.10, "Adding Pipeline Registers," p. 3‑85/3‑86, is dated December 2000 — after the Nov. 13, 2000 provisional. It is therefore not § 102(b) art (needs to predate 2000‑03‑05) and is only § 102(a) art if it predates the actual invention date — which the applicant can presumptively swear behind via the provisional. Do not build the rejection on this NPL alone. However, it is powerful evidence of the state of the art and PHOSITA knowledge, and earlier editions of the same Mentor manual (1999 or earlier) would be clean § 102(b) art. The patent's own examiner cited the Dec. 2000 version, which strongly suggests earlier versions existed.

2. What actually distinguishes the claims (built on the prior section)

The applicant's admitted FIG. 2 art already discloses, verbatim in the specification: a BIST controller with an FSM and address/data/control registers; compare circuitry at the memory output; and a compare capture register gating the pass/fail output. The specification also concedes that register‑vs‑combinational‑logic substitution, and moving pipeline registers inside the BIST controller or compare circuitry, are "well understood in the art."

So the real delta is narrow:

Every one of these is a throughput/latency optimization over an admitted architecture. That posture is unfavorable under KSR.

3. Primary reference combinations

Ground A — Claim 1 (and 2–15): BIST controller + pipeline register in the compare path

Primary: US 6,182,257 (Mosaid, "BIST memory test system"). Discloses an embedded‑memory self‑test controller that internally generates test data patterns and expected resulting data, a comparison circuit comparing expected to actual, and a state machine controlling the sequence — i.e., every element of claim 1 except the pipeline register. (Verified: https://www.freepatentsonline.com/[6182257](/patent/6182257).html, http://www.everypatent.com/comp/pat6182257.html — note the number: 6,182,257, the Mosaid BIST patent; the similarly numbered US 6,181,257 is an unrelated utility‑meter transponder patent. Do not conflate.)

Secondary: US 5,673,271 (Advantest, "High speed pattern generator"). Expressly teaches that the address/pattern/expected‑value generation and compare path "is difficult to perform in one test cycle," so "a multiple staged pipeline structure is employed and preprocessing is performed," with the pipeline clocked by the system clock. (Verified: https://patents.google.com/patent/[US5673271A](/patent/US5673271A)/en.) This is the classic "known technique" — insert pipeline stages between a generator/sequencer and a comparator to keep pace with a fast device under test.

Secondary: US 6,643,807 (IBM, "ABIST … bitmapping of large embedded arrays in manufacturing test"). Discloses a BIST macro with a sequencer, address generator, data generator, control block, muxes, a read compare register that compares read‑back data to written data, and a diagnostic register capturing the compare output and failing address — and expressly states that "many faults occurring in today's technologies occur at speed," requiring on‑chip clock generation (PLL) to run BIST "at megahertz and gigahertz clock speeds to detect the AC faults." (Verified: https://patents.google.com/patent/[US6643807B1](/patent/US6643807B1)/en; https://patentimages.storage.googleapis.com/b7/3f/95/5fdff3ca616506/US6643807.pdf.)

Mapping: memory ports ← '257/'807; BIST address/data ports + FSM ← '257 (state machine) or Credence US 5,974,579 / Motorola US 5,615,531; compare circuitry at memory output ← '257, '807 (read compare register 255); pipeline register between FSM and compare ← '271 (multi‑stage pipeline) or '807 (compare register + diagnostic register forming a two‑stage capture pipeline).

Motivation / rationale (the key part):

1. Same field, same problem. All three address at‑speed testing of embedded memory and the read‑compare‑report critical path. KSR permits combination of references directed to the same problem.
2. Recognized deficiency. '807 expressly identified that conventional BIST "takes on the order of minutes to test each chip" and that tester bus‑speed limits make at‑speed AC‑fault detection impossible without on‑chip high‑speed clocking. The '728 specification states the identical problem ("three clock cycles … some timing faults may go undetected … overall testing time is extremely long").
3. Known solution, predictable result. Inserting a register in the compare/capture path to split a long combinational path and decouple the FSM from the comparator's completion is the textbook use of pipelining — exactly what '271 already did in a memory‑test generator. KSR: "the combination of familiar elements according to known methods is likely obvious when it does no more than yield predictable results." Here the predictable result is higher throughput at the cost of one cycle of latency and one word‑wide register — a trade‑off, and trade‑offs are design choices.
4. Reasonable expectation of success. '271 and '807 both confirm that pipeline registers can be clocked by the same system clock as the DUT, so no new clocking scheme or re‑verification burden was required.

Ground B — Claims 16–22 (method: pipelined expected data value)

Combination: US 6,182,257 (Mosaid) + US 6,560,740 (AMD, "Apparatus and method for programmable built‑in self‑test and self‑repair of embedded memory") + US 5,673,271 (Advantest).

• '257 supplies "generate an expected data value" and "compare."
• '560,740 (AMD) supplies the "test data separate from control data and address data" limitation: the master test unit generates the first and second sets of address and control signals while the BIST logic unit's background register stores the memory test pattern and "produce[s] the data input signals dependent upon the memory test pattern." (Verified: https://patents.google.com/patent/US6560740 and https://www.freepatentsonline.com/[6560740](/patent/6560740).html.) That is a clean disclosure of separately generated data vs. address vs. control.
• '271 supplies the one‑cycle pipeline delay of the expected value and the multi‑stage series pipeline (mapping claims 19 and 21 directly).

Motivation: aligning a delayed expected value with a delayed read result is the necessary consequence of pipelining the compare path (Ground A); '271's pipeline already delays pattern/expected data relative to the DUT's response, so the same delay is applied to the expected value for the same reason — to line up the two comparator inputs. Claim 21's "two pipeline registers positioned in series" is a shift‑register delay line, the most predictable of predictable variations.

Ground C — Claims 23–30 (consecutive cycles, results every cycle)

Combination: admitted FIG. 2 prior art + US 6,182,257 + US 6,643,807 + US 5,673,271.

Critically, the patent's own FIG. 3A depicts the prior‑art read as three discrete stages: (1) address/control set‑up, (2) memory output + compare, (3) compare‑capture‑controlled output of pass/fail. The invention, as the specification describes FIG. 5, is nothing more than overlapping those same three stages so that stage 3 of read N, stage 2 of read N+1, and stage 1 of read N+2 occur in the same cycle. That is the definition of pipelining, and '271 already implements exactly that structure ("the address operations are processed by dividing into multiple cycles … preprocessing is performed"). A PHOSITA would have every reason to overlap the admitted stages: the admitted prior art's own inefficiency (3 cycles/read, 2 cycles/write) is the stated problem, and the benefit (≈3× throughput) is precisely what pipelining predictably delivers. No new mechanism, no unexpected result.

Claim 24's step ordering (claim 37) is the mechanical consequence of that overlap. Claims 25/26 (repeat for N cycles; "arbitrary clock cycle") are obvious extensions with no added structure — the specification itself says the cycle "can continue indefinitely."

Ground D — Claim 31 (full flow with pipelined compare‑capture circuit)

Combination: admitted FIG. 2 (compare capture register 48) + US 6,643,807 (diagnostic register 251 capturing compare output and failing address) + US 5,673,271 / Mentor NPL.

Claim 31(g) adds only that the compare capture circuit is pipelined. The admitted prior art already has that circuit; '807 already pipelines a compare‑result capture register. Adding one delay stage to a capture register is a routine expedient — and the '728 specification says so itself, listing the two‑register (93/94) capture pipeline as an implementation detail, not an invention.

Ground E — Opposite‑edge clocking (claims 12, 13, 22, 28, 29, 39–41)

Combination: US 6,006,347 (Cypress, "Test mode features for synchronous pipelined memories") + US 6,182,257 + the admitted art.

'6347 discloses a synchronous pipelined SRAM with an address register, an input register clocked by a first internal clock (CCPULSE), and an output register clocked by a second internal clock (SACLK), plus a programmable delay circuit for altering internal signal timing so the device "may be characterized for timing margins." (Verified: https://patents.google.com/patent/US6006347; the full text is also mirrored at https://patents.justia.com/patent/[6006347](/patent/6006347).) It thus teaches, in the same field, (a) clocked register boundaries around a synchronous memory core and (b) deliberately skewing internal clock relationships for test/characterization.

Motivation: the patent itself states the reason — using a negative‑edge controller or memory "avoids any hold‑time violations" and lets one pipeline register be eliminated. That is a pure timing‑margin design choice made to fix a hold‑time failure, with the predictable benefit (one fewer word‑wide register) and predictable cost (a half‑cycle phase relationship to manage). Under KSR, "when a patent claims a structure … where the improvement is the predictable use of prior art elements according to their established functions," the claim is obvious. There is no teaching away in the record; the art uniformly tries to characterize and optimize timing margins via clock adjustment.

Ground F — Claims 14 and 15 (reference‑data selector / clocked selector as the pipeline register)

Combination: US 6,560,740 (AMD background register) + US 5,673,271 (Advantest data/expected‑value generation) + the patent's own admission.

Claim 14's mux‑selected constants are the standard way to realize march/checkerboard patterns: a small set of background patterns selected by a few control bits. '560,740's background register + pattern‑dependent data generation and Advantest's data/expected‑value generation sections together suggest selecting among stored patterns rather than storing a full word. Claim 15 (the selector doubles as the pipeline register) is a clocked mux/register — a conventional circuit element. The specification's own argument for it is area/cost trade‑off (reduce the delay register from 8 bits to 2, or 256 to 4). Cost‑motivated substitution of a smaller known element is a classic design choice; the Federal Circuit treats such trade‑offs as evidence of obviousness, not non‑obviousness, absent unexpected results.

4. Dependent claims — brief notes

• cl. 5 (delay = one clock cycle) — inherent to the disclosed scheme; also '271.
• cl. 6, 30 (shared clock for BIST and memory) — admitted in FIG. 2 ("a clock controls both the BIST controller and the memories"); '271 clocked everything off the timing generator.
• cl. 7, 11 (compare capture circuit controls compare; register between capture circuit and compare) — admitted FIG. 2 (register 48) + '807 (diagnostic register 251).
• cl. 8 (bit‑by‑bit compare + match output) — '257 and '807.
• cl. 9, 10 (consecutive reads / consecutive writes every cycle) — the stated object of the invention; obvious from admitted 3‑stage/2‑stage art + pipelining.
• cl. 14, 15 — see Ground F.
• cl. 20, 21 — see Ground B.
• cl. 27 — "pipelining data from a BIST controller that provides the expected data value to a compare circuit" — this is Ground A in one sentence.

5. Secondary considerations / anticipated rebuttals

• No unexpected results. The claimed benefit (≈3× throughput) is exactly the predicted throughput of a 3‑stage overlap; the patent even quantifies it as "nearly three times the speed," a predictable scaling of the admitted 3‑cycle read / 2‑cycle write. That math is an admission against non‑obviousness.
• No nexus evidence of record. I found no evidence (and the earlier sections found none) of asserted patents, licenses, or industry praise tied to the claimed pipeline‑register feature. The one notable commercial artifact — Mentor Graphics' own Built‑in Self‑Test Process Guide that already discusses "Adding Pipeline Registers" — cuts toward obviousness, not away.
• Area cost is a stated trade‑off. The specification repeatedly frames the pipeline register (word‑wide, e.g., 32 bits) as a cost to be traded against speed and mitigated by the FIG. 11 selector. Courts treat that as a design choice.
• Possible teaching‑away argument. The patentee may argue that the prior art taught waiting for compare completion before reloading the address/control registers (as FIG. 2/3A does). That is a disclosure of a working alternative, not a statement that pipelining "would not work" — insufficient for teaching away.
• § 112 anomalies from the earlier section (claim 32 recites "circuit of claim 16"; claims 40–41 recite "method of claim 39"; claim 14 lacks antecedent basis for "reference data circuit"). These affect how the claims are construed for a § 103 mapping — if the preamble controls, claims 32/40/41 inherit the wrong statutory class — but they do not supply patentable weight, and several of the dependents add no structural limitation beyond their parents.

6. Bottom line

The overall picture is one of narrow, throughput‑oriented improvements to an admitted BIST architecture, achieved by the textbook technique of pipelining — the paradigm KSR finds obvious. The claims most likely to survive are those with a specific, non‑generic structural hook (e.g., the exact partitioning of pipeline registers relative to the compare‑capture circuit, claim 21; and the opposite‑edge/one‑register arrangement of claim 39), and even those are vulnerable on predictable‑variation and design‑choice grounds.

Confidence: Moderate‑to‑high on the mapping and motivation for the combinations built on Mosaid '257, IBM '807, AMD '560,740, Advantest '271 and Cypress '6347 (I verified the disclosure substance of each). Lower for the Credence ('579, '346, '748), Artisan ('192, '481), Motorola ('531, '731), Cirrus '048, Nortel '256, Samsung '8252, TSMC EP 1031994, and AMD/IBM '979 references, where I worked from the citation titles and general knowledge only and did not retrieve column/line support. The single largest practical threat to this rejection is the date of the Mentor Graphics NPL — the applicant should be expected to swear behind the December 2000 manual, so a rejection should be anchored on the patents above, with the NPL used only as corroborating state‑of‑the‑art evidence (or an earlier edition of the same manual obtained as clean § 102(b) art).