US 6813742

Patent Summary: US 6,813,742 B2

Title: High speed turbo codes decoder for 3G using pipelined SISO log-map decoders architecture

Assignee: TurboCode LLC

Inventor: Quang Nguyen

Filing Date: January 2, 2001

Issue Date: November 2, 2004

Abstract:
A Baseband Processor for Wireless Communications is presented. The invention encompasses several improved Turbo codes method to provide a more practical and simpler method for implementation a Turbo Codes Decoder in ASIC or DSP coding. (1) A plurality of pipelined Log-MAP decoders are used for iterative decoding of received data. (2) In a pipeline mode, Decoder A decodes data from the De-interleaver RAM memory while the Decoder B decodes data from the De-interleaver RAM memory at the same time. (3) Log-MAP decoders are simpler to implement in ASIC with only Adder circuits, and are low-power consumption. (4) Pipelined Log-MAP decoders method provide high speed data throughput, one output per clock cycle.

Plain-Language Overview of Independent Claims:

Claim 1: Describes a baseband processor that uses at least two soft decision decoders connected in a circular loop. Each decoder processes the output from the previous one. The output of the last decoder is fed back to the first, creating an iterative processing loop for decoding digital signals. Each decoder is connected to a memory module to store its output before it's passed to the next.

Claim 6: Outlines a method for iteratively decoding received baseband signals. This method involves using a specific type of algorithm (maximum a posteriori (MAP) probability algorithm) to process both the main data and additional "extrinsic" information. The system generates and stores "soft decisions" (probabilistic estimates of the data) in memory. This process is repeated a set number of times, with the output of the last in a series of decoders being fed back to the first, and then sequentially through the others, to refine the decoding accuracy.

---

Recent Developments:

As of April 14, 2026, a third party, Unified Patents, LLC, filed an ex parte reexamination request for US Patent 6,813,742. The patent has been asserted in litigation against numerous companies in the technology and telecommunications sectors. A search of the CAFC 2026 dockets did not yield any specific results for this patent.

Litigation History of U.S. Patent 6,813,742

U.S. Patent No. 6,813,742, assigned to TurboCode LLC, has been the subject of extensive litigation, having been asserted against at least 35 companies. The patent, which covers a high-speed turbo codes decoder for 3G wireless communications, has been litigated primarily in the Western and Eastern Districts of Texas.

Detailed below are notable cases involving this patent. The outcomes often involve voluntary dismissals, suggesting settlements or other resolutions prior to a final judgment on the merits.

Plaintiff(s)	Defendant(s)	Jurisdiction	Case Number	Filing Date	Outcome/Status
TurboCode LLC	TCL Technology	Western District of Texas	1:22-cv-01163	Not specified in results	Dismissed with prejudice on January 4, 2024, following a joint motion, suggesting a confidential settlement.
TurboCode LLC	[Dell Technologies Inc. et al](/litigations/by-defendant/Dell%20Technologies%20Inc.%20et%20al)	Western District of Texas	6:21-cv-00359	April 12, 2021	Status not specified in search results.
TurboCode LLC	BEC Technologies, Inc.	Eastern District of Texas	4:24-cv-00357	April 25, 2024	Voluntarily dismissed with prejudice by TurboCode LLC on August 12, 2024, before the defendant filed an answer.
TurboCode LLC	Advantech Co., Ltd.	Eastern District of Texas	4:24-cv-00524	June 7, 2024	Status not specified in search results.
TurboCode LLC	Ceragon Networks, Inc.	Eastern District of Texas	Not specified in results	Not specified in results	Terminated on July 9, 2025.

Other defendants that have been involved in litigation concerning the '742 patent include Itron, Acer, Hitachi, Siemens, T-Mobile, AT&T, HTC, and Huawei.

It should be noted that a request for ex parte reexamination of the '742 patent was filed by Unified Patents on April 14, 2026. The outcome of this reexamination could impact any ongoing and future litigation.

Proceedings overview

No AIA (America Invents Act) trial proceedings, such as Inter Partes Reviews (IPRs), Post-Grant Reviews (PGRs), or Covered Business Method (CBM) reviews, are on file for US Patent 6,813,742 as of the most recent data ingest. However, the patent has undergone one ex parte reexamination, which concluded with claims 5 and 8 being canceled and the remaining claims (1-4, 6-7) being confirmed as patentable in an amended form. A second ex parte reexamination request was filed by Unified Patents, LLC on April 14, 2026, and is currently pending.

For a defendant facing assertion of this patent today, the key takeaway is that claims 5 and 8 are no longer valid, and claims 1-4, 6, and 7 survived a challenge and are patentable as amended. Any infringement theories must rely on the amended versions of claims 1-4, 6, and 7. The pending reexamination by Unified Patents could potentially impact the validity of the remaining claims.

90/008,189 — Ex Parte Reexamination of US 6,813,742 (Patent Owner: IComm Tech Inc)

• Type: Ex Parte Reexamination
• Filed: December 5, 2006 (Date of Request for Reexamination)
• Status: Concluded - Certificate Issued (February 10, 2009)
• Judge panel: Not applicable (ex parte reexaminations are handled by a Patent Examiner, not a PTAB panel).
• Petition grounds: The exact prior art and grounds raised by the third-party requester (who initiated this reexamination) are not detailed in the provided patent text. However, ex parte reexaminations are based on patents or printed publications relevant to 35 U.S.C. §§ 102 and 103.
• Institution decision: Reexamination was ordered (implied by the issuance of a certificate).
• Final Written Decision (if issued): A Reexamination Certificate (B1 6,813,742) was issued on February 10, 2009. The outcome stated that "CLAIMS 5 AND 8 ARE CANCELLED. CLAIMS 1-4, 6 AND 7 ARE DETERMINED TO BE PATENTABLE AS AMENDED."
• Settlement / termination: Not applicable for ex parte reexaminations.
• Appeal: Not applicable in the same manner as AIA trials; decisions are appealable within the USPTO and then to the Federal Circuit. No record of such an appeal for this reexamination is provided.
• Defensive value: Claims 5 and 8 of the original patent are no longer valid. Any current or future assertion of the patent cannot rely on these claims. Claims 1-4, 6, and 7 were confirmed as patentable as amended, meaning they survived a prior validity challenge. A defendant would need to analyze the specific amendments made to these claims during the reexamination to understand their current scope and potential for infringement.

Unified Patents, LLC v. Turbocode LLC (Ex Parte Reexamination Request filed 2026-04-14)

• Type: Ex Parte Reexamination Request
• Filed: April 14, 2026
• Status: Pending (Awaiting a determination of a Substantial New Question of Patentability (SNQ)).
• Judge panel: Not applicable at this stage.
• Petition grounds: Unified Patents, LLC typically challenges patents based on prior art (patents or printed publications) under 35 U.S.C. §§ 102 and 103. The specific claims challenged and the prior art cited are not publicly detailed in the provided patent information or search results.
• Institution decision: This request is pending. For requests filed on or after April 5, 2026, patent owners now have a new "pre-order" procedure to submit a paper within 30 days of service to argue against the finding of a Substantial New Question of Patentability (SNQ) before reexamination is ordered. The USPTO then has three months from the filing date to determine if an SNQ has been raised.
• Final Written Decision (if issued): Not yet issued as the request is still in its initial review phase.
• Settlement / termination: Not applicable.
• Appeal: Not applicable at this stage.
• Defensive value: This active reexamination represents a new challenge to the patent's validity. If reexamination is ordered and successful, it could lead to the cancellation or further amendment of the remaining claims (1-4, 6, 7). A defendant facing assertion could monitor this proceeding closely as its outcome will directly impact the strength of the patent.

Strategic summary

Currently, claims 5 and 8 of US 6,813,742 are CANCELED, while claims 1-4, 6, and 7 are SUSTAINED in their amended form following Ex Parte Reexamination Control No. 90/008,189. This significantly narrows the scope of the patent compared to its original issuance. The patent has been "hardened" in the sense that its surviving claims have withstood a prior validity challenge.

The estoppel landscape for ex parte reexaminations is generally different from IPRs. While an IPR FWD estops a petitioner and its privies from raising grounds raised or reasonably could have raised, ex parte reexaminations initiated by a third party do not typically create the same statutory estoppel under 335 U.S.C. § 315(e)(2) for that third party in subsequent litigation. However, if an ex parte reexamination is ordered, the patent owner can amend claims. A defendant being asserted against might still be able to use the same prior art, or new prior art, depending on the specifics and their involvement. Unified Patents is a defensive aggregator known for challenging patents, and their recent request signals a continued effort to invalidate this patent. The new USPTO pre-order procedure for ex parte reexaminations allows the patent owner to submit arguments against institution, a strategic consideration for both sides.

The current litigation history shows TurboCode LLC has been actively asserting this patent against numerous companies, often leading to confidential settlements. The reexamination by Unified Patents suggests a counter-strategy against this assertion pattern. The absence of AIA trial proceedings (IPR/PGR/CBM) for a patent that has been extensively litigated and held by an NPE like TurboCode LLC, especially given the increased use of ex parte reexaminations in Q1 2026, is noteworthy. This might be due to recent shifts in PTAB policies making IPRs harder to institute.

Recommended next steps

• For the concluded Ex Parte Reexamination (90/008,189): Defendants should obtain and thoroughly analyze the Reexamination Certificate B1 6,813,742 and its prosecution history. This will show the exact amendments made to claims 1-4, 6, and 7, which are now the only claims that can be asserted. Any infringement analysis must be based on the amended claim language.
  • Disposition for Claims 5 and 8: "CLAIMS 5 AND 8 ARE CANCELLED."
  • Disposition for Claims 1-4, 6, and 7: "CLAIMS 1-4, 6 AND 7 ARE DETERMINED TO BE PATENTABLE AS AMENDED."
• For the pending Ex Parte Reexamination by Unified Patents (filed 2026-04-14): Defendants should monitor this proceeding closely. The next significant milestone will be the USPTO's determination on whether a Substantial New Question of Patentability (SNQ) has been raised, which is expected within three months of the April 14, 2026 filing date (around mid-July 2026). If reexamination is ordered, the proceedings could lead to further claim invalidation or amendment, potentially weakening the patent owner's position.

Inventors

• Quang Nguyen (Employer: IComm Tech Inc at the time of filing).

Original assignee

IComm Tech Inc. was the original assignee named on the issued patent. There is no information in the provided patent text or readily available public records to confirm if IComm Tech Inc. shipped a product embodying the claims. The primary line of business was implied to be in "Baseband Processor and Error-Correction Codes for Third Generation (3G) Wireless Mobile Communications" as described in the patent's field of invention. The current status of IComm Tech Inc. is not specified in the patent information, but subsequent assignments indicate its interest was transferred.

Assignment timeline

• 2002-09-07 (executed) / recorded 2002-09-13 — Reel 013084/0676

  • Conveyance: Assignment
  • Assignor: Quang Nguyen
  • Assignee: ICOMM TECHNOLOGIES, INC., PENNSYLVANIA
  • Correspondent: John F. Williams, Law Office of John F. Williams, P.C., 202 S. Main Street, Suite 300, Blacksburg, VA 24060.
  • Context: Inventor assigned rights to the original assignee.

• 2018-06-21 (executed) / recorded 2018-11-19 — Reel 047547/0691

  • Conveyance: Assignment
  • Assignor: ICOMM TECHNOLOGIES, INC.
  • Assignee: INNOBRILLIANCE, LLC, TEXAS
  • Correspondent: Hanieh Mazhar, MAZHAR IP LAW, PLLC, 303 Pearl Pkwy Ste 111, San Antonio, TX 78215.
  • Context: Transfer from original assignee to an LLC.

• 2021-03-25 (executed) / recorded 2021-03-26 — Reel 055728/0845

  • Conveyance: Assignment
  • Assignor: INNOBRILLIANCE, LLC
  • Assignee: TURBOCODE LLC, TEXAS
  • Correspondent: Robert C. Cumbow, CUMBOW & ASSOCIATES, LLC, 7635 Ashley Park Court, Suite 503-T, Orlando, FL 32835.
  • Context: Transfer from one LLC to another LLC (current assignee).

• 2021-03-25 (executed) / recorded 2021-07-29 — Reel 057066/0655

  • Conveyance: Corrective Assignment
  • Assignor: INNOBRILLIANCE, LLC
  • Assignee: TURBOCODE LLC, TEXAS
  • Correspondent: Robert C. Cumbow, CUMBOW & ASSOCIATES, LLC, 7635 Ashley Park Court, Suite 503-T, Orlando, FL 32835. This correspondent recurred in this chain.
  • Context: Corrective assignment for a previous transfer.

• 2021-03-25 (executed) / recorded 2021-08-20 — Reel 057573/0448

  • Conveyance: Corrective Assignment
  • Assignor: INNOBRILLIANCE, LLC
  • Assignee: TURBOCODE LLC, TEXAS
  • Correspondent: Robert C. Cumbow, CUMBOW & ASSOCIATES, LLC, 7635 Ashley Park Court, Suite 503-T, Orlando, FL 32835. This correspondent recurred in this chain.
  • Context: Corrective assignment for a previous transfer.

Timeline diagram

timeline
    title Ownership of US 6813742
    2002 : Assigned to IComm Technologies Inc
    2004 : Patent issued
    2018 : Assigned to Innobrilliance LLC
    2021 : Assigned to Turbocode LLC
         : Corrective Assignment Turbocode
         : Corrective Assignment Turbocode

NPE / troll-pattern signals

1. Shell-entity transfer — present.

   • Innobrilliance, LLC: Transferred from ICOMM TECHNOLOGIES, INC. to INNOBRILLIANCE, LLC on 2018-11-19 (Reel 047547/0691). The name "LLC" and the absence of clear product information for Innobrilliance suggest a licensing-focused entity.
   • TurboCode LLC: Transferred from INNOBRILLIANCE, LLC to TURBOCODE LLC on 2021-03-26 (Reel 055728/0845). "LLC" in the name and current litigation patterns (asserting against numerous companies) strongly indicate a licensing-only entity.

2. Known asserter in the chain — present.

   • TurboCode LLC: The current assignee, TurboCode LLC, is identified as the plaintiff in the litigation summary, having asserted the patent against at least 35 companies. This directly aligns with the definition of a high-frequency plaintiff or NPE.

3. Repeat correspondent across the chain — present.

   • Robert C. Cumbow, CUMBOW & ASSOCIATES, LLC: Appears as the correspondent on multiple corrective assignments from INNOBRILLIANCE, LLC to TURBOCODE LLC on 2021-07-29 (Reel 057066/0655) and 2021-08-20 (Reel 057573/0448). This suggests a consistent legal representation across these transfers to the current asserting entity.

4. Cascading transfers — unclear. While there are two corrective assignments close in time after the main assignment to Turbocode LLC, the primary transfers (IComm Tech -> Innobrilliance -> Turbocode) occurred over a few years, not within 24 months. The corrective assignments themselves don't form a "chain" of distinct assignees.

5. Pre-litigation transfer — present.

   • The patent was assigned to TurboCode LLC on 2021-03-26 (Reel 055728/0845). The litigation summary indicates a case was filed by TurboCode LLC vs. [Dell Technologies Inc. et al](/litigations/by-defendant/Dell%20Technologies%20Inc.%20et%20al) on April 12, 2021 (case 6:21-cv-00359), which is within six months of the transfer. This suggests the transfer was made in preparation for assertion.

6. Bankruptcy fire-sale — not present. No indication of bankruptcy proceedings for IComm Tech Inc. or Innobrilliance, LLC in the assignment records or patent information.

7. Privateering — unclear. While the pattern aligns with an NPE asserting patents, there's no explicit evidence (e.g., SEC filings, specific reports) to confirm that TurboCode LLC is asserting on behalf of an operating company.

8. Defensive aggregator (anti-NPE) — not present. The chain ends with TurboCode LLC, an asserting entity, and does not involve any known defensive aggregators.

Verdict

NPE — high confidence

The assignment timeline and identified signals strongly indicate that US Patent 6,813,742 is being asserted by a Non-Practicing Entity (NPE). Key signals include the transfer to shell entities (INNOBRILLIANCE, LLC and TURBOCODE LLC (Reel 047547/0691, Reel 055728/0845)), the current assignee TURBOCODE LLC being a known asserter with numerous litigation cases, and a transfer to TURBOCODE LLC occurring within six months of its first recorded litigation for this patent. The recurrence of the same correspondent for the corrective assignments also points towards a managed assertion strategy.

For verification, see the USPTO Assignment Center search results for US6813742: https://assignmentcenter.uspto.gov/patent/index.html

Prior Art Analysis for U.S. Patent 6,813,742

The following analysis details prior art cited during the prosecution of U.S. Patent 6,813,742. Each reference is evaluated for its potential to anticipate the claims of the '742 patent under 35 U.S.C. § 102. The analysis focuses primarily on independent claims 1 and 6, which define the core inventive concepts of the patent.

The '742 patent describes a turbo code decoder architecture using two or more soft-in/soft-out (SISO) Log-Maximum a Posteriori (Log-MAP) decoders in a pipelined, circular, and iterative configuration to improve decoding speed and efficiency for 3G wireless communications.

Cited Patent References

1. U.S. Patent 5,446,747 - "Error-correction coding method with at least two systematic convolutional codings in parallel, corresponding iterative decoding method, decoding module and decoder"

• Full Citation: US Patent 5,446,747, issued to France Telecom.
• Filing Date: April 23, 1991.
• Brief Description: This patent is foundational to turbo codes. It describes a decoding process that uses two or more elementary decoders in an iterative loop. The output of one decoder, specifically the extrinsic information, is passed to the next decoder to refine the probability estimates of the received data. The process is repeated, with each iteration improving the accuracy of the final decoded output.
• Potential Anticipation: This reference is highly relevant as it discloses the fundamental concept of iterative decoding using multiple decoders.
  • Claim 1: The '747 patent appears to anticipate the core elements of claim 1. It describes at least two decoders coupled in a manner where the output of one feeds the input of another in an iterative process. The patent's disclosure of passing extrinsic information between decoders implies the use of memory to store these intermediate soft decisions.
  • Claim 6: The method described in claim 6 is also likely anticipated. The '747 patent explicitly details a method of iterative decoding using what is now known as the MAP algorithm, where soft decisions (extrinsic information) from one decoder are used as input for the next in a circular, iterative fashion.

2. U.S. Patent 6,023,783 - "Hybrid concatenated codes and iterative decoding"

• Full Citation: US Patent 6,023,783, assigned to the California Institute of Technology.
• Filing Date: May 15, 1996.
• Brief Description: This patent describes advanced concatenated coding schemes, including hybrid structures that can combine different types of codes. It elaborates on iterative decoding techniques where extrinsic information is exchanged between constituent decoders to achieve high performance.
• Potential Anticipation: This reference builds upon the concepts in the '747 patent and provides further detail on iterative decoding architectures.
  • Claim 1: The '783 patent discloses architectures with serially coupled decoders that operate iteratively. It describes the essential feedback loop where the output from one stage of decoding informs the next, which aligns with the "circular circuit" and iterative processing described in claim 1.
  • Claim 6: The method of iteratively processing systematic and extrinsic information using a MAP-type algorithm is a central theme of the '783 patent. It provides a detailed description of the process of generating and passing soft decision information between decoders, anticipating the core steps of claim 6.

3. U.S. Patent 6,182,261 B1 - "Efficient iterative decoding"

• Full Citation: US Patent 6,182,261 B1, assigned to Qualcomm Incorporated.
• Filing Date: November 5, 1998.
• Brief Description: This patent focuses on improving the efficiency of iterative decoders, such as turbo decoders. It discloses methods for managing memory and computations to optimize the decoding process, including techniques for handling block sizes and scheduling the iterative decoding steps.
• Potential Anticipation: This patent addresses the practical implementation and efficiency of the systems described in the '747 and '783 patents.
  • Claim 1: The '261 patent describes systems with multiple decoders and memory modules configured for iterative decoding. Its focus on efficiency anticipates the practical arrangement claimed, wherein decoders are serially coupled and memory is used to pass information between them.
  • Claim 6: This reference details methods for performing iterative decoding that include generating soft decisions and feeding them back in subsequent iterations. While it may not use the exact "logarithm approximation algorithm" language, the underlying principles of MAP-based iterative decoding are present, potentially anticipating the method of claim 6.

4. U.S. Patent 6,526,539 B1 - "Turbo decoder"

• Full Citation: US Patent 6,526,539 B1, assigned to Fujitsu Limited.
• Filing Date: June 23, 1999.
• Brief Description: This patent discloses a turbo decoder architecture designed for practical implementation. It describes the arrangement of constituent decoders, interleavers, and memory components. The focus is on a hardware implementation that can achieve high-speed performance.
• Potential Anticipation: As a more contemporary reference, it describes an architecture that is structurally very similar to that claimed in the '742 patent.
  • Claim 1: The '539 patent describes a turbo decoder with two MAP decoders, an interleaver, and a deinterleaver, which function as memory modules. The decoders are connected in a feedback loop for iterative processing, directly aligning with the structure of "at least two soft decision decoders are serially coupled in a circular circuit" as recited in claim 1.
  • Claim 6: The method of decoding described in the '539 patent inherently involves the iterative steps of processing information, generating soft outputs, storing them, and feeding them back to another decoder, which maps directly onto the method described in claim 6.

In summary, the cited prior art, particularly the foundational '747 patent and the more implementation-focused '539 patent, appear to disclose the key elements of the independent claims of the '742 patent. The novelty of the '742 patent likely resides in the specific architectural details claimed, such as the use of "pipelined" Log-MAP decoders and the specific configuration for 3G wireless standards, which would require a more detailed infringement analysis to distinguish from this prior art.

Obviousness Analysis of U.S. Patent 6,813,742 under 35 U.S.C. § 103

This analysis evaluates the obviousness of the independent claims of U.S. Patent 6,813,742 ('742 patent) in light of the prior art cited during its prosecution. The standard for obviousness under 35 U.S.C. § 103 is whether the claimed invention as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art (a "POSA"). This analysis focuses on whether a POSA would have been motivated to combine the teachings of the existing prior art to arrive at the invention claimed in the '742 patent.

The core of the '742 patent, as defined in independent claims 1 and 6, is a turbo decoder architecture for 3G wireless systems that uses at least two soft-in/soft-out (SISO) decoders in a serially-coupled, circular, and iterative configuration. The key features are the iterative feedback loop and the use of MAP (or Log-MAP) algorithms to process soft decision information.

A person of ordinary skill in the art at the time of the invention (priority date of January 2, 2001) would have been an electrical engineer or computer scientist with experience in digital communications, error-correction coding, and integrated circuit design, particularly with knowledge of algorithms like Viterbi and MAP, and familiarity with emerging 3G wireless standards.

Combination of Prior Art Rendering Claims Obvious

The claims of the '742 patent would have been obvious to a POSA by combining the foundational teachings of U.S. Patent 5,446,747 ('747 patent) with the practical implementation details disclosed in U.S. Patent 6,526,539 B1 ('539 patent).

• '747 Patent (Berrou et al.): This patent is a foundational reference for turbo codes and explicitly teaches the core concept of iterative decoding. It discloses a decoder comprising at least two constituent decoders connected in a feedback loop. Crucially, it describes the process where one decoder calculates and outputs "extrinsic information" (a form of soft decision) which is then used as an input by the subsequent decoder. This iterative process, passing refined probabilistic information back and forth, is the central mechanism of turbo decoding and directly maps to the "iteratively processing," "circular circuit," and feedback loop elements recited in claims 1 and 6 of the '742 patent.

• '539 Patent (Fujitsu): This patent, filed in June 1999, addresses the practical hardware implementation of a turbo decoder. It explicitly discloses a turbo decoder architecture with two MAP decoders, an interleaver, and a de-interleaver. The components are arranged for iterative decoding, where the output of one decoder is passed through memory (the interleaver/de-interleaver) to the other. This patent provides a clear and concrete hardware blueprint for the system conceptually introduced by the '747 patent.

Motivation to Combine

A person of ordinary skill in the art in early 2001 would have been strongly motivated to combine the teachings of the '747 and '539 patents for the following reasons:

1. Solving a Known Problem with a Known Solution: The '747 patent established the theoretical and functional basis for turbo codes, demonstrating their superior performance. The primary challenge then shifted to creating efficient, high-speed hardware implementations suitable for commercial applications like the emerging 3G wireless standards. The '539 patent directly addresses this challenge by providing a specific, practical architecture for a hardware-based turbo decoder. A POSA, tasked with designing a high-performance decoder for a 3G baseband processor, would have naturally looked to the foundational principles of the '747 patent and sought out known methods for efficient hardware implementation, such as those described in the '539 patent.

2. Predictable Results: Combining the iterative decoding method from the '747 patent with the hardware architecture from the '539 patent would yield a result that was entirely predictable: a functional, hardware-based turbo decoder. The '539 patent is essentially an implementation of the concepts taught in the '747 patent. The combination does not produce an unexpected or surprising result; rather, it achieves the exact goal for which both technologies were developed—efficient, high-performance error correction.

3. Use of Log-MAP as a Known Optimization: The '742 patent claims the use of a "logarithm approximation algorithm," referring to the Log-MAP algorithm. The standard MAP algorithm, while optimal, was known to be computationally intensive due to its many multiplication operations. The Log-MAP algorithm, which operates in the log domain and replaces multiplications with simpler additions, was a well-known and widely adopted simplification by 2001. A POSA would have considered the use of Log-MAP not as an inventive step, but as a standard and obvious design choice for implementing a MAP-based decoder in an application-specific integrated circuit (ASIC) to reduce complexity, cost, and power consumption, all of which are critical for 3G devices. The '742 patent itself touts this as an advantage, but it was a common practice in the field.

Conclusion on Obviousness

• Claim 1 recites a baseband processor with at least two serially coupled soft decision decoders in a circular circuit, with memory modules to facilitate feedback. The '747 patent teaches the circular, iterative processing, and the '539 patent provides a concrete example of this architecture using two MAP decoders and memory (interleaver/de-interleaver). A POSA would have found it obvious to implement the iterative method of '747 using the hardware structure of '539.

• Claim 6 recites a method of iterative decoding using a MAP (or logarithm approximation) algorithm, generating and storing soft decisions, and feeding the output of the last decoder back to the first. This is the fundamental process of turbo decoding as taught by the '747 patent. The '539 patent describes this same method in the context of a specific hardware implementation. The selection of a Log-MAP algorithm would have been an obvious and routine optimization for any skilled engineer implementing such a decoder in hardware.

Therefore, the combination of the foundational iterative decoding method disclosed in the '747 patent with the practical hardware architecture shown in the '539 patent would have rendered the independent claims of the '742 patent obvious to a person of ordinary skill in the art at the time of the invention. The '742 patent claims a predictable combination of known elements from the prior art that were established solutions to well-understood problems in the field of digital communications.

Patent Term and Family Details for U.S. Patent 6,813,742

Projected Expiration:

The patent has expired. U.S. Patent 6,813,742 was filed on January 2, 2001. Under the patent term of 20 years from the earliest filing date, the patent term would have ended on January 2, 2021. Public records indicate the patent's status is "Expired - Lifetime" with an adjusted expiration date of December 15, 2021. No evidence of Patent Term Adjustment (PTA) or Patent Term Extension (PTE) that would extend the date beyond this has been found.

Patent Term Adjustments (PTA) / Extensions (PTE):

• PTA: There is no indication of any Patent Term Adjustment in the available records. PTA is granted to compensate for delays caused by the USPTO during the patent prosecution process.
• PTE: There is no indication of any Patent Term Extension. PTE is typically granted for patents covering products that undergo a lengthy regulatory review process, such as pharmaceuticals, which is not applicable to this patent's technology area.

Continuity and Related Family Members:

The application for the '742 patent (US 09/681,093) is part of a family of applications that claim priority to the same initial filing date.

• Continuation-in-Part Applications:

  • U.S. Patent 6,799,295 (Application No. 10/248,245): Filed on December 30, 2002, this is a continuation-in-part of the application that led to the '742 patent.
  • U.S. Patent Application Publication No. 2003/0097633 A1 (Application No. 10/065,408): Filed on October 15, 2002, this is also a continuation-in-part of the '742 patent's application. This application was later abandoned.

• Provisional Application: The '742 patent references and claims the benefit of U.S. Provisional Application No. 60/131,516, filed on May 26, 1999.

The existence of these related applications demonstrates a strategy to expand and build upon the technology disclosed in the original 2001 filing. However, the expiration date of the '742 patent is tied to its own filing date, and it has now expired.

Defensive Disclosure: Architectures and Methods for Iterative Signal Decoding

Publication Date: May 9, 2026

Abstract: This document discloses various implementations, applications, and extensions of iterative decoding systems, particularly those employing multiple soft-in/soft-out (SISO) decoders in a pipelined and circular configuration. The disclosed variations are intended to enter the public domain to serve as prior art for future patent applications in the fields of digital communications, signal processing, and related technologies. The following disclosures build upon the core concepts found in U.S. Patent 6,813,742.

---

I. Derivative Embodiments

Axis 1: Material & Component Substitution

1.1. Quantum-Assisted Hybrid Decoder

• Enabling Description: This embodiment replaces the classical soft-decision decoders described in U.S. Patent 6,813,742 with hybrid quantum-classical modules. The architecture maintains two serially coupled decoding units operating in a circular, iterative fashion. Within each unit, a classical digital pre-processor calculates the branch metrics from the received soft-symbol inputs. These metrics are then mapped into a Quadratic Unconstrained Binary Optimization (QUBO) problem, where the trellis state transitions are represented by binary variables. A dedicated Quantum Annealing unit is used to find the ground-state solution to the QUBO problem, which corresponds to the maximum a posteriori probability path through the trellis. A classical post-processor converts the annealing result back into extrinsic information (log-likelihood ratios) for the subsequent decoding stage. The interleaver and de-interleaver memory modules are implemented with Magnetoresistive RAM (MRAM) to reduce static power consumption and provide non-volatility for state-saving operations.
• Mermaid Diagram:

  graph TD
      subgraph Hybrid Decoder A
          A1[Classical Pre-Processor] --> A2{QUBO Formulation};
          A2 --> A3[Quantum Annealer];
          A3 --> A4[Classical Post-Processor];
      end
      subgraph Hybrid Decoder B
          B1[Classical Pre-Processor] --> B2{QUBO Formulation};
          B2 --> B3[Quantum Annealer];
          B3 --> B4[Classical Post-Processor];
      end
      subgraph Memory
          M1[Interleaver Memory (MRAM)];
          M2[De-interleaver Memory (MRAM)];
      end
  
      Input[Received Signal] --> A1;
      A4 --> M1;
      M1 --> B1;
      B4 --> M2;
      M2 -- Feedback --> A1;
      B4 --> Decoded_Output[Hard Decision Output];
  

1.2. Neuromorphic Spiking Network Decoder

• Enabling Description: This variation implements the Soft-In/Soft-Out (SISO) decoders using a Spiking Neural Network (SNN) on a neuromorphic processor. The iterative decoding algorithm is mapped to a recurrent SNN architecture. Trellis states from the Log-MAP algorithm are represented by distinct clusters of spiking neurons. Branch metrics derived from the input signal are encoded as input spike trains, where the probability is proportional to the spike frequency. The recursive state metric calculation is performed through the temporal integration of spikes by the neuron clusters. The Add-Compare-Select (ACS) function is realized using winner-take-all (WTA) inhibitory circuits that ensure only the most likely path (neuron cluster) continues to fire. The extrinsic information passed between the two neuromorphic decoders is encoded as the output spike patterns. This asynchronous, event-driven approach drastically reduces power consumption compared to a clocked, digital ASIC implementation.
• Mermaid Diagram:

  sequenceDiagram
      participant R as Received Signal
      participant SNN_A as Neuromorphic Decoder A
      participant MEM_I as Interleaver Memory
      participant SNN_B as Neuromorphic Decoder B
      participant MEM_DI as De-interleaver Memory
  
      R->>SNN_A: Input Spike Trains (Systematic Info)
      Note over SNN_A: Neuron clusters compute forward/backward passes
      SNN_A->>MEM_I: Store Extrinsic Info (Encoded Spike Patterns)
      MEM_I->>SNN_B: Provide Interleaved Extrinsic Info
      R->>SNN_B: Input Spike Trains (Parity Info)
      Note over SNN_B: Neuron clusters compute forward/backward passes
      SNN_B->>MEM_DI: Store De-interleaved Extrinsic Info
      loop Iterations
          MEM_DI->>SNN_A: Feedback Extrinsic Info
          SNN_A->>MEM_I: Update Extrinsic Info
          MEM_I->>SNN_B: Update Extrinsic Info
          SNN_B->>MEM_DI: Update Extrinsic Info
      end
      SNN_B-->>Decoded_Output: Final Decision
  

Axis 2: Operational Parameter Expansion

2.1. Cryogenic Superconducting Decoder for Terabit Communication

• Enabling Description: This embodiment describes the decoder architecture implemented with superconducting logic, such as Rapid Single Flux Quantum (RSFQ) circuits, to achieve operational clock frequencies exceeding 100 GHz. The entire baseband processor, including the two SISO decoders and memory modules, is designed to operate at cryogenic temperatures (e.g., 4 Kelvin). The Log-MAP algorithm's adders, comparators, and selectors are built from Josephson junction-based logic gates. Data is represented by the propagation of single magnetic flux quanta. This design is intended for extreme-bandwidth applications, such as deep-space communication links or terrestrial terabit-per-second backhaul networks, where real-time decoding is required for data rates far beyond the capabilities of conventional CMOS technology.
• Mermaid Diagram:

  graph TD
      subgraph Cryocooler (4K)
          subgraph RSFQ_Decoder_A
              direction LR
              BM_A[Branch Metric] --> FACS_A[Forward ACS];
              BM_A --> BACS_A[Backward ACS];
              FACS_A & BACS_A --> LMAP_A[Log-MAP Calc];
          end
          subgraph RSFQ_Decoder_B
              direction LR
              BM_B[Branch Metric] --> FACS_B[Forward ACS];
              BM_B --> BACS_B[Backward ACS];
              FACS_B & BACS_B --> LMAP_B[Log-MAP Calc];
          end
          subgraph Superconducting_Memory
              MEM_I[Interleaver RAM]
              MEM_DI[De-interleaver RAM]
          end
          RF_Input(Terabit RF In) --> RSFQ_Decoder_A;
          LMAP_A --> MEM_I;
          MEM_I --> RSFQ_Decoder_B;
          LMAP_B --> MEM_DI;
          MEM_DI -- Feedback --> RSFQ_Decoder_A;
          LMAP_B --> Decoded_Output(Terabit Data Out);
      end
  

2.2. Radiation-Hardened Decoder for Extreme Environments

• Enabling Description: This version is designed for operation in high-radiation environments, such as satellite avionics or planetary rovers. The decoder is fabricated on a Silicon-On-Insulator (SOI) process using radiation-hardened-by-design (RHBD) principles. All sequential and combinational logic within the Log-MAP decoders is implemented with Triple-Modular Redundancy (TMR), where each gate is triplicated and its output is determined by a majority voter circuit to mitigate single-event upsets (SEUs). The interleaver and de-interleaver memory arrays are protected by built-in Error Detection and Correction (EDAC) logic (e.g., a Hamming code or BCH code) for each memory word, ensuring the integrity of the stored extrinsic information against single-event functional interrupts (SEFIs). The iterative nature of the decoder provides a further layer of resilience, as transient errors in one iteration can be corrected in subsequent passes.
• Mermaid Diagram:

  stateDiagram-v2
      [*] --> Idle
      Idle --> Receiving: Decoder_Enable
      Receiving --> Decode_A: Block_Ready
      state Decode_A {
          direction LR
          TMR_BM: Branch Metric (TMR)
          TMR_SM: State Metric (TMR)
          TMR_LMAP: Log-MAP (TMR)
          TMR_BM --> TMR_SM --> TMR_LMAP
      }
      Decode_A --> Store_Interleaved: A_Done
      note right of Decode_A: All logic uses Triple Modular Redundancy
      Store_Interleaved --> Decode_B: Stored
      note left of Store_Interleaved: Memory uses EDAC codes
      state Decode_B {
          direction LR
          TMR_BM_B: Branch Metric (TMR)
          TMR_SM_B: State Metric (TMR)
          TMR_LMAP_B: Log-MAP (TMR)
          TMR_BM_B --> TMR_SM_B --> TMR_LMAP_B
      }
      Decode_B --> Store_Deinterleaved: B_Done
      Store_Deinterleaved --> Iteration_Check
      Iteration_Check --> Decode_A: Iterate
      Iteration_Check --> Hard_Decision: Max_Iterations_Reached
      Hard_Decision --> [*]: Output_Ready
  

Axis 3: Cross-Domain Application

3.1. Genomic Sequencing Error Correction

• Enabling Description: The iterative decoding architecture is applied to correct errors in raw data from Next-Generation Sequencing (NGS) of DNA or RNA. A DNA fragment is modeled as a message protected by a convolutional code, where the "channel" is the error-prone sequencing process. The systematic information is derived from a primary read of the fragment, while parity information is derived from a redundant paired-end read. The "soft information" input to the decoders is the per-base quality score (e.g., Phred score) provided by the sequencer. The pipelined decoders iteratively refine the probability of each base call (A, T, C, G), using the redundant information to resolve ambiguities and correct substitution errors. The interleaver helps mitigate the impact of burst errors common in some sequencing technologies. The final output is a high-confidence consensus sequence.
• Mermaid Diagram:

  flowchart TD
      A[NGS Sequencer] --> B{Raw Reads (Read 1 + Read 2) & Quality Scores};
      B --> C[Soft Value Mapping];
      C --> |Systematic: Read 1, Parity: Read 2| D[SISO Decoder A];
      D --> E[Interleaver Memory];
      E --> F[SISO Decoder B];
      F --> G[De-interleaver Memory];
      G -- Iterative Feedback --> D;
      F --> H{Consensus Sequence Generation};
      H --> I[High-Fidelity DNA Sequence];
  

3.2. Predictive Maintenance in Industrial IoT

• Enabling Description: The decoder architecture is used to predict failures in industrial machinery by analyzing correlated sensor data. A machine's healthy operational state is modeled as a known state machine (the code's trellis). Correlated sensor streams, such as vibration data (systematic information) and acoustic emissions (parity information), are treated as noisy signals. The decoder system processes these streams in real-time. Deviations from the "healthy" signal pattern are treated as errors. The soft-decision extrinsic information that is iteratively passed between decoders represents the evolving probability of a fault condition. When the log-likelihood ratio of a fault state exceeds a predetermined threshold, a predictive maintenance alert is triggered.
• Mermaid Diagram:

  graph LR
      subgraph Machine
          S1[Vibration Sensor]
          S2[Acoustic Sensor]
      end
      subgraph Predictive_Maintenance_Unit
          D1[SISO Decoder 1]
          D2[SISO Decoder 2]
          M1[Interleaver Memory]
          M2[De-Interleaver Memory]
      end
      subgraph ControlSystem
          A[Alert Dashboard]
      end
      S1 -- Systematic Data --> D1
      S2 -- Parity Data --> D1
      D1 --> M1 --> D2
      D2 --> M2 -- Feedback --> D1
      D2 -- Failure Probability --> A
  

Axis 4: Integration with Emerging Tech

4.1. AI-Managed Adaptive Decoding

• Enabling Description: A reinforcement learning (RL) agent is integrated to dynamically manage the decoder's operational parameters. The RL agent monitors the communication channel's state (e.g., SNR) and the decoder's performance (e.g., extrinsic information convergence rate). Based on this state, the agent selects actions to optimize for a reward function balancing accuracy, latency, and power consumption. Actions include: (1) dynamically adjusting the number of decoding iterations, (2) selecting the optimal MAP approximation algorithm (e.g., Log-MAP vs. Max-Log-MAP), and (3) altering the bit-width of the soft-value quantization. This creates an intelligent decoder that adapts its resource usage to changing channel conditions in real-time.
• Mermaid Diagram:

  flowchart TD
      subgraph Main_Decoder
          Input[Signal In] --> D_A[Decoder A]
          D_A <--> D_B[Decoder B]
          D_B --> Output[Signal Out]
      end
      subgraph RL_Controller
          Monitor[Monitor SNR, BER, Power]
          Agent{RL Agent}
          Action[Set Iterations, Algorithm, Quantization]
      end
      Monitor -- State --> Agent
      Agent -- Action --> Action
      Action --> D_A
      Action --> D_B
      Output -- Reward Signal --> Monitor
  

4.2. Distributed Cooperative Decoding in IoT Mesh Networks

• Enabling Description: The decoder's components are distributed across two or more separate nodes in an IoT mesh network to enable cooperative decoding of weak signals. Node A receives the systematic portion of a signal and functions as Decoder A. After its processing pass, it transmits the resulting extrinsic information over the wireless mesh to Node B. Node B, which received the parity portion of the signal, uses this extrinsic information as an input for its decoding pass (as Decoder B). It then transmits its updated extrinsic information back to Node A. This "over-the-air" iterative exchange allows the nodes to jointly decode a signal that would be indecipherable to either node individually.
• Mermaid Diagram:

  sequenceDiagram
      participant Source
      participant IoT_A
      participant IoT_B
      participant Sink
  
      Source->>IoT_A: Transmit Systematic Bits (Weak Signal)
      Source->>IoT_B: Transmit Parity Bits (Weak Signal)
      IoT_A->>IoT_A: Perform Decode Pass 1
      IoT_A->>IoT_B: Transmit Extrinsic Info via Mesh
      IoT_B->>IoT_B: Perform Decode Pass 2
      IoT_B->>IoT_A: Transmit Updated Extrinsic Info via Mesh
      Note over IoT_A, IoT_B: Iterations continue over the mesh link
      IoT_B->>Sink: Send Final Decoded Data
  

Axis 5: The "Inverse" or Failure Mode

5.1. Graceful Degradation Low-Power Decoder

• Enabling Description: This embodiment is designed for power-constrained devices and features multiple operational modes for graceful degradation of performance. In a "full power" mode, it operates as described in U.S. Patent 6,813,742. When a power management unit signals a low-battery state, the decoder controller transitions to a "low power" mode. In this mode, it reduces the maximum number of iterations (e.g., from 8 to 2), switches from the computationally complex Log-MAP algorithm to the simpler Max-Log-MAP approximation, and reduces the quantization precision of the soft-information from 6 bits to 3 bits. In a "critical power" mode, one of the two decoder cores is power-gated, and the system performs a single-decoder iterative process at half the throughput, further reducing power consumption while maintaining a baseline communication link.
• Mermaid Diagram:

  stateDiagram-v2
      state "Full Power Mode" as Full {
          [*] --> Iteration_Loop
          note right of Full
              Algorithm: Log-MAP
              Iterations: 8
              Quantization: 6-bit
          end note
      }
      state "Low Power Mode" as Low {
          [*] --> Iteration_Loop_Reduced
          note right of Low
              Algorithm: Max-Log-MAP
              Iterations: 2
              Quantization: 3-bit
          end note
      }
      state "Critical Power Mode" as Critical {
           [*] --> Single_Decoder_Loop
           note right of Critical
              Architecture: Single Decoder
              Iterations: 1
           end note
      }
      [*] --> Full: High_Battery
      Full --> Low: Low_Battery_Signal
      Low --> Full: Battery_Recharged
      Low --> Critical: Critical_Battery_Signal
  

---

II. Combination Prior Art with Open-Source Standards

1. Combination with GNU Radio:

• Enabling Description: The pipelined, circular decoder architecture is implemented as a C++ processing block within the GNU Radio open-source SDR framework. The block, named pipelined_turbo_decoder, exposes input ports for systematic and parity soft symbols and an output port for decoded bits. Internally, it instantiates and manages the two SISO decoders, memory buffers, and the iterative feedback loop as described in U.S. Patent 6,813,742. This makes the architecture readily available as a standard component for developers using GNU Radio, thereby placing the implementation in the public domain for SDR applications.

2. Combination with RISC-V ISA Extension:

• Enabling Description: The core computational kernels of the Log-MAP algorithm are defined as a custom instruction set extension for the open-source RISC-V architecture. This extension includes custom instructions such as ACS.FWD Rdest, Rs1, Rs2 to execute a full forward Add-Compare-Select operation in a single cycle, and LMAP.CALC Rdest, Rs1, Rs2, Rs3 to compute the a posteriori probability. A RISC-V processor core designed with this extension can execute the iterative decoding algorithm with high efficiency, with the control flow managed in software and the intensive computations handled by the custom hardware instructions. This standardizes the core method as a public feature of a RISC-V communications processor.

3. Combination with WebRTC Forward Error Correction:

• Enabling Description: The iterative decoding method is implemented as a Forward Error Correction (FEC) mechanism within the open-source WebRTC standard. A WebAssembly (WASM) module containing a complete implementation of the dual-decoder architecture is specified as a standard FEC option for the WebRTC data channel. When a web browser negotiates a WebRTC session that uses this FEC scheme, it loads and executes the WASM module to perform iterative decoding on incoming data packets. This integrates the patented method directly into an open web standard, making it a publicly available technique for any developer of real-time web applications.