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US 6813742

High speed turbo codes decoder for 3G using pipelined SISO log-map decoders architecture

Current assignee: TurboCode LLC

Added 4/30/2026, 2:46:35 PM

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Patent summary

Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.

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Patent Summary: US 6,813,742 B2

Title: High speed turbo codes decoder for 3G using pipelined SISO log-map decoders architecture

Assignee: TurboCode LLC

Inventor: Quang Nguyen

Filing Date: January 2, 2001

Issue Date: November 2, 2004

Abstract:
A Baseband Processor for Wireless Communications is presented. The invention encompasses several improved Turbo codes method to provide a more practical and simpler method for implementation a Turbo Codes Decoder in ASIC or DSP coding. (1) A plurality of pipelined Log-MAP decoders are used for iterative decoding of received data. (2) In a pipeline mode, Decoder A decodes data from the De-interleaver RAM memory while the Decoder B decodes data from the De-interleaver RAM memory at the same time. (3) Log-MAP decoders are simpler to implement in ASIC with only Adder circuits, and are low-power consumption. (4) Pipelined Log-MAP decoders method provide high speed data throughput, one output per clock cycle.

Plain-Language Overview of Independent Claims:

Claim 1: Describes a baseband processor that uses at least two soft decision decoders connected in a circular loop. Each decoder processes the output from the previous one. The output of the last decoder is fed back to the first, creating an iterative processing loop for decoding digital signals. Each decoder is connected to a memory module to store its output before it's passed to the next.

Claim 6: Outlines a method for iteratively decoding received baseband signals. This method involves using a specific type of algorithm (maximum a posteriori (MAP) probability algorithm) to process both the main data and additional "extrinsic" information. The system generates and stores "soft decisions" (probabilistic estimates of the data) in memory. This process is repeated a set number of times, with the output of the last in a series of decoders being fed back to the first, and then sequentially through the others, to refine the decoding accuracy.


Recent Developments:

As of April 14, 2026, a third party, Unified Patents, LLC, filed an ex parte reexamination request for US Patent 6,813,742. The patent has been asserted in litigation against numerous companies in the technology and telecommunications sectors. A search of the CAFC 2026 dockets did not yield any specific results for this patent.

Generated 4/30/2026, 7:48:20 PM