US 6003151

I'll verify the patent details against live sources before summarizing.

Let me check the litigation signal and related family members, since the source page flagged family litigation.

Let me check for any Federal Circuit / ITC activity and the litigation record more precisely.

US Patent 6,003,151 — Verification Summary

Data-integrity caveat up front: I could not retrieve any live USPTO PatentCenter/Assignment record, nor any CAFC docket entry for 2026 (or any year) listing patent 6,003,151 as an asserted patent. The CAFC-2026 portion of your request returned no matching docket — this is a genuine null result, not something I can pad. The details below are drawn from the authoritative full patent text supplied, cross-checked against Google Patents, FreePatentsOnline, uspto.report, a MediaTek financial report, and an ITC publication.

Bibliographic Data

Assignee nuance (literal reading): The source page shows both "1997-03-24 Application filed by MediaTek Inc." and a 1999-04-19 reassignment record reading "MEDIATEK INC. — ASSIGNMENT OF ASSIGNORS INTEREST... Assignors: UNITED MICROELECTRONICS CORPORATION." These two entries are in tension. I report both literally rather than reconciling them; the recorded chain appears to be that the technology originated with UMC and was assigned to MediaTek, consistent with MediaTek's own 2005 filing stating its optical-drive controller technology "源自聯華電子" (originated from UMC).

Abstract (verbatim, as fetched)

Data read out from a mass storage unit are provided as a serial data stream in parallel to both a buffer memory and an error detection circuit. The read out data are stored within the buffer memory. At the same time, the error detection circuit performs an error detection operation on the serial data stream read out from the mass storage unit. The error detection operation consists of dividing a segment of the serial data stream corresponding to a data block by the error check polynomial and determining the remainder of the division operation. The remainder from this initial error division operation is stored. Error correction is then performed on the data stored in the buffer memory, for example using a Reed-Solomon code. When erroneous bytes are identified by the error correction circuitry, the error equations are solved to determine the error pattern and then the erroneous byte is overwritten in the buffer memory. The location of the erroneous byte within the serial data stream, along with the error pattern of the byte, are then used to calculate a correction to the remainder from the initial error division by the error check polynomial on the read in data stream. Error correction continues until the remainder is reduced to a zero value. At this point, it is assumed that all of the errors have been corrected and the data stored in the buffer memory is provided to the data bus of the host computer.

Independent Claim 1 — Plain-Language Overview

A method of transferring data from an optical disk mass-storage system to a host computer, comprising:

1. Retrieving a data string from the storage system and converting it into a form storable in digital memory;
2. Feeding the retrieved/converted data string into a buffer memory for storage, while concurrently feeding that same data string to a first error-detection circuit;
3. Running a first error-detection operation on the data string to see whether errors exist — with at least part of that detection performed while the data are still being written into the buffer memory (this concurrency is the core point);
4. If no errors are found, transferring the data straight out of the buffer memory to the host; and
5. If errors are found, performing an error-correction operation on the data before transferring it to the host.

Independent Claim 14 — Plain-Language Overview

A second, overlapping method claim (independent; claims 15–28 depend from it):

1. Retrieve a data string from the optical disk and store it into a buffer memory;
2. Concurrently with that storing, provide the data string to a first error-detection circuit;
3. Transfer the data out of the buffer memory if the first error-detection operation shows no errors;
4. If errors do exist, perform a first error-detection operation to determine that errors exist and to determine a first error-detection value characteristic of those errors (the stored CRC remainder);
5. Perform an error-correction operation that identifies a first error and determines an error pattern for it;
6. Correct that first error in the data string; and
7. Perform a second error-detection operation to determine whether errors remain in the corrected data string.

Drafting note (literal, no auto-correction): Claim 14's step ordering is internally awkward — it recites "transferring the retrieved data string out of the buffer memory if the first error detection operation determines that no errors are present" before reciting performance of the first error-detection operation itself. I flag this as it appears in the text rather than silently reordering it.

Dependence Structure

• Claims 2–13 depend (directly or indirectly) on claim 1. Notable dependents: claim 5 (detection = division by an error-check polynomial, value = remainder); claim 6 (second detection responsive to error pattern and error location from correction); claim 9 (double-interleaved Reed-Solomon encoded data); claim 10 (detection circuit is a CRC checker); claim 13 (correction performed only after detection determines errors exist).
• Claims 15–28 depend on claim 14. Notable: claim 15 (second detection calculates a correction to the first error-detection value based on the error pattern — the mathematical heart of the patent); claim 17 (second detection value produced by a second detection circuit distinct from the first); claim 21 (no error correction until after the first detection value is stored).

Key Technical Distinction (for context)

The claimed advance over the incorporated-by-reference Verinsky '715 architecture (US 5,581,715, Oak Technology) is that the invention does not re-read the whole ~16,000-bit EDC codeword out of the buffer to re-run CRC after correction. Instead it incrementally updates the stored CRC remainder: R(i+1) = R(i) ⊕ {(e·x^8λ) mod P(x)}, where e is the 8-bit error pattern, λ = (L − l) with L = 2067 (Mode 1) or 2075 (Mode 2 Form 1), per equation (2). FIG. 9 implements this with a three-stage polynomial multiplier splitting λ into λ8·2⁸ + λ4·2⁴ + λ0.

Litigation / Docket Findings (grounded, with sources)

• The Google Patents record flags "Family has litigation – First worldwide family litigation filed," linking to a Darts-ip family ID 26713857.
• Sanyo Electric Co. v. MediaTek (C.D. Cal.): Per MediaTek's Q4-2005 Consolidated Results, Sanyo sued on 2005-04-07 alleging infringement of US 5,499,252 and 5,818,801; MediaTek moved to add a counterclaim asserting US 6,003,151, and the Central District of California granted that motion on 2006-12-05. Source: https://www.mediatek.com/hubfs/MediaTek%20Assets/Pdfs/Financial%20Reports/2005/Q4-Consolidated-Results.pdf
• Oak Technology / Zoran v. MediaTek (ITC § 337 and N.D. Cal.): ITC Pub. 3251 (the '715 investigation) records that MediaTek's CD-ROM controller performs conventional CRC remainder generation before error correction and then updates that remainder during and after error correction, and that this was found non-infringing under the doctrine of equivalents against Oak's '715 claim 1. The 6,003,151-consistent architecture is expressly the accused/non-infringing design described there. Source: https://www.usitc.gov/publications/337/pub3251.pdf
• A National Taiwan University thesis tabulates 6,003,151 among the four patents MediaTek asserted in infringement litigation (alongside 6170043, etc.), noting it carried the highest CPP, SL, and TCT citation-quality metrics of MediaTek's asserted set.
• MediaTek later pursued Zoran/Oak in ITC and D. Del. (2004-07-23) on patents 6,229,773 and 5,970,031, amended to add 6,170,043 and Sunext Technology; those matters were settled/dismissed.

Explicit Uncertainties

• No CAFC 2026 docket exists that I could find for this patent. The patent's anticipated expiration was 2017-03-24 and it is marked "Expired – Fee Related," making live 2026 appellate activity highly improbable; I will not invent one.
• I do not have an authoritative records-based confirmation of the exact outcome of the Sanyo counterclaim beyond the 2006-12-05 grant of leave to add it.
• The UMC→MediaTek assignment discrepancy noted above is reported as-is, un-reconciled.
• Google Patents' "Claims (28)" count and the two independent claims (1 and 14) are taken from the supplied authoritative text; FreePatentsOnline's rendering matches on claim numbering.

Primary sources cited: https://patents.google.com/patent/US6003151/en · https://www.freepatentsonline.com/6003151.html · https://uspto.report/patent/grant/6003151 · https://patentimages.storage.googleapis.com/b8/ea/85/4b40e874641490/US6003151.pdf · https://www.usitc.gov/publications/337/pub3251.pdf

I'll search for litigation involving US patent 6003151 across patent litigation databases.

Found significant leads. Let me dig deeper into the specific cases.

Excellent leads found. Let me search for more specifics on the district court cases and any additional litigation.

Known litigation involving U.S. Patent No. 6,003,151

Patenting basics (from the authoritative full text): U.S. 6,003,151, "Error correction and detection system for mass storage controller," inventor Cheng-Te Chuang, filed Mar. 24, 1997 (priority Feb. 4, 1997, provisional 60/037,157), granted Dec. 14, 1999; originally assigned to United Microelectronics Corporation, assignment recorded to MediaTek Inc. on Apr. 19, 1999. Status: expired (fee related, anticipated expiration Mar. 24, 2017). Google Patents flags the family as "has litigation" (Darts-IP family ID 26713857), but that Darts-IP record itself was not retrievable in my searches.

Confirmed litigation

1. Sanyo Electric Co., Ltd. v. MediaTek Inc., et al. — MediaTek counterclaim asserting the '151 patent

Grounding:

• MediaTek's audited financial statement states: "On April 7, 2005, Sanyo Electric Co. ("Sanyo") filed a complaint with the Central District of California, USA, alleging certain of the Company's chips infringed two of its US patents (Pat. No. 5499252 and 5818801)... The Company filed a motion to add a counterclaim with one US patent (Pat. No. 6003151), seeking damages and injunctive relief against any and all of Sanyo's infringing products. The Central District of California granted the Company's motion on December 5, 2006." — MediaTek 2005 Q4 consolidated results, https://www.mediatek.com/hubfs/MediaTek%20Assets/Pdfs/Financial%20Reports/2005/Q4-Consolidated-Results.pdf
• MediaTek's 2006 Q3 report (Chinese) states MediaTek counter-sued Sanyo on the '151 patent in the Central District of California on 民國94年11月28日 (Nov. 28, 2005), and the court accepted the counterclaim on 民國94年12月5日 (Dec. 5, 2005). It also notes Sanyo's own counter-counterclaims (U.S. 6,594,213 and 6,487,616) were later jointly dismissed by that court on 民國95年4月28日 (Apr. 28, 2006). — https://www.mediatek.com/hubfs/MediaTek%20Assets/Pdfs/Financial%20Reports/2006/Q3-Report.pdf
• Date discrepancy to flag: the audited accounts render the leave date as "December 5, 2006," while the 2006 Q3 filing says Dec. 5, 2005. I cannot resolve this from the sources available; treat the exact grant date as uncertain.
• The district-court docket is likewise reflected in the Markman ruling in Sanyo Electric Co. Ltd. v. MediaTek Inc., No. CV 05-2580 RSWL (JTLx) (C.D. Cal. Aug. 17, 2006) — https://ipmall.law.unh.edu/sites/default/files/hosted_resources/Markman/pdfFiles/2006.08.17_SANYO_ELECTRIC_CO_LTD_v._MEDIATEK.pdf
• Settlement of both suits: Law360 interview with counsel (Stephen S. Korniczky) describing MediaTek Inc. v. Sanyo Electric Co. (E.D. Tex.): "the parties agreed to settle both suits" the night before opening argument — https://www.sheppardmullin.com/assets/htmldocuments/1191.pdf

Related but distinct companion case (does NOT appear to assert the '151 patent):

Source: Second Amended Complaint, https://insight.rpxcorp.com/litigation_documents/[2377627](/patent/2377627)

Unconfirmed / possible additional litigation

• A National Taiwan University master's thesis lists the '151 patent among patents "MediaTek has asserted in infringement litigation" (聯發科於侵權訴訟曾主張之專利), and separately notes that the '151 patent had the highest CPP/SL/TCT indicator values among MediaTek's asserted patents. This is consistent with the 2005 Sanyo counterclaim above, but the thesis also associates MediaTek's asserted patents with a favorable 1999 outcome, raising the possibility that the '151 patent was asserted in the earlier Oak Technology/UMC/MediaTek dispute (N.D. Cal. Case No. C 97-20959 RMW consolidated with C 97-21126 RMW; parallel ITC Inv. No. 337-TA-409). I could not confirm that the '151 patent was actually asserted in that 1997–2002 Oak/UMC litigation — the ITC and Federal Circuit records I located concern Oak's U.S. 5,581,715 (the '715 patent), and the accused MediaTek "Error Detection Processor" there is the technology described in the '151 specification, not an assertion of the '151 patent. — https://theses.im.ntu.edu.tw/thesis/download?filename=r90725013_master_19d58ced-b4c8-40dd-a426-7e7ec24e9003 ; Oak Tech., Inc. v. Int'l Trade Comm'n, 248 F.3d 1316 (Fed. Cir. 2001); https://www.usitc.gov/publications/337/pub3251.pdf

Summary

The only litigation I can confirm in which U.S. 6,003,151 was actually asserted is MediaTek's counterclaim against Sanyo Electric Co. in Sanyo Electric Co., Ltd. v. MediaTek Inc., No. CV 05-2580 RSWL (JTLx) (C.D. Cal.) — a counterclaim added in late 2005 to the C.D. Cal. action, which was settled before trial along with MediaTek's parallel E.D. Tex. case (No. 6:05-cv-323). Patent owner MediaTek (successor to original assignee UMC) appears to have been the asserting party in every instance; I found no case in which the '151 patent was asserted against MediaTek, and no PTAB/IPR or CAFC appeal specifically addressing the '151 patent.

Caveats: (1) I was unable to open the Darts-IP litigation-family record referenced by Google Patents, so there may be additional foreign or U.S. actions not reflected here. (2) The grant date of leave to add the '151 counterclaim is inconsistently reported (Dec. 5, 2005 vs. Dec. 5, 2006). (3) Docket-level confirmation from PACER/CourtListener for the '151 counterclaim specifically was not obtained; the C.D. Cal. case number and the Sanyo party alignment are confirmed, but I did not independently retrieve the counterclaim docket entry itself.

I'll start by verifying the ODP's "no proceedings" result against public sources.

Let me run more targeted checks for PTAB dockets and any AIA trial involving this patent.

Let me do final confirmation searches, including for any related post-grant or reexam activity.

PTAB Proceedings — U.S. Patent No. 6,003,151

Patent: "Error correction and detection system for mass storage controller"
Inventor: Cheng-Te Chuang | Original assignee: United Microelectronics Corporation (assigned to MediaTek Inc. 1999-04-19)
Priority: 1997-02-04 (provisional 60/037,157) | Filed: 1997-03-24 | Granted: 1999-12-14
Claims: 28 (independent claims 1 and 14; claims 2–13 depend from claim 1; claims 15–28 depend from claim 14)
Legal status (ODP/Google Patents): Expired – Fee Related; anticipated expiration 2017-03-24

Proceedings overview

There are zero AIA trial proceedings on file against U.S. Patent No. 6,003,151 — the USPTO Open Data Portal's structured PTAB record returns no IPR, PGR, or CBM dockets, and my independent web searches surfaced no PTAB proceeding number referencing this patent. No claims have been canceled, none have been sustained in a Final Written Decision, and no petitioner has ever been estopped — because no trial was ever instituted. The bottom line for a defendant is therefore not "the patent is hardened by surviving IPRs" and not "the claims are dead." It is the less common (but in this case decisive) posture that the patent expired on 2017-03-24 and can no longer be asserted prospectively, so a validity fight before the PTAB is moot; the only live questions are whether any pre-expiration damages window remains and what the file history/litigation record says about claim scope.

Sourcing caveat: The ODP structured block is the canonical list and shows nothing. I could not directly query PTAB E2E or the PTAB "Patent Trial" search UI in this session; my corroborating searches were web-based. If a proceeding was filed very recently and not yet ingesting into ODP, I found no evidence of it. Absent contrary information, treat this as no PTAB activity on file.

No proceedings to report at proceeding-level granularity

There is no {PROCEEDING_NUMBER} — {Petitioner} v. {Patent Owner} entry to populate, no judge panel, no institution decision, no FWD, no settlement, and no CAFC appeal arising from an AIA trial. I will not manufacture a docket number to fill this section.

Strategic summary

Claim status — all 28 claims are UNTESTED at the PTAB. Because no AIA trial was ever instituted, claims 1–13 and 14–28 stand exactly as granted in 1999. There is no PTAB-narrowed claim set, no certificate canceling claims, and no surviving-claim list to point to. Any argument that "claims 1–5 have been canceled" (to borrow the archetype from the task framing) would be false as to this patent — the danger runs the other direction: because it has never been PTAB-tested, there is no administrative precedent on the scope or validity of claims 1 or 14 to lean on.

Estoppel landscape — none. With no instituted IPR/PGR, § 315(e)(2) estoppel never attached to any party, and no privity chain exists to worry about. Practically, this means there is also no useful invalidity record to inherit: a defendant cannot piggyback on an earlier petitioner's grounds, expert declarations, or an FWD's claim constructions. Any prior-art challenge would have to be built from scratch in district court (or, historically, at the PTAB had the patent not expired).

The expiration date is the controlling fact. The patent's anticipated expiration was 2017-03-24, and its ODP status is "Expired – Fee Related." Expiration extinguishes prospective infringement liability. A demand letter asserting this patent in 2026 is therefore on very thin ice: the only conceivable exposure is past damages for infringement occurring before expiration, and even that is subject to the six-year damages lookback of 35 U.S.C. § 286 (which, measured from 2026, reaches only back to 2020 — a period during which the patent had already expired). Do not concede the point without checking the actual term computation and any PTA/PTE, but on the face of the ODP record, there is no live damages window.

Litigation, not PTAB, is where this patent's history lives. The patent's enforcement history is district-court and ITC activity by MediaTek as asserting patent owner — the opposite of the NPE-assertion pattern the task template anticipates:

• MediaTek filed an ITC complaint and Delaware district court action in July 2004 against Zoran and Oak (later adding Sunext) over U.S. Pat. Nos. 6,229,773; 5,970,031; and 6,170,043 — not the '151 patent. (Source: MediaTek Q4-2005 financial report note (c).)
• MediaTek asserted U.S. 6,003,151 as a counterclaim against Sanyo in the Central District of California (Sanyo's complaint filed 2005-04-07; MediaTek's motion to add the counterclaim granted 2006-12-05). (Source: MediaTek Q4-2005 financial report note (B).)
• A 2006 MediaTek report also describes the patent as one asserted in MediaTek's infringement litigation, along with 6,170,043. (MediaTek Q4-2006 financial report.)

These sources are MediaTek's own SEC-style financial statement notes and secondary analyses, not court dockets; treat the litigation dates as corroborating context rather than a certified docket. Critically, none of this is PTAB activity, and none of it involved a validity challenge to the '151 patent in an AIA trial.

Pattern signals: No repeat petitioner (there is no petitioner at all). No patent-owner PTAB appeal strategy (nothing to appeal). No defensive aggregator (no Unified Patents or RPX docket against the '151). The absence of any IPR is itself a signal worth reading carefully: the '151 was asserted in the mid-2000s, before the AIA created IPR (effective 2012-09-16), and by the time IPR was available the patent was within roughly five years of expiration — a combination that plausibly explains why no one bothered, rather than any implication that the claims are unusually strong.

Recommended next steps

• If you have received a demand letter citing U.S. 6,003,151: verify the expiration date first. The ODP record shows "Expired – Fee Related" with anticipated expiration 2017-03-24. Confirm the full term at Patent Center and check for any terminal disclaimer, PTA, or PTE that could shift the date. If expiration stands, prospective infringement is off the table.
• Assess the § 286 damages window. Damages are limited to six years before suit. Suit in 2026 reaches back only to 2020 — after expiration. Unless the demand is tied to a complaint actually filed earlier (unlikely for a 2017-expired patent), there is no recoverable period.
• Do not over-invest in an IPR/PGR strategy. There is no PTAB proceeding to intervene in, no estoppel to exploit, and — because the patent is expired — the PTAB is not a viable forum at this point. Any budget is better spent on (a) confirming expiration/term and (b) reviewing the 2005–2007 Sanyo counterclaim record for any claim-construction positions MediaTek took on claims 1 and 14.
• Existing proceedings/trial milestones: none — there are no pending PTAB proceedings, so there is no institution-deadline, oral-hearing, or statutory one-year FWD date to track.
• If you want to be certain: run the patent number directly through USPTO PTAB E2E and the PTAB Decisions search to confirm the null result independently, since my confirmation was ODP-plus-web rather than a direct E2E query.

Honest limitations: I found no PTAB proceeding and no Federal Circuit appeal from any PTAB proceeding. I did not verify the litigation record against PACER or CourtListener dockets, and I did not confirm whether the Sanyo counterclaim produced any appeal. If you need certified litigation facts (e.g., for an estoppel or res judicata analysis in district court), pull the C.D. Cal. and E.D. Tex. dockets directly rather than relying on MediaTek's financial-report summaries.

I'll research the assignment record for US 6003151 before drafting. Let me pull from the primary sources.

Key finding already: MediaTek asserted this patent itself against Sanyo. Let me verify the assignment reel/frame and the UMC→MediaTek corporate relationship.

Let me try to pin down the reel/frame and confirm no later transfers.

Assignment Record Reconstruction — US 6003151

Patent: US 6003151 A — "Error correction and detection system for mass storage controller"
App. No.: 08/823,423 · filed 1997-03-24 · priority to provisional 60/037,157 (1997-02-04) · granted 1999-12-14
Status: Expired – Fee Related (anticipated expiration 2017-03-24)

Data-quality caveat up front: I could not retrieve the Assignment Center detail page (reel/frame, execution date, correspondent) directly — the Assignment Center UI is not crawlable through the search tools available to me, and no mirror (uspto.report, FreePatentsOnline, Justia) surfaced the reel/frame in its public HTML. Everything below is grounded in the Google Patents legal-events register (which is derived from the same USPTO assignment feed) and in MediaTek's own SEC-style financial-statement disclosure of the 2005–2006 Sanyo litigation. Reel/frame numbers and the correspondent of record are marked UNVERIFIED; verify them on the Assignment Center before relying on them.

Inventors

• The provisional (60/037,157, 1997-02-04) and the non-provisional (08/823,423, 1997-03-24) both predate MediaTek's incorporation on 1997-05-28. The invention therefore originated inside UMC's consumer/design group.
• Unusual-pattern note: the "inventor departs within 12 months" fire-sale tell is not what happened here. The inventor and his work moved as part of a corporate spin-off — UMC's multimedia/consumer-IC group was split out and incorporated as MediaTek on 1997-05-28 (MediaTek corporate history; EE Times, "Taiwan's MediaTek files DVD chip suit against AOpen and Via"). The same inventor, Cheng-Te Chuang, appears again on MediaTek-owned continuations in this family (US 6751771; US 2004/0205442; US 2009/0037793), confirming he stayed with the spun-out entity rather than leaving.
• Sole named inventor — no co-inventor split that would complicate chain of title.

Original assignee

MediaTek Inc. is the assignee named on the face of the issued patent (Google Patents lists MediaTek Inc. as both current and original assignee; the 1999-04-19 assignment record identifies United Microelectronics Corporation as the assignor, i.e. UMC was the pre-issuance owner).

• Product embodiment: Yes, strongly. MediaTek's founding business was exactly this subject matter — optical-storage controller/decoder chipsets for CD-ROM, CD-RW and DVD drives. MediaTek's own financial statements describe it as designing, manufacturing and supplying "integrated circuit chips and decoders," and the company held roughly 60% of the Taiwanese DVD chipset market by 2001. This patent is a CD-ROM/DVD controller error-correction architecture, i.e. core product IP.
• Primary line of business: fabless semiconductor design (Hsinchu, Taiwan). Now a top-tier SoC vendor (smartphone, TV, connectivity). Listed on TWSE as 2454 since 2001-07-23.
• Current status: Operating. Publicly traded, no bankruptcy, no dissolution, no acquisition. Still the owner — no assignment off the original family was ever recorded.

Assignment timeline

Only one post-filing assignment is recorded in the Google Patents legal-events register. Chronologically:

• Execution date UNVERIFIED / recorded 1999-04-19 — Reel UNVERIFIED / Frame UNVERIFIED
  • Conveyance: Assignment (Google Patents logs it as a "reassignment"; the USPTO type string is an assignment of assignor's interest — not independently confirmed)
  • Assignor: United Microelectronics Corporation
  • Assignee: MediaTek Inc.
  • Correspondent: UNVERIFIED — not exposed by any source I could reach. Cannot be assessed for recurrence; do not treat as either present or absent.
  • Context: internal corporate reorg / spin-off clean-up. UMC spun its design group out into MediaTek on 1997-05-28; this April 1999 recording papered the patent over to the new entity about 8 months before grant. Not a sale, not securitization, not a transfer-to-asserter.

For completeness, the other register entries (not assignments):

• 1997-03-24 — application filed; priority to US 08/823,423 claimed.
• 1999-12-14 — application granted; US 6003151 A published.
• 2017-03-24 — anticipated expiration; status "Expired – Fee Related."

No later assignments of any kind. No transfer to an IP-holding subsidiary, no security agreement, no merger conveyance, no change of name. The chain is UMC → MediaTek and stops.

Timeline diagram

timeline
    title Ownership of US 6003151
    1997 : Provisional filed 1997-02-04
         : Application filed 1997-03-24 by UMC
         : MediaTek spun out of UMC
    1999 : UMC assigns patent to MediaTek
         : Patent granted 1999-12-14
    2005 : MediaTek asserts patent against Sanyo
    2006 : Counterclaim granted in CD California
    2017 : Patent expired 2017-03-24

NPE / troll-pattern signals

On the "privateering" and "operating-company assertion" distinction — the one substantive litigation fact worth recording: MediaTek asserted US 6003151 offensively as a counterclaim against Sanyo Electric in the Central District of California. MediaTek's own Q4-2005 and Q4-2006 financial statements disclose that Sanyo sued MediaTek on 2005-04-07 (US 5,499,252 and 5,818,801), that MediaTek moved to add a counterclaim on US 6003151, and that the Central District of California granted that motion on 2006-12-05. MediaTek separately sued AOpen and VIA over DVD chipset patents (EE Times) and filed an EDTex action against Sanyo and Sanyo North America on 2005-08-31 (US 5,867,819, US 6,118,486). This is classic operating-company-versus-competitor assertion in a chipset market both parties actually sold into — no shells, no patent-only plaintiff.

Verdict

Operating-company assertion.

The patent was filed by UMC's design group in March 1997, moved to the spun-out MediaTek by a single recorded assignment on 1999-04-19, and never left MediaTek's hands — no reel entry after that one, no NPE, no IP-holding subsidiary, no defensive aggregator. MediaTek is a publicly listed fabless semiconductor vendor that shipped optical-drive controller chipsets embodying the CD-ROM/DVD error-correction architecture claimed here, and it asserted the patent in its own name as a counterclaim against competitor Sanyo, a motion the Central District of California granted on 2006-12-05 (MediaTek Q4-2006 financial statements). Zero NPE signals are present; the most probable complete ownership history is a two-step intra-corporate chain terminating at an operating company, and the patent simply expired on 2017-03-24.

Verify the reel/frame, execution date, and correspondent on the Assignment Center before relying on this — that single unresolved field is the one gap in the above:
https://assignmentcenter.uspto.gov/ (search patent number 6003151)
Google Patents legal events for cross-check: https://patents.google.com/patent/US6003151/en

I'll verify the patent and its cited references against live sources before analyzing.

Let me pull details on the remaining cited references to characterize them accurately.

Prior-Art Analysis — U.S. Patent No. 6,003,151

Analysis date: 2026-04-26 · Source of record: full patent text at https://patents.google.com/patent/[US6003151](/patent/US6003151)/en (fetched 2026-09-28 in the corpus) plus live verification searches

1. The patent under analysis

Critical dates for §102: every reference must predate the 1997-02-04 priority date to be §102(a)/(b) art (subject to the 1997-03-24 filing date for §102(b)/§102(e) analysis). All eleven patent citations do.

The claimed invention's point of novelty (from the specification and the claim language):

1. The read-in bitstream is fed concurrently to the buffer memory and to an error-detection (CRC/EDC) circuit, so the first EDC runs while the sector is being stored (claim 1, claim 14, claim 19).
2. The first EDC remainder (CRC₀) is retained rather than discarded (claims 3, 5, 22).
3. After each ECC correction, the stored remainder is incrementally corrected using the error pattern e and error location λ — R_i+1 = R_i ⊕ {(e·x^8λ) mod P(x)} (Eq. 2) — and tested for zero (claims 4, 6, 15, 16, 23), rather than re-reading the buffer through a CRC checker.

Because claims 7–13 and 15–28 all depend from claim 1 or 14, no single reference can anticipate any dependent claim without first anticipating claim 1 or claim 14 in full.

2. Methodology and confidence caveats

• The eleven references listed below are exactly the "Patent Citations (11)" on the face of US 6,003,151. No similar-but-different numbers were substituted.
• I verified full text/abstracts for US 5,241,546, US 5,604,753, US 5,581,715, and US 4,413,340 via live search. For the remaining citations I relied on the patent's own face-of-record data plus the description US 6,003,151 gives of them (it expressly incorporates '340, '764, '2152 and '715 by reference). I flag those characterizations as lower-confidence below.
• "Potentially anticipates" below means a prima facie §102 case could be pleaded, not that the reference necessarily discloses every element as construed. This is a technical analyst's assessment, not a legal opinion.

3. Reference-by-reference analysis

★ 3.1 US 5,241,546 A — the single most relevant prior art

• Full citation: U.S. Patent No. 5,241,546, "On-the-fly error correction with embedded digital controller," Peterson, Bruce R.; Nguyen, Hung C.; and Machado, Michael G., assigned to Quantum Corporation. Appl. No. 07/650,791.
• Dates: filed 1991-02-01; granted 1993-08-31. (EP counterpart EP 0 497 593 A2/A3/B1; priority US 07/650,791.)
• Brief description (verified): A syndrome generator / remainder-recovery circuit processes the incoming code block while the user bytes are transferred into the block buffer memory; the recovered remainder bytes are compared with zero; if non-zero they are latched in a remainder latch to free the syndrome generator for the next block; a microcontroller then computes the error location and value and substitutes corrected bytes into the block buffer before the block is sent to the host. A Reed-Solomon "cross check" is also recovered, and after a correction the microcontroller computes "Syndrome cross check (XC) = previous (XC) + e_i·α^li," where e_i is the error value and li the error location, and re-tests for zero to confirm that errors have been eliminated and no miscorrection occurred.
• Why it is the closest art: the reference discloses both of the structural ideas that US 6,003,151 claims — (i) error-detection computation on the data stream contemporaneously with filling the buffer, and (ii) updating a stored, latched remainder by an e·α^l correction term after each correction and testing the result for zero, instead of re-running the full codeword through a checker.
• Potentially anticipates under §102:
• Claim 1 — all elements appear present: retrieval/conversion (sequencer/SERDES), concurrent provision to buffer and to the syndrome/zero-detect circuit, detection performed while storing, transfer to host if remainder is zero, correction before transfer if non-zero.
• Claim 14 — likewise, including "determining a first error detection value" (the latched remainder), "identifying a first error," "determining an error pattern," "correcting the first error," and "performing a second error detection operation to determine if errors remain in the corrected data string" (the cross-check re-test for zero).
• Claims 2, 3, 5, 6, 11, 12, 13, 18, 19, 20, 21, 22, 23, 26, 27, 28 — each element is disclosed by the same disclosure (remainder = polynomial division; RS decoder; XOR of correction value into the erroneous byte; ECC begun only after the non-zero remainder is latched; "no error" release for host transfer).
• Claims 4, 15, 16, 17 (arguable) — '546 teaches computing a correction to a stored detection value based on the error pattern and location, updating it, and testing non-zero. The mismatch to be argued is that '546's updated quantity is a cross-check syndrome over G(x) = x² + α¹, whereas claims 14–16 speak of correcting "the first error detection value." Under a broad reading these read on '546; under a narrow reading they are at minimum strong §103 art.
• Does NOT anticipate: claims 7, 8, 9, 10, 24, 25 — '546 is a magnetic disk drive: no CD-ROM digital signal processor, no descrambler, no CRC-based EDC, and its RS code is a three-interleave code rather than the CD double-interleaved product code.

★ 3.2 US 5,581,715 A — second most relevant (the claimed environment)

• Full citation: U.S. Patent No. 5,581,715, "IDE/ATA CD drive controller having a digital signal processor interface, dynamic random access memory, data error detection and correction, and a host interface," Verinsky, Phil et al., Oak Technologies, Inc. Appl. No. 08/264,361 (continuations include US 6,968,404 B2, US 7,124,216 B2).
• Dates: filed 1994-06-22; granted 1996-12-03. (EP counterpart published as EP 0 689 207 A1.)
• Brief description (verified): A CD-ROM drive controller with (a) a DSP interface including a descrambler that descrambles/assembles the DSP digital information and stores it into the random access memory, (b) a DRAM controller, (c) an ECC data corrector (Reed-Solomon stated as an option), (d) an EDC device employing cyclic redundancy checking (EDC/CRC), and (e) an IDE/ATA host interface. The related EP disclosure expressly states the CRC is used "for detecting errors in the digital information after correction of the digital information by the error correction code circuit."
• Significance: US 6,003,151's own FIG. 1 and Background are drawn from this controller; the patent characterizes '715 as the conventional arrangement to be improved, in which all ECC operations run before EDC, and the corrected sector must be re-read for EDC.
• Potentially anticipates under §102:
• Claims 7 and 8 — digital signal processor operations plus a descrambler that supplies data to the data organizer/buffer: directly disclosed.
• Claims 10 and 25 — "first error detection circuit is a cyclic redundancy code checker": disclosed.
• Claims 9 and 24 — CD-ROM data; double-interleaved RS coding is disclosed in the CD-ROM context.
• Claims 11, 12, 26, 27 — Reed-Solomon ECC corrector; error patterns applied to erroneous data.
• Claim 1 / claim 14 — NO (not anticipated): '715 performs the CRC after correction, not concurrently with buffer storage, and does not retain/correct a first EDC remainder. This is precisely the gap US 6,003,151 fills. '715 is, however, the key §103 combination partner with US 5,241,546.

3.3 US 4,413,340 A (Odaka et al. / Sony)

• Full citation: U.S. Patent No. 4,413,340, "Error correctable data transmission method," Odaka, Kentaro; Sako, Yoichiro; Iwamoto, Ikuo; Doi, Toshitada; and Vries, Lodewijk B., Sony Corporation. JP priority 1980-05-21 (JP 55-067608).
• Dates: US filed 1981-11-12; granted 1983-11-01.
• Brief description (verified): The foundational cross-interleaved Reed-Solomon (CIRC) encoding/decoding system — data words are interleaved in two stages with two generations of check words satisfying a Reed-Solomon parity matrix; decoding generates syndromes and corrects burst/random errors. Acknowledged in the error-correction literature as the CIRS source for CD audio/CD-ROM.
• Potentially anticipates under §102: no whole claim (§102 exposure is element-level only). Supplying elements of claims 9 and 24 (double-interleaved Reed-Solomon encoding), claims 11 and 26 (RS decoding to determine error location/pattern), claims 12 and 27 (correcting by adding an error pattern). Because claims 9/11/12 depend on claim 1, this reference functions as §103 art, not a standalone §102 anticipation. US 6,003,151 itself incorporates it by reference for conventional EDC/ECC.

3.4 US 4,680,764 A (Suzuki et al. / Sony)

• Full citation: U.S. Patent No. 4,680,764, "Method and apparatus for transmitting digital data," Suzuki et al., Sony Corporation. Filed 1984-03-24; granted 1987-07-14.
• Brief description (from US 6,003,151's own discussion, which incorporates it by reference): Conventional CD-ROM error encoding, error correction and error detection: appending EDC bytes so that the block is divisible by the check polynomial, and performing the CRC division with shift registers and XOR feedback (the FIG. 5-type serial CRC decoder), together with Reed-Solomon correction. Lower-confidence — I was unable to retrieve the full text in this session; the characterization rests on the citing patent's description.
• Potentially anticipates under §102: no whole claim. Element-level §102 relevance for claims 5 and 22 (dividing the retrieved data string by an error check polynomial and treating the remainder as the detection value) and claims 10 and 25 (CRC checker). Again dependent claims ⇒ §103 art.

3.5 US 4,730,321 A (Machado / Quantum)

• Full citation: U.S. Patent No. 4,730,321, "Disk drive with improved error correction code," Machado, Michael G., Quantum Corporation. Filed 1986-05-30; granted 1988-03-08.
• Brief description (established through the verified description of it in US 5,241,546, which cites and builds on it): an internal-form Galois-field syndrome generator used both for encoding and as a remainder-recovery circuit; error correction is performed by the drive microcontroller using a DMA channel to access the already-existing data block buffer and overwrite erroneous bytes. Data flow is stopped on detection of an error (the non-"on-the-fly" approach).
• Potentially anticipates under §102: no whole claim. Element-level relevance to claims 12 and 27 (adding an error pattern to erroneous data), claims 13 and 28 (identifying/correcting errors in the data stored in the buffer memory only after an error is detected), and claims 11 and 26 (RS decoding). §103 art.

3.6 US 4,802,152 A (Markvoort et al. / U.S. Philips)

• Full citation: U.S. Patent No. 4,802,152, "Compact disc drive apparatus having an interface for transferring data and commands to and from a host controller," Markvoort, W. et al., U.S. Philips Corporation. Filed 1986-04-07; granted 1989-01-31.
• Brief description: a CD drive with a host-controller interface for both commands and data — the CD-drive-to-host data path architecture. Lower-confidence as to internal detail; incorporated by reference by US 6,003,151 for background.
• Potentially anticipates under §102: none as a whole. Element-level environment for claim 1 / claim 14 (retrieving data from an optical disk mass storage system and transferring it to a host) and possibly claims 7 and 8 (CD drive data path). §103/background art only.

3.7 US 5,379,305 A (Digital Equipment Corporation)

• Full citation: U.S. Patent No. 5,379,305, "Error correction system with selectable error correction capabilities," Digital Equipment Corporation. Filed 1992-07-20; granted 1995-01-03.
• Brief description: an error-correction system in which the level/type of error correction applied is selectable — i.e., correction effort is conditioned on the detected error situation. Lower-confidence as to internal detail (title/face-of-record only).
• Potentially anticipates under §102: none as a whole. Most relevant to claims 13 and 28 (performing the ECC only after the detection operation determines the existence of one or more errors) and to the specification's stated advantage of "elimination of unnecessary data correction operations." §103 art.

3.8 US 5,563,896 A (Fujitsu Limited)

• Full citation: U.S. Patent No. 5,563,896, "Error correction processor and an error correcting method," Fujitsu Limited. Filed 1991-01-22; granted 1996-10-08.
• Brief description: an ECC processor/method for locating and correcting errors in codewords. Lower-confidence as to internal detail (title/face-of-record only).
• Potentially anticipates under §102: none as a whole. Element-level relevance to claims 11 and 26 (RS decoder identifying the error), claims 12 and 27 (adding an error pattern to erroneous data). §103 art.

3.9 US 5,604,753 A (Intel Corporation)

• Full citation: U.S. Patent No. 5,604,753, "Method and apparatus for performing error correction on data from an external memory," Intel Corporation. Filed 1994-01-04; granted 1997-02-18.
• Brief description (verified): data read from an external memory (L2 cache) is forwarded to the requesting unit while error correction is performed in parallel; a single-bit (Hamming-type) error is corrected and the corrected data forwarded on the next cycle, with the pipeline/execution core purged of results computed on faulty data.
• Potentially anticipates under §102: none as a whole — it is a cache-memory context, uses Hamming rather than a CD-ROM Reed-Solomon product code, and forwards data before knowing whether it is correct (the opposite of claim 1's "transfer only if no errors are present"). It is relevant §103 art for (i) the motivation to run detection/correction in parallel with data handling, and (ii) the error-indication/flush behaviour. Best mapped as general art against claims 1, 2, 14, 20.

3.10 US 5,617,384 A (Sony Corporation)

• Full citation: U.S. Patent No. 5,617,384, "Method and apparatus for recovering TOC and user information from an optical disk and using the TOC information to access user tracks," Sony Corporation. Filed 1994-03-19; granted 1997-04-01.
• Brief description: optical-disk read/recovery of table-of-contents and user information, using TOC data to access user tracks. Lower-confidence as to internal detail (title/face-of-record only).
• Potentially anticipates under §102: none as a whole; no disclosure of concurrent EDC/ECC or remainder updating. At most background art for the optical-disk retrieval step of claim 1 / claim 14. Low relevance.

3.11 Non-patent citation

• Citation: Microsoft Press, Computer Dictionary, 3rd Edition, 1997, p. 104 (cited by examiner).
• Nature: a dictionary entry (p. 104 of that edition covers terms in the "C" range, consistent with a definition of "cyclic redundancy check"/"CRC" or a related acronym). It is cited for claim construction / definitional support, not as §102 art. It cannot anticipate any of claims 1–28. (Note: it postdates the 1997-02-04 priority date by publication, but dictionary citations are used for construction, not prior-art effect.)

4. §102 claim-mapping summary

5. Bottom line

1. Most relevant prior art: U.S. 5,241,546 (Peterson/Nguyen/Machado, Quantum Corporation; filed 1991-02-01, granted 1993-08-31). It is the only cited reference that discloses both limbs of the US 6,003,151 concept: ECC-remainder computation on the incoming block while the user bytes are transferred into the block buffer, and post-correction updating of a stored remainder by an e·α^l term with a zero test in place of a full re-read. It presents a genuine §102 exposure for independent claims 1 and 14 and most of their dependents.
2. Second: U.S. 5,581,715 (Verinsky/Oak Technologies; filed 1994-06-22, granted 1996-12-03). It is the CD-ROM/IDE controller architecture that US 6,003,151 adopts as its starting point, and supplies the elements '546 lacks (DSP + descrambler, buffer/DRAM controller, CRC-based EDC, IDE host interface). It does not anticipate claims 1 or 14 — it runs CRC after ECC — but with '546 it is the central §103 combination.
3. The remaining references are element-level art: the Sony cross-interleaved Reed-Solomon/EDC pair ('340, '764) and the Quantum buffer/DMA ECC reference ('321) supply the coding and buffering elements; DEC '305, Fujitsu '896, Intel '753 and the Philips/Sony documents ('152, '384) supply selective-correction, ECC-processor, parallel-operation and CD-drive-environment elements respectively. None is a standalone §102 anticipation of an independent claim.
4. The dictionary citation is claim-construction material, not prior art.
5. Do not treat the "Cited By" lists (47 and 127 documents) as prior art for this patent. Those are later publications; the ones in MediaTek/Chuang's own continuation lineage (e.g., US 6,751,771 B2; US 8,166,369 B2; US 2009/0037793 A1 — "Method for error processing in optical disk memories," Cheng-Te Chuang) share the inventor/family and are not §102 art against US 6,003,151.

Uncertainty disclosure: I fully verified the content of US 5,241,546, US 5,604,753, US 5,581,715 and US 4,413,340. For US 4,646,303, US 4,680,764, US 4,730,321, US 4,802,152, US 5,379,305, US 5,563,896 and US 5,617,384 my descriptions rest on the face-of-record data in US 6,003,151 (including the portions that patent expressly incorporates by reference) and on the description of '321 contained in the verified text of '546; I could not retrieve each of their full specifications within this session's search budget. Any of those characterizations should be re-verified against the individual specifications before being relied on in a validity or infringement contention.

I'll research the prior art references cited on the patent page before building the § 103 analysis.

Let me research the remaining cited references.

Obviousness Analysis — U.S. Patent No. 6,003,151

"Error correction and detection system for mass storage controller"
Inventor: Cheng-Te Chuang · Assignee: MediaTek Inc. (originally United Microelectronics Corp.)
Provisional priority: Feb. 4, 1997 (Ser. No. 60/037,157) · Filed: Mar. 24, 1997 · Granted: Dec. 14, 1999

Note on scope: I was asked to use the Prior Art section of the patent page. That section comprises the 11 "Patent Citations" (examiner-cited) and the single Non-Patent Citation. I treat those as the § 103 prior-art universe below. The "Cited By" and "Similar Documents" listings are later-dated art and are addressed only as corroboration; they are not independently relied on. Where my search of a reference was cut short, I say so.

I. Legal standard and framing

Under 35 U.S.C. § 103, a claim is obvious if the differences between the claimed invention and the prior art are such that the subject matter as a whole would have been obvious to a person of ordinary skill in the art at the effective filing date. Under KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007), the analysis asks whether the elements were known in the field, whether there was a known problem for which the combination was an obvious solution, and whether the combination was "obvious to try" with a reasonable expectation of success. A motivation to combine may be found in the references themselves, in the knowledge of a PHOSITA, or in the "market demand" / "design incentive" rationales.

Two structural points matter here:

1. The patent's own background makes substantial admissions. The specification states that descrambling, data organization, buffer storage, error correction and error detection per ISO/IEC-10149 are "generally familiar to those of ordinary skill in the art," that Reed-Solomon P/Q parity and the CRC check polynomial P(x) = (x¹⁶+x¹⁵+x²+1)·(x¹⁶+x²+x+1) are standard, and — critically — that "while the industry standards … require both error correction and error detection, the particular structure illustrated in FIG. 1 is not mandated by the standards." That is an admission that the ordering/architecture is a design choice.
2. The independent claims are method claims directed to an architectural re-ordering plus one computational feature. Claims 1 and 14 cover (a) concurrent EDC during buffer write, (b) skip ECC and transfer if no error, (c) run ECC only if an error is detected, and (d, claim 14) capture an error-detection value. The genuinely distinctive computational feature — updating the stored EDC remainder from the ECC error location/pattern instead of re-dividing the codeword — appears only in claims 4 and 6 (via claim 3) and in claims 15–17 and 23.

II. Person of ordinary skill in the art (PHOSITA)

At the Feb. 4, 1997 priority date, a PHOSITA would be a hardware/firmware engineer with a B.S.E.E. or equivalent and 3–5 years of experience designing mass-storage controllers, familiar with: (i) the ISO/IEC-10149 CD-ROM sector format (sync, header, 2048-byte user data, 4-byte EDC, 172-byte P-parity, 104-byte Q-parity); (ii) interleaved Reed-Solomon product codes over GF(2⁸) and their decoding (syndromes, error location, error pattern); (iii) CRC generators built from shift registers and XOR gates; (iv) ATAPI/IDE/ATA host interface design; and (v) buffer-memory management (DRAM/SRAM) in controller ASICs.

III. The prior art of record

IV. Element-by-element mapping of independent claim 1

Conclusion: Every element of claim 1 is disclosed either by Verinsky or by Peterson, and the only element Verinsky lacks (detection concurrent with the write, and the skip-ECC-if-clean path) is expressly taught by Peterson. The combination is a two-reference combination within a single field of endeavor (KSR).

Claim 14 maps essentially identically, adding only "determining a first error detection value characteristic of the errors present." Peterson's remainder latch discloses a stored value characteristic of the error condition.

V. Grounds of rejection / obviousness combinations

Ground 1 — Claims 1, 13, 14, 19, 20, 28: obvious over Verinsky (US 5,581,715) in view of Peterson (US 5,241,546), further in view of Intel (US 5,604,753)

• Verinsky supplies the complete host-side architecture the claims presuppose: a CD-ROM controller with a descrambler/DSP interface, a DRAM buffer memory into which descrambled bytes are assembled and stored, an ECC corrector, an EDC/CRC checker, and an IDE/ATA host interface — i.e., "transferring … to the host computer system." It is in the identical technical field and shares claim 1's preamble.
• Peterson supplies the two missing limitations: (i) performing the check on the incoming stream, in parallel with storage into the buffer, and (ii) not stopping the data stream when the check is clean, i.e., transferring without correction when no error is present, and correcting in the buffer only when the remainder is non-zero. Peterson states the mechanism expressly: the syndrome generator "operates on-the-fly upon the data stream," the remainder is compared to zero, and only a non-zero remainder triggers the correction routine.
• Intel (US 5,604,753) supplies an explicit, articulated motivation: because errors are rare, requiring detection/correction to complete before the data is consumed "is an undue delay," so data should be "forwarded to the requesting unit while the error correction is performed on the data, such that the two operations are performed in parallel." Intel thus teaches the reason a PHOSITA would move the EDC into the write path and eliminate the always-run-ECC bottleneck.
• Claim 13 / 28 ("only after the error detection operation determines the existence of one or more errors" is ECC performed): directly taught by Peterson's zero-comparison gate and by Intel's conditional-flush architecture.
• Claim 19 (data provided to the first error detection circuit while being stored): Peterson's on-the-fly syndrome generation.
• Claim 20 (transfer if no errors): Peterson's clean-remainder path; Verinsky's host interface.

Ground 2 — Claims 2, 3, 5, 18, 21, 22: obvious over Verinsky + Peterson, further in view of Machado (US 4,730,321)

• Claim 2 (correct the error; run a second error detection to decide whether uncorrected errors remain; deliver corrected data on the no-error signal): Peterson discloses cross-checking the correction and delivering the corrected block to the host; Verinsky discloses a CRC that detects errors "after correction of said data by said correction circuitry." The two together teach a post-correction verification gate.
• Claim 3 (first error detection value is stored): Peterson's "latching the recovered information into a remainder latch."
• Claim 5 / 22 (detection = dividing by an error check polynomial; the value is the remainder): Peterson's remainder-recovery circuit performs exactly this polynomial-division-to-remainder operation; Verinsky's cyclic redundancy checker performs the CRC division. The Microsoft Press Computer Dictionary NPT confirms "CRC" was a defined term of art.
• Claim 21 (no correction until after the first detection value is stored): Peterson's sequence — remainder latched first, then the microcontroller's correction service routine is invoked.
• Claim 18 (provide corrected data string to host after correction): Verinsky's corrected-data path to the IDE bus; Peterson's substitution before host delivery.
• Machado (US 4,730,321) corroborates that storing a non-zero ECC remainder and having a controller correct the data in the block buffer memory was known, and provides the buffer-based correction architecture that the '151 specification adopts.

Ground 3 — Claims 4, 6, 15, 16, 17, 23 (the "remainder-correction" claims): obvious over Verinsky + Peterson + Weng (US 5,379,305), with Machado and Intel

This is the narrowest and least certain ground, and it is almost certainly where the examiner's allowance rested. These claims require, in substance:

"calculating a correction to the first error detection value … on the basis of the error pattern determined for the first error" (claim 15); "correcting the first error detection value and storing the corrected first error detection value as a second error detection value and then determining whether the second error detection value is non-zero" (claim 16); "the second error detection operation is responsive to an error pattern and an error location derived by the error correction operation" (claim 6/23); "the second error detection value is determined by a second error detection circuit distinct from the first error detection circuit" (claim 17).

Supporting rationale:

• Weng (US 5,379,305) discloses a syndrome calculator that "iteratively modifies error syndromes" and an error corrector that "iteratively modifies error and erasure values" (its FIGS. 6–9 are flow charts for "iteratively modify[ing]" syndromes and values, including an embodiment that "modifies error syndromes in parallel"). That is the same computational idea the '151 claims recite: rather than recompute a check value from the full codeword, incrementally adjust the stored check value using the error location/value. A PHOSITA would recognize the mathematical equivalence between iteratively updating an RS syndrome and iteratively updating a CRC/EDC remainder (both are polynomial-division remainders over GF(2)), and would apply the technique to the '151's EDC remainder to avoid the very cost the '151 background identifies — re-reading the entire >16,000-bit codeword through the CRC shift register.
• Peterson supplies the stored remainder and the error-location/error-pattern outputs. Machado supplies buffer-based substitution and the error-location/corrected-value computation. Intel supplies the "make detection overlap with the rest of the pipeline" motivation.
• Claim 17 (a second, distinct error-detection circuit) is at most a design choice: Peterson already isolates the remainder latch/controller from the syndrome recovery circuit, and once incremental updating is adopted, a separate small multiplier/modulo datapath logically follows.

Why this ground is weaker than Grounds 1–2: none of the cited references expressly applies an incremental correction to a CRC/EDC remainder — Weng does it to RS syndromes, and Peterson latches the remainder but does not re-derive it as errors are corrected. The "second error detection circuit" and the specific λ-decomposition (λ = λ₈·2⁸ + λ₄·2⁴ + λ₀, three-stage ·x⁸/·x¹²⁸/·x²⁰⁴⁸ multiplier of FIG. 9) are recited only in the specification, not in the claims — but if the claims are construed to require that specific computational pathway via claim differentiation or the doctrine of claim construction in light of the spec, the obviousness case gets materially harder. In litigation, this is where a validity challenge would concentrate, and where MediaTek would argue (a) no reference teaches correcting an EDC remainder, and (b) Weng's syndrome modification is a different data object than a CRC remainder used for detection only.

Ground 4 — Claims 7–12, 24–27 (CD-specific limitations): obvious in view of Odaka (US 4,413,340) and Suzuki (US 4,680,764), with Nippon Gakki Seizo (US 4,646,303), Philips (US 4,802,152) and the Microsoft Press NPT

• Claims 7–8 (digital signal processor + descrambler; descrambler feeds both the error-detection circuit and a data organizer that stores to the buffer): taught essentially verbatim by Verinsky ("descrambler … descramble and assemble the digital information … and store said digital information into said random access memory").
• Claims 9 / 24 (double-interleaved Reed-Solomon code): the ISO/IEC-10149 CD-ROM P/Q product code, described in the '151 background and attributed to Odaka (US 4,413,340) and Suzuki (US 4,680,764); Nippon Gakki Seizo (US 4,646,303) discloses CIRC detection/correction with error-correction and double-error-detection circuits.
• Claims 10 / 25 (CRC checker): Verinsky's EDC/CRC; Microsoft Press Computer Dictionary definition of "cyclic redundancy check."
• Claims 11/26 and 12/27 (Reed-Solomon decoder identifies the error; correction adds an error pattern to erroneous data): Peterson and Machado both compute error location/corrected value and substitute; the '151 specification itself states the error equations and that "correct value = original data pattern ⊕ error pattern." Nippon Gakki Seizo teaches syndrome-based detection plus correction.

VI. Motivation to combine (the KSR rationales)

1. Same field, same problem, same solution type. Verinsky, Peterson, Machado, Intel and Weng are all error-processing/data-transfer controllers for mass storage or memory subsystems. The problem each attacks is identical: maximize data throughput by removing the error-processing bottleneck. The '151 background concedes this bottleneck narrative ("the primary bottleneck … has been the speed at which data are read … operations of the data transfer controller are now, or may soon be, limiting data transfer rates").
2. Explicit teaching in the references. Peterson: detection "operates on-the-fly upon the data stream" and the remainder is latched "to free the syndrome information recovery circuit for the next data block" — i.e., the reference's own design rationale is to overlap detection with streaming and to avoid stopping the flow. Intel: errors are rare, so waiting "is an undue delay"; use data now, verify in parallel.
3. Predictable result. Running detection concurrently with the buffer write, and skipping correction when the check is clean, yields the expected and purely mechanical result of lower latency; no new or unpredictable result is claimed.
4. Recognized design freedom. The '151 specification itself states the standards do not mandate the conventional ECC-then-EDC ordering of FIG. 1, which removes the principal "teaching away" hurdle.
5. Market/demand pressure. The background describes ever-faster CD-ROM rotational speeds and emerging high-density media (explicitly naming DVD, WORM and rewritable optical) as creating pressure to raise controller throughput — a classic design incentive under KSR.
6. Obvious to try. Given a family of known controller architectures in which detection and correction can be sequenced or overlapped in several ways, and a known benefit to overlap, a PHOSITA would have had a reasonable expectation of success in re-sequencing them.

VII. Rebuttal considerations (what a patent owner would argue)

• No express teaching of the specific remainder-correction math. The strongest non-obviousness argument is confined to claims 4/6/15/16/17/23: none of the eleven references of record is shown to compute the correction e·x^{8λ} mod P(x) and XOR it into a stored CRC remainder. Weng's iterative syndrome modification is the closest analogue but operates on RS syndromes, and Peterson's remainder is latched, not updated.
• Potential teaching away. Verinsky's own claim 1 requires CRC detection only "after correction of said data," i.e., a stated order opposite to claims 1/14. A patent owner would argue this is a teaching away from EDC-first. Counter: the '151 background itself acknowledges that ordering is not standards-mandated and is merely conventional; Verinsky's ordering was a design choice driven by its own correctness concerns (CRC as post-correction cross-check), which Peterson and Intel show can be re-ordered for speed without loss of function.
• Secondary considerations. No evidence of unexpected results, long-felt need, or industry praise appears in the record I have. The patent page flags "Family has litigation" (a Darts-IP entry for the family). If a validity challenge occurred, the resulting record — claim constructions, IPR/PGR petitions, and any prior-art findings — would be the most probative evidence on the Ground 3 issues and should be reviewed directly; I have not verified the litigation documents and cannot state with confidence what was decided.
• Patent has expired (anticipated expiration Mar. 24, 2017; status "Expired – Fee Related"), so any § 103 challenge would now have practical significance only for past damages, not for injunctive relief.

VIII. Bottom line

Overall: The independent claims and the architecture/buffer/CRC/CD-format dependent claims are, on this record, strongly vulnerable to a § 103 challenge built from Verinsky + Peterson (+ Intel for motivation). The durable non-obviousness, if any, resides almost entirely in claims 4, 6, 15, 16, 17 and 23 — specifically the incremental correction of a stored EDC/CRC remainder using the ECC error location and error pattern, which the cited art approaches (Weng's iteratively modified syndromes) but does not squarely teach for an EDC remainder.

IX. Confidence and limitations

• I verified the disclosures of US 5,581,715, US 5,241,546, US 5,604,753, US 5,379,305, and US 4,646,303 from search results; citations above are drawn from those documents (e.g., https://patents.google.com/patent/US5581715, https://patents.google.com/patent/US5241546, https://patents.google.com/patent/US5604753, https://patents.google.com/patent/US5379305, https://patents.google.com/patent/US4646303).
• I could not retrieve the full text of US 4,413,340, US 4,680,764, US 4,730,321, US 4,802,152, US 5,563,896 and US 5,617,384 before my search budget was exhausted. For US 4,413,340, US 4,680,764, US 4,730,321 and US 4,802,152 I rely on their titles plus the characterization given in the specification of US 6,003,151 and in US 5,241,546's discussion of Machado '321. US 5,563,896 and US 5,617,384 should not be relied on without full-text review.
• The date of the cited Microsoft Press Computer Dictionary, 3rd ed. page should be confirmed; if it post-dates Feb. 4, 1997 it is not § 102 prior art and should be used only as evidence of the ordinary meaning of "CRC."
• Claim 14's recitation is internally awkward (it recites "transferring … if the first error detection operation determines that no errors are present" before the conditional step of "performing a first error detection operation"). I analyzed it as written and as illuminated by the specification; a court might construe the term more narrowly, which would only help a validity challenger by narrowing the claim.
• Nothing here is a legal conclusion or an invalidity opinion; it is a technical § 103 analysis. A formal opinion would require full-text review of all eleven references, the prosecution history of Ser. No. 08/823,423, and any IPR/PGR or litigation record.