US 5818801

I'll search for current information on this specific patent number.

Let me dig deeper into the litigation history and any Federal Circuit activity.

Let me check for any Federal Circuit appeals and current docket status.

US Patent 5,818,801 — Summary Report

Data sources: Full patent text from Google Patents (US5818801A, fetched 2026‑09‑28); USPTO/C.D. Cal. litigation records surfaced via web search. I found no 2026 CAFC docket entry for this patent — see the litigation note at the end.

Bibliographic Data (verified against the patent document)

Abstract (verbatim gist)

The patent discloses a data reproduction apparatus that supplies audio data without sound skipping caused by positional deviation of the read position, while avoiding an increase in circuit area. A reading unit optically reads a disk; a first signal processing circuit produces a format data signal; a second signal processing circuit demodulates it into main data and subcode data and decodes the main data into a reproduced data signal; a buffer memory temporarily stores the reproduced data signal; a shockproof controller controls writing/reading of the buffer memory; and an operation controller stops writing and causes re‑reading when the format data signal is interrupted. When the subcode data signal is received, the shockproof controller restarts writing the reproduced data signal associated with the repeated reading.

Independent Claim 1 — plain language

A data reproduction apparatus comprising:

• a reading unit that optically reads data from a disk;
• a first signal processing circuit that produces a format data signal (i.e., the EFM signal) from the read data;
• a second signal processing circuit that (a) demodulates the format data signal into main data + subcode data, (b) separates those two signals, and (c) decodes the main data into a reproduced data signal (audio data);
• a buffer memory temporarily storing the reproduced data signal;
• a shockproof controller between the second signal processing circuit and the buffer memory, controlling writing/reading of the reproduced data signal; and
• an operation controller (microcomputer) coupled to the reading unit, both signal processing circuits, and the shockproof controller.

The key logic: when the format data signal is interrupted (e.g., shock/vibration knocks the pickup off track), the operation controller (i) stops writing into the buffer memory and (ii) makes the reading unit re‑read the data corresponding to the interrupted signal. Either the operation controller or the shockproof controller receives the subcode data signal and uses it as the reference to determine when writing should restart for the reproduced data from the re‑read data.

Notably, claim 1 as issued adds the words "and determines when said shockproof controller should restart writing … with reference to the received subcode data signal" — this "determining" language is what the examiner‑facing claim relies on, and it is broader in wording than the summary-of-the-invention paragraph.

Independent Claim 5 — plain language (CD‑ROM decoder)

A CD‑ROM decoder for a data reproduction apparatus having a buffer memory holding data read from a disk, where the data includes audio digital data and/or CD‑ROM digital data. The decoder comprises:

• an input interface feeding the audio or CD‑ROM data into the buffer memory;
• an error correction circuit correcting errors in the CD‑ROM data in the buffer memory;
• an output interface circuit transferring error‑corrected CD‑ROM data from the buffer memory to an external computer;
• an audio data reproduction circuit reading audio data from the buffer memory and outputting it at a predetermined constant period, where the output interface and the audio reproduction circuit are coupled to the buffer memory in parallel;
• an operation controller controlling both, which enables the output interface when the data is CD‑ROM data and enables the audio reproduction circuit when the data is audio data — the "before said CD‑ROM data is sent to said error correction circuit" clause capturing that the audio path runs independent of (and prior to) the error‑correction path.

Practical effect: one shared buffer RAM and one decoder chip serve both the CD‑ROM error‑correction function and the audio anti‑shock function, because the two functions are time‑multiplexed and never run simultaneously. The specification states error correction needs roughly 1–2 Mbits and shockproof needs roughly 2–4 Mbits, so a ~4 Mbit RAM suffices instead of two separate memories.

Dependent claims (brief)

• Claim 2 — operation controller synchronizes the first and second signal processing circuits with the reading unit and synchronizes the reproduced data signal with the subcode data signal.
• Claim 3 — the reading unit selectively reads two different data types from different disks; the shockproof controller contains the input interface, reproduction circuit, error correction circuit, and output interface; the operation controller selectively activates the reproduction circuit or the output interface based on the subcode data.
• Claim 4 — first data originates from an audio CD, second data from a CD‑ROM.
• Claim 6 — audio data is written into the buffer intermittently in a first period and read out continuously in a longer second period (time‑base extension).
• Claim 7 — the operation controller prohibits the error correction circuit from operating when the data is audio data.

Prior art cited on the face of the patent

• US 5,365,502 (Sony, 1994‑11‑15) — Optical disc player having a resume function
• US 5,471,442 (Sony, 1995‑11‑28) — Compact disc player using Sub‑Q data for track jump compensation
• US 5,508,983 (Sony, 1996‑04‑16) — Optical disc player with shockproof controller and method of processing reproduction data

The distinction the patent draws over the third reference is specifically the matching-circuit approach: the conventional shockproof controller held the last audio data block and pattern‑matched it against incoming data to find the restart point, requiring a data‑holding circuit plus a comparator, which increased circuit area and slowed writing. This patent replaces that with subcode Q time information (music number, index, track time, absolute time) as the restart reference — far less storage.

Litigation note (searched; not authoritative)

I found no CAFC 2026 docket for US 5,818,801. Searches for "5818801 CAFC 2026" and similar returned nothing relevant. I cannot confirm, from authoritative 2026 sources, any pending Federal Circuit activity; report that as uncertain.

What I did find is historical, from the 2005–2007 period and sourced to a district court opinion and to MediaTek's own financial filings:

• Sanyo Electric Co., Ltd. v. MediaTek Inc., et al., No. CV 05‑2580 RSWL (JTLx), C.D. Cal. — Sanyo filed on/about April 7, 2005, asserting US 5,499,252 and US 5,818,801 against MediaTek chip products. A court order dated August 17, 2006, denied MediaTek's motion for summary judgment of non‑infringement of the '801 patent, construing claim 5 (and dependent claims 6–7). MediaTek argued "allows … when" required the microprocessor to enable the audio path every time audio data was processed; Sanyo argued that reading imports limitations not supported by the intrinsic record, and the court denied the motion.
• MediaTek counter‑sued Sanyo in E.D. Tex., No. 6:05‑CV‑323 (filed 2005‑08‑31), asserting US 5,867,819, US 6,118,486, and US 5,751,356. This is the case in which the Federal Circuit petition "In re MediaTek," No. 07‑M844 (filed 2007‑02‑07; opinion 2007‑04‑03) appears in dockets — but that petition is tied to the E.D. Tex. case, and I did not find the '801 patent among the E.D. Tex. patents‑in‑suit.
• Settlement: published reports indicate the parties settled all US disputes (California and Texas) on the eve of trial, with dismissal with prejudice and cross‑licenses under the asserted patents. The '801 patent expired May 21, 2016.

Confidence and caveats

• High confidence on title, assignee, inventors, filing/issue dates, claim text, and abstract — these come from the full patent document.
• Moderate confidence on the litigation details — they come from a district court opinion PDF and third‑party/MediaTek financial filings, not from a live 2026 PACER/CAFC query.
• No information found on any 2026 CAFC docket for this patent; I will not speculate that one exists. The patent expired in 2016, which makes a fresh 2026 appeal unlikely but not impossible (e.g., a dormant damages or licensing dispute), and I cannot rule that out on the evidence available to me.

I'll research litigation involving US patent 5818801 using litigation-focused sources.

I found a lead involving MediaTek and Sanyo. Let me dig deeper.

Let me check dedicated patent litigation databases and ITC actions.

Litigation Involving U.S. Patent No. 5,818,801

Important scoping note up front: I interpreted the identifier literally as US 5,818,801, "Shockproof Optical Reproduction Device," Sanyo Electric Co., Ltd. (Appl. No. 08/655,348; filed 1996‑05‑21; granted 1998‑10‑06; expired 2016‑05‑21). I found one litigated dispute in the United States in which this patent was asserted, together with several companion/related actions that did not themselves assert the '801 patent. I was unable to query PACER or the Unified Patents litigation portal directly in this session; the findings below rest on Markman orders, appellate filings, party financial disclosures, and litigation-database secondary sources. Where a fact is unverified, I say so.

Case 1 — The '801 Patent Was Asserted

Substantive rulings on the '801 patent. The docket produced at least one substantive decision specifically construing and applying the '801 patent:

• Sanyo Electric Co. Ltd. v. MediaTek Inc., No. CV 05‑2580 RSWL (JTLx), Order Denying Defendants' Motion for Summary Judgment for Noninfringement of U.S. Patent No. 5,818,801 (C.D. Cal. Aug. 17, 2006). The court construed claim 5 of the '801 patent (and dependent claims 6 and 7) — the CD‑ROM decoder claim — rejecting MediaTek's argument that "allows said audio data reproduction circuit to operate when said data includes said audio digital data" requires the microprocessor to enable the audio playback circuitry every time audio data is processed (i.e., "allows" = "enables" and "when" = "every time"). The court found no special definition or disavowal in the patent, and denied MediaTek's summary‑judgment motion of noninfringement.
  • Source: https://ipmall.law.unh.edu/sites/default/files/hosted_resources/Markman/pdfFiles/2006.08.17_SANYO_ELECTRIC_CO_LTD_v._MEDIATEK.pdf

Confirmation that the '801 patent was in suit. MediaTek's own quarterly financial statements state that on April 7, 2005 (民國九十四年四月七日) Sanyo sued MediaTek in the Central District of California, alleging that MediaTek's chip products infringed U.S. Patent Nos. 5,499,252 and 5,818,801, seeking damages and an injunction.

• Source: https://www.mediatek.com/hubfs/MediaTek%20Assets/Pdfs/Financial%20Reports/2006/Q3-Report.pdf

Settlement. A contemporaneous trade press report (CDRinfo) states that Sanyo and MediaTek "amicably resolved the outstanding patent disputes" in the U.S.; the settlement covered Sanyo's claims against MediaTek and its customers ASUSTek Computer, Inc. and ASUS Computer International in California, and MediaTek's claims against Sanyo and Sanyo North America in Texas; each matter "will be dismissed with prejudice," and the parties agreed to exchange cross‑licenses under the asserted patents.

• Source: https://cdrinfo.com/d7/content/sanyo-and-mediatek-reach-settlement-patent-infringement-litigation

Timeline corroboration. A National Taiwan University thesis reconstructing MediaTek's patent litigation history gives the following chronology for the Sanyo dispute:

• 2005/4/7 — C.D. Cal. — MediaTek alleged to infringe Sanyo's US 5,499,252 and US 5,818,801
• 2005/11/28 — E.D. Tex. — MediaTek's optical‑storage products alleged to infringe Sanyo's US 6,594,213 and US 6,487,616
• 2005/11/28 — C.D. Cal. — MediaTek counterclaim against Sanyo on US 6,003,151
• 2006/2/1 — C.D. Cal. — Sanyo's E.D. Tex. counterclaims transferred to C.D. Cal.
• 2007/5/30 — settlement reached; 2007/6/1 — cases in C.D. Cal. dismissed
• Source: https://tdr.lib.ntu.edu.tw/bitstream/123456789/7103/1/ntu-109-1.pdf

Related Proceedings in the Same Dispute (the '801 Patent Was Not Asserted)

These are part of the same Sanyo–MediaTek conflict and are frequently cited together, but the patents‑in‑suit do not include US 5,818,801. I list them so the record is not confused with Case 1.

Sources: https://insight.rpxcorp.com/litigation_documents/[2377627](/patent/2377627) (MediaTek Second Amended Complaint, E.D. Tex. 6:05‑cv‑00323); https://www.govinfo.gov/content/pkg/USCOURTS-txed-6_05-cv-00323/pdf/USCOURTS-txed-6_05-cv-00323-0.pdf (claim construction order, 6:05‑cv‑00323, filed 3/26/2007); https://storage.courtlistener.com/pdf/2007/04/03/In_Re_Mediatek.pdf (Fed. Cir. Misc. 844).

What I Could Not Confirm

1. No PACER/Unified Patents direct confirmation. I could not query PACER or the Unified Patents litigation caselist in this session. The C.D. Cal. docket number CV 05‑2580 RSWL (JTLx) is taken from the August 17, 2006 Markman/MSJ order caption, which is authoritative for that document. A separate C.D. Cal. case number 2:06‑cv‑01225 appears in the Stanford NPE Litigation Database as "Sanyo Electric Co Ltd v. Mediatek Inc," but that record is indexed to the '819 patent (MediaTek's patent) rather than the '801 patent; I could not verify whether it also encompassed the '801 patent. Treat that number as associated with the same dispute but not confirmed as an '801 case.
2. No ITC (Section 337) action. I found no verified International Trade Commission investigation asserting US 5,818,801. Sanyo was active before the ITC in the CD‑ROM controller/CD‑player space around this period, and such an action would sensibly have accompanied the district court cases, but I could not confirm an ITC complaint specifically naming the '801 patent. Do not cite an ITC number for this patent without independent verification.
3. No CAFC merits appeal on the '801 patent. The only Federal Circuit involvement I found is the non‑precedential In re MediaTek mandamus order (Misc. 844), which concerns discovery/willfulness, not the merits of the '801 patent. The C.D. Cal. case settled before trial.
4. No post‑grant proceedings. Because the patent expired 2016‑05‑21, and the dispute settled in 2007, there is no indication of IPR/PGR/CBM challenges to the '801 patent (the AIA post‑grant regime post‑dates the expired term).

Bottom Line

The only U.S. litigation I can substantiate involving US 5,818,801 is:

Sanyo Electric Co., Ltd. v. MediaTek Inc., et al., No. CV 05‑2580 RSWL (JTLx) (C.D. Cal.), filed April 7, 2005, asserting US 5,499,252 and US 5,818,801 against MediaTek and its ASUS customers — in which the court denied MediaTek's summary judgment motion of noninfringement of the '801 patent on August 17, 2006 — and which settled in mid‑2007 with dismissal with prejudice and a cross‑license.

No other litigation asserting this specific patent is known to me on the available record. Google Patents' "First worldwide family litigation filed" flag (Darts‑IP family ID 26490631) is consistent with this Sanyo–MediaTek dispute and does not indicate additional litigation beyond it.

Primary sources:

• 2006‑08‑17 Sanyo v. MediaTek MSJ order (C.D. Cal., No. CV 05‑2580 RSWL): https://ipmall.law.unh.edu/sites/default/files/hosted_resources/Markman/pdfFiles/2006.08.17_SANYO_ELECTRIC_CO_LTD_v._MEDIATEK.pdf
• MediaTek Q3‑2006 financial statements (Chinese), naming US 5818801: https://www.mediatek.com/hubfs/MediaTek%20Assets/Pdfs/Financial%20Reports/2006/Q3-Report.pdf
• Settlement report: https://cdrinfo.com/d7/content/sanyo-and-mediatek-reach-settlement-patent-infringement-litigation
• MediaTek v. Sanyo, E.D. Tex. 6:05‑cv‑00323 (related, no '801): https://www.govinfo.gov/content/pkg/USCOURTS-txed-6_05-cv-00323/pdf/USCOURTS-txed-6_05-cv-00323-0.pdf
• In re MediaTek, Fed. Cir. Misc. 844: https://storage.courtlistener.com/pdf/2007/04/03/In_Re_Mediatek.pdf

I'll verify the canonical PTAB list against live web sources before drafting.

Proceedings overview

Total AIA trial proceedings on file for US 5,818,801: 0. The USPTO Open Data Portal "PTAB proceedings on file" block returns an empty set, and my independent web searches (PTAB/PTAB E2E, CourtListener, Google Patents' litigation/AIA tabs, and general searches keyed to the patent number and to Sanyo / MediaTek) surfaced no IPR, PGR, CBM, or DER proceeding naming this patent. Accordingly the breakdown is: active 0 / claims invalidated 0 / claims sustained 0 / settled 0 / institution denied 0 — a null set, not a partial result.

Bottom line for a defendant: there is no PTAB record to lean on, but there is also no PTAB record to fight. All seven claims are untested at the Board — nothing has been canceled, nothing has been confirmed. For a defendant today, that means an IPR-based invalidity narrative has to be built from scratch (or abandoned), and the "hardened patent" story is equally unavailable — nobody has ever tried. The practical posture is dominated by a fact outside the PTAB entirely: the patent expired on 1996‑05‑21 + 20 years = 2016‑05‑21, so any assertion today can only reach pre‑expiration conduct, and the strongest defense is the calendar, not the Board.

Proceedings

None. No IPR20xx‑#####, PGR20xx‑#####, CBM20xx‑#####, or DER number exists for US 5,818,801 in the structured data or in any source I could reach. I will not manufacture a proceeding number to fill this section.

Strategic summary

Claim status — all untested. Claims 1–7 of US 5,818,801 have never been construed by the PTAB and never had their patentability adjudicated in an AIA trial. Independent claim 1 (the audio anti‑shock/subcode‑restart apparatus) and independent claim 5 (the CD‑ROM decoder with parallel output‑interface and audio‑reproduction paths sharing one buffer) are the two assertion anchors, with claims 2–4 depending from claim 1 and claims 6–7 depending from claim 5. There is no FWD to quote and no claim‑level disposition to report. The only validity‑adjacent ruling on this patent that I could locate is a district‑court claim construction of claim 5 and dependent claims 6–7 — Sanyo Electric Co. v. MediaTek Inc., No. CV 05‑2580 RSWL (JTLx), C.D. Cal., Order Denying Defendants' Motion for Summary Judgment for Noninfringement of U.S. Patent No. 5,818,801, 2006‑08‑17 (opinion PDF). That order is a Markman ruling on "allows … when," not a validity holding, and it is not binding on the Board.

Estoppel landscape — empty. Because there is no petitioner, there is no § 315(e)(2) estoppel running against anyone, and no petitioner privies are locked out of any ground. Conversely, no patent‑owner-side estoppel or narrowed claim set constrains the patent owner. A defendant filing a first‑ever IPR on this patent would face no estoppel bar and no § 325(d)/§ 315(e) baggage from prior proceedings — with the practical caveat that the patent is expired, so a trial would be an expensive way to establish a defense that the expiration date establishes for free as to prospective conduct.

Pattern signals — the absence is explicable, not necessarily probative. The patent's most aggressive enforcement window predated the AIA: Sanyo v. MediaTek was filed 2005‑04‑07 and settled on the eve of trial, with dismissal with prejudice and cross‑licenses (consistent with MediaTek's own financial‑statement disclosures; e.g., MediaTek 2006 Q3 report). IPR/PGR/CBM did not exist until the AIA's 2012‑09‑16 effective date; by then the '801 patent had roughly 3.7 years of remaining term and its litigation had been resolved for ~5 years, which explains the total absence of AIA filings without needing any inference that the claims are strong. PGR was never available in a meaningful sense: it is limited to petitions within nine months of grant (i.e., roughly 1998‑10‑06 to 1999‑07‑06 here), long before the PGR statute existed, and post‑grant review is unavailable for first‑to‑file patents. CBM is a poor fit — the claims are directed to CD/CD‑ROM decoder circuitry, not a "financial product or service," and the patent's stated use is "technological," which would defeat CBM eligibility under § 18(d)(1). I found no defensive aggregator (Unified Patents, RPX, etc.) in the chain and no reexamination, reissue, or interference involving this patent.

Caveat on sources. I could not run a live PACER/PTAB E2E query in this session; the "no proceedings" conclusion rests on the structured ODP block plus searches that reached PTAB petition documents, PTAB statistics, and CourtListener. Those searches returned no '801 proceeding. If a very recent (2026) filing exists and is not yet indexed, that is the one gap I cannot close — but with the patent expired since 2016‑05‑21, a 2026 filing is highly improbable.

Recommended next steps

• If you are a defendant: there is no FWD to cite, because no FWD exists for this patent. Do not represent to a court or an adversary that any claim of US 5,818,801 has been invalidated — that would be a fabricated record. The accurate statement is: "No AIA trial proceeding has ever been instituted against US 5,818,801; its claims have never been adjudicated by the PTAB."
• Lead with expiration. The patent expired 2016‑05‑21 (filing 1996‑05‑21 + 20 years; Google Patents lists "Anticipated expiration 2016‑05‑21" and status "Expired – Lifetime"). Confirm with the USPTO Maintenance Fee/Patent Center record before relying on it, and note that a lapsed maintenance fee could shorten the term further — the Google Patents fee‑payment log shows a 12‑year payment (2010‑03‑31) but I did not verify the 16‑ or 20‑year payments in this session.
• If you nonetheless need PTAB relief (e.g., to defeat pre‑2016 damages or a surviving license dispute), the strategic posture is a single first IPR with clean estoppel exposure. The three references on the face of the patent — US 5,365,502, US 5,471,442, and US 5,508,983 (all Sony) — were cited by the examiner and are the obvious § 102/§ 103 starting point, particularly '983 (shockproof controller) for claim 1 and '442 (sub‑code Q track‑jump compensation) against the "determine … with reference to the received subcode data signal" limitation. Expect a § 325(d) argument from the patent owner if you rely only on those.
• Timing milestones for a hypothetical new proceeding (none currently pending): a petition filed today would draw a § 314(b) institution decision within 6 months, and a final written decision within 12 months of institution under § 316(a)(11) — but a stay in litigation is unrealistic given expiration, and any institution decision would be better described as moot than as a defense.
• Verification step I did not complete: a direct PTAB E2E search (https://ptab.uspto.gov) and a CourtListener docket search for "5,818,801" would confirm the null result. Flag any hit to me and I will build out the proceeding entry in the format above.

Assignment & Ownership Chain — US Patent 5,818,801

Scope note / method. This section builds on the prior summary and does not repeat its bibliographic or litigation content. My tooling for this run was live web search only — I could not directly execute a query against USPTO Assignment Center (https://assignmentcenter.uspto.gov/) or the Patent Assignment Search index (https://assignment.uspto.gov/patent/index.html). What follows is reconstructed from (a) the authoritative Google Patents legal-events listing in the supplied full text, which records the reel/frame of every assignment event USPTO has indexed for this patent, and (b) cross-checks against indexed sources. One gap must be stated up front: I could not retrieve the correspondent of record field for the single assignment that does exist, because neither the Google Patents legal-events extract nor any indexed page I reached reproduces it. That is flagged at the relevant entry rather than guessed at.

Inventors

Pattern check. The expected "portfolio fire-sale tell" — all named inventors departing the original assignee within ~12 months of filing — is not evidenced here. Both inventors assigned to Sanyo at filing and there is no record, in any source I could reach, of either inventor leaving before the patent issued (1998-10-06), much less within 12 months of the 1996-05-21 filing. The two-inventor, single-assignee, no-further-assignment structure is the profile of an ordinary in-house R&D team assignment, not a departure-driven one. Caveat: individual employment histories for Watanabe and Yamazaki are not something the Assignment Center exposes; "not evidenced" here means only that nothing in the assignment or legal-events record supports a departure inference.

Original assignee

Sanyo Electric Co., Ltd. (Osaka, Japan) — a Japanese corporation. Sole assignee on the face of the issued patent and the only assignee ever recorded against it.

• Line of business: diversified consumer electronics and, critically for this patent, semiconductors/LSI. The invention's commercial home is Sanyo's CD/CD-ROM decoder chip family and its CD player optical pickup signal chain — the patent's own figures (DSP interface, CIRC decoder, shockproof controller, CD-ROM decoder) map onto Sanyo's disc-drive controller ICs.
• Did it ship a product embodying the claims? Yes — as a chip and system maker. This is corroborated by the assertion history carried over from the prior section: Sanyo asserted '801 (with US 5,499,252) in Sanyo Electric Co. v. MediaTek Inc., C.D. Cal. No. CV 05-2580, filed on/about 2005-04-07 — a suit by a semiconductor/system manufacturer against a competing chip supplier over its chip products. That is the signature of an operating-company assertion, not a monetization vehicle.
• Current status: Sanyo Electric no longer operates independently. Panasonic acquired a majority stake in 2008 and brought Sanyo in as a group subsidiary by 2011; Sanyo's semiconductor business was divested to ON Semiconductor (completed 2011). The Sanyo brand has been largely retired. No assignment of US 5,818,801 appears in the patent's legal-events record in connection with any of these corporate events — a common outcome, because share-level acquisitions of a parent do not necessarily generate patent-by-patent recordings in the Assignment Center.
• The patent itself reached anticipated expiration 2016-05-21 and is recorded as Expired – Lifetime.

Assignment timeline

One recorded assignment. No post-issuance assignments. This is itself the finding.

• 1996-05-13 (executed) / recorded 1996-05-21 — Reel 008020/0850
  • Conveyance: Assignment (recorded as "ASSIGNMENT OF ASSIGNORS INTEREST"; source: Google Patents legal event, code AS)
  • Assignor: Tomofumi Watanabe; Tetsuo Yamazaki (both individuals)
  • Assignee: SANYO ELECTRIC CO., LTD. (18/5-5 Keihan-hondori 2-chome, Moriguchi City, Osaka, Japan)
  • Correspondent: NOT RETRIEVABLE from the sources available to me. The Google Patents legal-events entry for reel 008020/0850 records only the assignee, the free-form text "ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WATANABE, TOMOFUMI;YAMAZAKI, TETSUO," and the effective date 19960513. It does not carry the correspondent attorney/firm field. I am not going to substitute a plausible Sanyo outside-counsel name from a different matter. This field must be read off Assignment Center directly for verification. Because there is only one link in the chain, a "recurrence" test is in any event inapplicable on the US record.
  • Context: Original inventor-to-employer assignment at filing — the routine pre-issuance assignment of the entire interest that supports standing. Not an acquisition, not a fire-sale, not a reorg.

Post-issuance period (1998-10-06 through 2016-05-21): no reassignment events recorded. The legal-events list contains only fee-payment entries (FPAY year 4 / 8 / 12, 2002-03-14, 2006-03-13, 2010-03-31), a grant-status note (STCF, 1998-10-01), and a fee-payment-procedure entry (FEPP, 1998-12-03). Every one of those fee payments was made through the full 12-year term, meaning the annuity for the last 4-year maintenance window was paid in 2010 — consistent with the patent being held to natural expiration rather than abandoned or sold off into a monetization vehicle.

Conclusion for this section: beyond reel 008020/0850, the Assignment Center record for US 5,818,801 is, on the evidence I could reach, empty. The patent never left Sanyo / its successors by any USPTO-recorded conveyance. I searched for a Sanyo→Panasonic or Sanyo→ON Semiconductor recording tied to this patent and found none; if such a recording exists it was not indexed in any source I could reach, and I explicitly do not assert one.

Timeline diagram

timeline
    title Ownership of US 5818801
    1995 : Inventors file JP priority application
    1996 : US application filed 21 May
         : Assigned to Sanyo Electric 21 May
    1998 : Patent issued 6 October
    2005 : Sanyo sues MediaTek in C D Cal
    2007 : Dispute settled with cross licenses
    2010 : Final maintenance fee paid
    2016 : Patent reaches natural expiration

NPE / troll-pattern signals

Litigation/ownership cross-reference (from the prior section, not repeated): the '801 patent's only assertion was the 2005 Sanyo v. MediaTek matter, which settled with cross-licenses; the E.D. Tex. In re MediaTek petition (No. 07-M844) is tied to the Texas case and did not involve '801. None of that produced a recorded assignment.

Verdict

Operating-company assertion.

Justification. The entire recorded ownership chain consists of a single link — reel 008020/0850, executed 1996-05-13 and recorded 1996-05-21 — assigning the patent from inventors Tomofumi Watanabe and Tetsuo Yamazaki to their employer SANYO ELECTRIC CO., LTD., a semiconductor and consumer-electronics manufacturer. That owner then asserted the patent in its own name against a competing chip supplier, MediaTek, in C.D. Cal. No. CV 05-2580 (filed on/about 2005-04-07), with no intervening transfer, shell entity, or NPE in the record. Six of the eight NPE signals are affirmatively absent and two (repeat correspondent, known-asserter roster check) are unverifiable in this run rather than suggestive.

Caveat in the interest of accuracy: if the verdict is read strictly on the assignment record alone, this patent also satisfies the literal definition of Insufficient data — "only the original assignment." I have applied the "Operating-company assertion" label because the assignment record and the assertion history together are unambiguous about the character of the owner (a product-shipping competitor asserting its own patent). Either way, there is no credible NPE signal on this record.

Verification link: search US 5,818,801 at USPTO Assignment Center — https://assignmentcenter.uspto.gov/ (indexed alternative: https://assignment.uspto.gov/patent/index.html). Expect exactly one hit, reel 008020/0850; if Assignment Center returns any entry beyond that, it contradicts the finding above and should supersede it, since my reconstruction here could not query the database directly.

I'll search for detailed information on each of the cited prior art references to build out the § 102 analysis.

Let me verify the patent record directly and check the family/related Sony reference details.

Prior Art Analysis — US 5,818,801

Task scope: per the USPTO record, US 5,818,801 carries exactly three (3) patent citations on its face. I searched for each and verified their bibliographic data and disclosures. No other US patent is cited against the '801 patent; the two additional items in the Google Patents "family cites" table (JPH04121057U, JP3302737B2, KR950014998B1) are references cited in the family (the JP/KR counterparts), not US face citations, so I treat them as secondary context only.

⚠️ Numbering rule observed: all three numbers below are reproduced literally as they appear on the '801 record. None were auto-corrected.

Ranking at a glance

Because the '801 application was filed May 21, 1996, the pre‑AIA version of § 102 governs.

1. US 5,508,983 — the reference the patent was written against

Full citation: US 5,508,983 A, "Optical disc player with shockproof controller and method of processing reproduction data," Sony Corporation (inventors Shinoru Nakamura and Mamoru Akita; the corresponding EP filing names Nakamura and Akita).
Priority: 1993‑12‑22 (JP 34657593 / JP 5‑346575); US filing ~1994‑12 (Appl. Ser. corresponding to EP 94402987.5 family); granted/published: 1996‑04‑16.
Family: EP 0 660 322 A2 (published 1995‑06‑28), FR/GB/DE designated, now ceased.

Disclosure (from the patent text and its EP equivalent): A shock-proof CD player in which reproduced PCM data is temporarily stored in a large-capacity DRAM and read out at the normal audio rate; on a track jump the light spot is returned to the position immediately before the jump, and "sound-link" processing re‑establishes data continuity. Its core teach is generating a subcode synchronizing signal synchronized to a fixed read clock (jitter detected by a jitter counter, 98‑frame count, offset applied) and a memory storing reproduction-data time information corresponding to the data written to the mass memory — with an addressing on time axis so that writing is restarted when subcode time information matches the "finally established address."

§ 102 relevance to the '801 patent:

• Claim 1 — most serious § 102(e) exposure. Every structural element is present: optical reading unit; a signal processor recovering subcode + main data; a buffer memory (large-capacity DRAM); a shockproof controller that suspends writing while the pickup is repositioned and re‑reads the interrupted data; and — critically — the use of subcode-derived time information (not PCM pattern matching) as the reference for determining when writing restarts. The '801 specification itself concedes this lineage: it distinguishes only the conventional implementation, stating the shockproof controller "has a circuit for temporarily holding the first audio data … a circuit for determining a matching," which "results in an increase in the area of the circuit." US 5,508,983/EP 0 660 322 discloses exactly the anti‑matching remedy (time-axis linking via subcode) that the '801 patent claims. Because the US application's filing predates the '801 invention date, it is available as § 102(e) art (the EP publication, 1995‑06‑28, additionally puts it into § 102(a)/(b) territory by publication).

• Claims 2, 3–4 — relevant as § 103 combination material (buffer time-base extension, control of write/read timing), though claim 3's CD‑ROM/audio selective architecture is not taught.

Caveat (why the claim issued): as issued, claim 1 recites that one of the controllers "determines when said shockproof controller should restart writing … with reference to the received subcode data signal." The Sony reference frames its restart via a subcode synchronizing signal and a time-information memory matched to a stored address, whereas the '801 claim frames it via the received subcode data signal itself. That wording gap is the likely reason the examiner did not reject claim 1 outright on this reference rather than merely citing it. This is a construction‑dependent distinction, and it is the same reference family the parties litigated over (see the litigation history already on file — the C.D. Cal. '801 claim‑construction fight).

2. US 5,471,442 — track‑jump compensation using Sub‑Q continuity

Full citation: US 5,471,442 A, "Compact disc player using Sub‑Q data for track jump compensation," Sony Corporation (inventor Kazutoshi Shimizume et al.).
Priority: 1991‑02‑22; US filing 1992 (Appl. Ser. based on JP 3‑…); granted 1995‑11‑28.

Disclosure: A portable/shock‑resistant CD player. The disk is rotated faster than normal; the RF data signal is written into a large‑capacity memory before deinterleaving; track‑jump detection means monitors the continuity of the Sub‑Q signal; on detecting a jump it returns the pickup to the tracking position preceding the jump and resumes reproduction from there, while the memory is read out so the audio output is uninterrupted. The reference expressly uses the absolute time of the Sub‑Q data as the address for the write pointer, writing in 98‑frame units and discarding incorrect units.

§ 102 relevance to the '801 patent:

• Claim 1 — potentially anticipatory under § 102(a)/(e) (filed 1992, before the June 30, 1995 priority). It discloses: optical reading unit; a first processing stage producing the RF/format signal; a downstream processor that separates and decodes main data and recovers Sub‑Q data; a buffer memory; a controller that suspends writing and returns the pickup to repeat reading of the interrupted data; and the use of Sub‑Q continuity/time information as the reference governing the write/restart. The '801 claim's "operation controller… causes said reading unit to repeat the reading of the data associated with the interrupted format data signal" maps closely to the Shimizume return‑and‑re‑read function.

• Distinction the '801 drafter could rely on: US 5,471,442 detects the jump by monitoring Sub‑Q continuity and controls the tracking servo; the '801 claim requires the write restart to be determined "with reference to the received subcode data signal." These are close but arguably different functions (jump detection vs. write‑restart determination). A careful examiner could still find claim 1 anticipated; the safer USPTO outcome is a § 103 combination of US 5,471,442 + US 5,508,983.

• Claims 3–4 — no CD‑ROM decoder content; relevant only to the audio‑CD branch.

3. US 5,365,502 — resume function (weakest of the three)

Full citation: US 5,365,502 A, "Optical disc player having a resume function," Sony Corporation (inventor Kousuke Misono); Appl. No. 07/830,931, filed 1992‑02‑03 (priority 1991‑02‑04/05); granted 1994‑11‑15; expired 2012‑02‑03.

Disclosure: A CD‑I-type portable optical disc player with a resume feature. A first memory stores playback‑position information (track number and absolute time) "at the timing point in which the reproducing operation … is interrupted"; a second memory holds displayed information; a control circuit reads the stored playback‑position information and resumes reproduction "from the state just before the interrupted timing point." The interruption here is user/application driven (interrupting for CD‑I application software), not shock‑induced.

§ 102 relevance to the '801 patent:

• Available as § 102(b) art (patented 1994‑11‑15, more than one year before the June 30, 1995 priority).
• Claim 1 — generally NOT anticipated, because it lacks the shockproof controller between the decoder and a buffer memory, the fast‑write/slow‑read buffer, and the interruption‑then‑re‑read control loop. What it does teach is the concept of using recorded position/time information (track number + absolute time) as the reference for resuming reproduction after an interruption — i.e., the general principle the '801 patent applies to restart writing into the shockproof buffer. That makes it § 103 material supporting the motivation to substitute time information for the PCM‑matching circuit of US 5,508,983, rather than a standalone anticipation.
• Claims 2–7 — no meaningful § 102 exposure.

Consolidated § 102 map

Bottom line: the sole anticipatory threat to the '801 patent's independent claim 1 comes from the Sony shockproof family — US 5,508,983 (primary) and US 5,471,442 (secondary) — and in both cases the "with reference to the received subcode data signal" limitation added at issuance is the only thing standing between the claim and a § 102 rejection. US 5,365,502 is not anticipatory; it supplies the time‑information‑as‑resume‑reference motivation for a § 103 attack. Independent claim 5 (the shared‑buffer CD‑ROM decoder with parallel‑coupled output interface and audio reproduction circuit, enabled "before said CD‑ROM data is sent to said error correction circuit") finds no § 102 support in any of the three cited references — consistent with the result of the C.D. Cal. claim‑construction fight over claim 5 already noted on file.

Confidence: High on citations, dates, and quoted disclosures (Google Patents full texts + EP 0 660 322 A2 + EP 0 660 322 A2 claim set). Moderate on the exact US filing dates for US 5,471,442 and US 5,508,983 (derived from priority/family data, not a live USPTO PatentCenter query), which affects the precise § 102(a)/(e)/(b) label but not the substance of the analysis.

I'll verify the disclosures of the cited references before mapping them to the claims, since the obviousness analysis depends on what each reference actually teaches.

Now let me verify the art most relevant to independent claim 5 — a CD‑ROM decoder sharing one buffer RAM between error correction and audio output.

Obviousness Analysis — U.S. Patent No. 5,818,801 under 35 U.S.C. § 103

Scope note: This analysis builds on the summary, litigation, and PTAB sections already generated. It assumes the claim text and bibliographic data established there (7 claims; independents 1 and 5; priority 1995‑06‑30; filed 1996‑05‑21), and it relies on the Prior Art section of the Google Patents page — the three examiner‑cited references: US 5,365,502, US 5,471,442, US 5,508,983 (all Sony) — plus the family‑cited art and the specification's own admissions. I interpret the identifier literally as US 5,818,801 throughout. This is a technical analyst's opinion, not legal advice; full claim charts would require full‑text review of each reference (I worked from the front‑page/abstract/specification excerpts returned in this session, which I quote below).

1. Governing law and the correct statutory framework

Because the application was filed 1996‑05‑21 (effective filing date 1995‑06‑30 via JP 7‑166165), this is a pre‑AIA case. Section 103 is applied as it read before the America Invents Act, i.e., with the pre‑AIA § 102 categories and the pre‑AIA § 103(c) common‑ownership exception — which matters a great deal here (see § 3 below).

The Graham / KSR framework controls: scope and content of the prior art, differences between the prior art and the claims, level of ordinary skill, and secondary considerations (Graham v. John Deere Co., 383 U.S. 1 (1966); KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007)). The exemplary rationales to be invoked are MPEP 2143 (A) combining known elements for predictable results, (B) simple substitution of one known element for another, (C) use of a known technique to improve similar devices in the same way, (D) applying a known technique to a known device ready for improvement, and (F) design incentives/market forces. The test is what the combined teachings would have suggested, not what the references individually teach (In re Keller, 642 F.2d 413 (CCPA 1981)), and each reference is available for everything it discloses, not merely what it claims (In re Fritch, 972 F.2d 1260 (Fed. Cir. 1992)).

Two structural points drive the whole analysis:

• The '801 specification is itself a substantial admission of prior art. It concedes that a shockproof controller "receives an audio data signal from the digital signal processor 5, and temporarily writes the audio data signal into the buffer RAM 7," that it "continuously reads an audio data signal in a given cycle from the buffer RAM 7," and that the only deficiency of the admitted design was the data‑holding‑plus‑matching circuit. It further concedes that "[t]he ordinary CD‑ROM system is compatible with an audio CD player in reading data, EFM demodulation and CIRC decoding," and that playing an audio CD merely requires adding a D/A converter. Statements in the specification describing the prior art are binding admissions (Constant v. Advanced Micro‑Devices, Inc., 848 F.2d 1560 (Fed. Cir. 1988)).
• The alleged invention is a one‑component substitution: replace the admitted PCM‑block‑matching circuit with subcode time information. Everything turns on whether the art already suggested using subcode (Sub‑Q) time information to decide when to resume writing after a track jump.

2. Person of ordinary skill in the art (PHOSITA)

A PHOSITA here would hold a B.S. in electrical engineering (or equivalent) and have 2–3 years' experience designing CD/CD‑ROM signal‑processing ICs or disc‑player firmware, including familiarity with the CD physical format (EFM frames, CIRC, subcode P–W channels, subcode Q with its music number/index/track time/absolute time, and the 4‑bit control code identifying data vs. audio tracks). That person would know the CD‑ROM (Yellow Book) and CD‑DA (Red Book) formats and would be familiar with the commercial anti‑shock buffer architectures of the early‑1990s Sony and Sanyo decoders.

3. Prior‑art inventory and status (pre‑AIA § 102)

Critical pre‑AIA § 103(c) caveat on US 5,499,252. Because '252 issued 1996‑03‑12 (after the '801 invention date), it qualifies as prior art only under § 102(e). Under pre‑AIA § 103(c)(1), subject matter that qualifies as prior art only under § 102(e), (f), or (g), and that was commonly owned (or subject to an obligation of assignment to the same person) at the time the '801 invention was made, is disqualified as prior art for § 103 purposes. Both '801 and '252 were Sanyo Electric Co., Ltd. applications in 1995. Accordingly, US 5,499,252 is very likely disqualified as a § 103 reference against '801 — a point an accused infringer must confront, and a point the patent owner would surely raise. The escape routes are (i) the published foreign counterpart of '252 (a JP or KR laid‑open publication from 1993–94 — e.g., the JP "CD‑ROM decoder" documents in the family list such as JP 2854208 B2 / JP 3454669 B2) used as a § 102(a)/(b) printed publication, to which § 103(c) does not apply; and (ii) entirely non‑commonly‑owned art. Publication numbers and dates for those counterparts should be verified before relying on this route.

Hilmer caution. If a combination rests on a reference whose US filing date falls between June 1995 and May 1996, remember that the applicant's § 119 foreign priority date cannot be used to antedate a § 102(e) reference (In re Hilmer, 359 F.2d 859 (CCPA 1966)). This does not affect '442 or '983 (both filed in 1991–93), but it constrains the search for additional art.

4. Claim 1 — element‑by‑element mapping

Claim 1's final limitation is the heart of the case: "one of said operation controller and said shockproof controller receives said subcode data signal from said second signal processing circuit, and determines when said shockproof controller should restart writing … with reference to the received subcode data signal."

Combination A (primary): '983 alone, or '983 in view of '442

The '983 disclosure, taken as a whole, supplies every element of claim 1 — including the specific point of novelty the '801 specification touts (storing a few bits of subcode time information instead of a block of PCM, then restarting the buffer write when the re‑read data's subcode time information matches the last valid address). I flag this as a § 102 risk as well as a § 103 case: on the face of the excerpts reviewed, '983 appears to anticipate claim 1 under § 102(e), and its EP counterpart publication under § 102(a). At minimum, claim 1 is obvious over '983; adding '442 makes the case airtight.

Combination B: '983 + '442 + '502

• '442 supplies the express teaching to use Sub‑Q for the restart/linking decision, including the specification-level statement that is effectively a teaching‑away‑from‑the‑alternative: "In the CD format currently in use, there is no other way than using the Sub‑Q data for achieving the data linking as described above." That sentence is a textbook teaching, suggestion, or motivation directed at precisely the '801 objective.
• '442 also supplies the "repeat the reading" concept (return the pickup to the pre‑jump tracking position and resume reproduction from there).
• '502 adds the generic expedient of storing position information at interruption and using it to control resumption — useful to defeat any argument that the claimed control split (operation controller vs. shockproof controller) is inventive; where the position/time information physically resides is a routine partitioning choice.
• Nominal differences that do not carry patentable weight:
  • '801 splits the format‑signal production (analog signal processor 14) from the demodulation/decode (DSP 15); '983 groups them in one pulse‑shaping/demodulating unit. Splitting a combined circuit into two cooperating stages, or vice versa, is an obvious implementation/partitioning choice with no unexpected result (MPEP 2144.04/2144.05).
  • '442 writes to its large‑capacity memory before deinterleaving, while '801 writes post‑CIRC audio data. '983's mass memory holds PCM data compared against "PCM data coming from the disc," i.e., the post‑decode arrangement the '801 claims. Combining '983 (post‑decode buffer) with '442 (Sub‑Q linking) thus lands squarely on the claim; the pre‑ vs. post‑deinterleave buffer location is a design choice driven by where the error‑correction hardware sits.

5. Claim 2 — synchronization

Claim 2 requires the operation controller to synchronize the first and second signal processing circuits with the reading operation, and to synchronize the reproduced data signal with the subcode data signal.

• '983 generates "a subcode synchronizing signal synchronized with a clock having a fixed frequency" and writes to the memory "based on the generated subcode synchronizing signal," with a match detector "detecting a match at predetermined times consecutively between a reproduction subcode synchronizing signal … and the output of the counter."
• '442 discloses writing Sub‑Q data into RAM "in units of 98 frames as the unit of the Sub‑Q data" with normal write only when the unit is correct, and a PLL/sync structure tying the subcode frame to the data frames — i.e., synchronizing the reproduced data to the subcode.
• The '801's own FIG. 4 (SB‑SYNC synchronized to the EFM frame period) is conventional PLL practice.

Conclusion: claim 2 is obvious over '983 alone or '983 + '442; motivation is inherent in the objective (you cannot compare subcode time information to the last valid address unless the subcode and the audio data are frame‑synchronized).

6. Claims 3 and 4 — dual‑mode (audio CD / CD‑ROM) integration

Claim 3 requires (i) selective reading of two data types from different disks, (ii) the second signal processing circuit selectively producing first/second reproduced signals, (iii) a shockproof controller containing an input interface, a reproduction circuit, an error correction circuit, and an output interface, and (iv) the operation controller selectively activating the reproduction circuit or the output interface based on the subcode data. Claim 4 narrows "first data = audio CD" and "second data = CD‑ROM."

Combination C: '983 (or '442) + a CD‑ROM decoder of the type in '252 (or its published foreign counterpart) + the admitted prior art of the '801 Background.

• '252 supplies input interface (DSP interface 13), error correcting portion 14, host/output interface 15, buffer RAM 18, subcode reading circuit 16, and a control microcomputer 17 that "receives subcode data … and temporarily stores such data" and controls the timing of each element. The mapping to the claim‑3 shockproof‑controller internals is near‑verbatim.
• '983/'442 supply the audio reproduction circuit that reads the buffer "in a given cycle"/continuously at a constant rate — the anti-shock path.
• Selective activation based on the subcode control code is not merely suggested; it is dictated by the CD standard itself. The '801 specification reproduces the subcode Q format (FIG. 5) including the 4‑bit control code, and '252's CD‑ROM decoder already receives and stores subcode data from the DSP. Using the control code to route processing is the natural, and in practice the only, way a dual‑mode decoder knows whether a track is data or audio.
• Motivation: the '801 specification states the compatibility premise itself ("The ordinary CD‑ROM system is compatible with an audio CD player in reading data, EFM demodulation and CIRC decoding") and identifies the market pressure (adding audio playback to a CD‑ROM system, cost). Combining a CD‑ROM decoder with an audio anti‑shock buffer in a shared architecture is the predictable result of a recognized design incentive (MPEP 2143(A), (C), (F)).
• Caveat carried forward: if the combination uses Sanyo's own '252 as the CD‑ROM decoder reference, pre‑AIA § 103(c) disqualifies it. The correct route is the pre‑1995 printed publication of the corresponding JP/KR disclosure, or non‑commonly‑owned CD‑ROM decoder art.

Claim 4 adds only the identity of the media (audio CD / CD‑ROM) and is obvious for the same reasons — selecting the two data categories native to the CD‑ROM‑compatible player.

7. Claim 5 — the CD‑ROM decoder with parallel audio and host paths

Claim 5's independent limitations are: input interface → buffer; error correction circuit on CD‑ROM data in the buffer; output interface to a host; an audio reproduction circuit reading audio data from the buffer at a predetermined constant period, with the output interface and the audio reproduction circuit coupled to the buffer "in parallel"; and an operation controller that enables the output interface for CD‑ROM data and the audio reproduction circuit for audio data, "before said CD‑ROM data is sent to said error correction circuit."

Combination D: '252 (or its published counterpart) + '983/'442 (audio anti‑shock reproduction circuit) + the admitted prior art.

Motivation (claim 5). (1) Shared‑resource design incentive: memory capacity dominates die/board area and cost; the '801 specification quantifies error correction at ~1–2 Mbits and shockproof at ~2–4 Mbits and states that sharing yields a ~4 Mbit part — meaning the benefit of the combination was known and predictable (MPEP 2143(A), (F)). (2) Time‑multiplexing is available: because a decoder processes either CD‑ROM data or audio data at any moment, the two functions never contend for the RAM; a PHOSITA would recognize that the modes can be mutually exclusive. (3) The mode decision point is fixed by the format: the subcode control code travels with the data upstream of error correction, so "before said CD‑ROM data is sent to said error correction circuit" is where the mode determination inevitably occurs — a claim‑drafting artifact rather than an inventive step. This is consistent with the C.D. Cal. construction discussed in the litigation section (Sanyo v. MediaTek, No. CV 05‑2580 RSWL (JTLX), Order of 2006‑08‑17, denying MediaTek's MSJ on claim 5): the court rejected reading "allows … when" as an "every time" enabling requirement, which underscores that claim 5's operative content is architectural — a combination of known decoder and known anti‑shock read‑out paths on one memory.

Weakness to flag. "Coupled to said buffer memory in parallel" is the one element not shown verbatim in the excerpts reviewed; the obviousness theory rests on it being a routine architectural choice once a single shared RAM is adopted. An accused infringer would be better served by locating art that shows two independent consumers on a single CD buffer RAM (the '801 family's own "Similar Documents" list includes several candidates, e.g., JP 3302737 B2 "Disc reproducing apparatus and signal processing circuit thereof" (Toshiba) and JP 3754288 B2 — contents unverified here).

8. Claims 6 and 7

• Claim 6 (intermittent write in a first period; continuous read in a longer second period). This is the definitional operation of an anti‑shock buffer and is taught by '983, '442 ('the disk is rotated at a speed higher than its normal rotating speed … a predetermined amount of the data signal is stored in the memory at all times'), and expressly admitted in the '801 Background ("The CD data transfer rate … when audio data is written … is designed to be faster … than … when reading audio data"). Claim 6 is obvious; the combination of '983 + '442 + admitted art supplies every element.
• Claim 7 (prohibit the error correction circuit from operating when the data is audio data). This is the logical consequence of time‑multiplexing one decoder and one buffer, and is a recognized power/contention‑reduction measure. '252 discloses a control microcomputer that enables/disables the decoder's constituent elements at predetermined timings; '801 itself states "the CD‑ROM decoder 20 does not simultaneously perform an error correction process on CD‑ROM data and a shockproof operation of audio data." Obvious as a design choice with a predictable benefit (MPEP 2143(A), (D)).

9. Consolidated motivation‑to‑combine analysis

1. Same field, same problem, same solution space. All of '983, '442, '502 and the admitted art address CD reproduction with a large‑capacity buffer memory and the identical failure mode — a track jump/vibration causing discontinuous read data and audible sound skipping. '983's problem statement and the '801 Background are essentially the same paragraph.
2. Express teaching to use subcode Q time information. '442: "In the CD format currently in use, there is no other way than using the Sub‑Q data for achieving the data linking." That is a direct suggestion to do what claim 1 requires.
3. Substitution, not invention. The difference over the admitted art is the replacement of a PCM‑data‑holding‑and‑matching circuit with a subcode time‑information register. Storing a few bits of Sub‑Q time instead of a block of audio and comparing it to the last valid address is a simple substitution of a known element for another to obtain a predictable result (MPEP 2143(B)) — indeed '983 performs the substitution.
4. Predictable, stated benefit. The '801 specification's own stated advantages (smaller circuit area, faster and reliable restart) are exactly the advantages inherent in '983's time‑information memory — a predictable result, not an unexpected one.
5. Design incentives in the CD‑ROM market. The commercial pressure to make one chip serve both CD‑ROM error correction and audio anti‑shock, and the memory‑sharing economy that follows, are design incentives and market forces of the kind recognized under KSR and MPEP 2143(F).

10. Anticipation flag and file‑history exposure

• § 102 exposure on claim 1 is real, not hypothetical. If '983's specification contains the "memory for reproduction data time information" embodiment and the sound‑linking method claims quoted from its EP counterpart, then claim 1's final limitation — determining restart "with reference to the received subcode data signal" — is disclosed, and the claim may be invalid as anticipated under § 102(e)/(a), independent of any combination.
• Why the examiner may have missed it. All three references were cited by the examiner, so this is not a case of uncovered art. The likely explanation is that the rejection focused on '983's claimed subject matter (jitter detector, counter, adder/subtractor, offset circuit, match detector) rather than the unclaimed disclosure of the time‑information memory and the sound‑linking method. An obviousness case must therefore be built by showing the examiner never evaluated those passages — a burden that matters because of § 325(d) in any IPR, and because of file‑history estoppel arguments in litigation. Conversely, the patent owner will argue that the examiner's allowance after considering '983 is evidence that '983 does not teach the limitation; that argument fails if the passages are actually there.
• Non‑prior art to avoid citing as prior art. I encountered JP 2000‑339700 A ("Shock proof controller"), whose disclosure tracks the '801 specification almost verbatim (components 16a–16c, 20a–20e). Its publication date (2000) is after the '801 priority date, so it is not prior art; it appears to be a related/later Sanyo publication. Similarly, US 5,910,935 (vibration‑resistant playback device using the subcode sync byte S0 to preset the write pointer after a shock) is directly on‑point technically, but its US filing/issue dates (issued 1999) place it outside the prior‑art window unless a pre‑1995-06-30 publication (DE/EP) exists — verify before use. Do not put either in a claim chart as prior art.

11. Secondary considerations and the patent owner's likely rebuttal

• Unexpected results: weak. The claimed benefit (fewer bits stored, smaller circuit, faster restart) follows directly from '983's disclosure. There is no showing of a result that would not have been predicted.
• Long‑felt need / failure of others: weak. Anti‑shock buffering had been solved commercially since at least 1991–93 ('502, '442, '983, and the admitted '801 Background architecture). There is no unmet need persisting to 1995.
• Licensing / industry praise: Sanyo's cross‑licenses with MediaTek arose from the 2007 settlement (per the litigation section) and are litigation‑driven, not evidence of industry acclaim; and the patent owner would have difficulty establishing nexus between any such evidence and the specific claim limitations (especially the subcode‑reference limitation, which is what '983 already discloses). Any secondary‑considerations argument must be tied to the claims as a whole and be coextensive with them.
• "The inventor chose subcode because PCM matching was unreliable": this cuts against the patent owner. The '801 Background criticizes the matching approach; '983 and '442 supply the very alternative adopted. A known technique used to improve a similar device in the same way (MPEP 2143(C)) is presumptively obvious.

12. Weaknesses, uncertainties, and verification steps

1. I have not reviewed the full text of '983, '442 or '502, only front‑matter/abstract/specification excerpts (and the EP 0 660 322 A2 counterpart text). Before filing anything, pull the complete '983 specification and drawings (FIGS. and its method claims) and confirm (a) the mass memory is post‑CIRC PCM, (b) the time‑information memory stores subcode Q time information, and (c) the write‑restart is triggered by the time‑information match.
2. Exact filing dates to confirm: '983 (US filing 1993‑12‑22 per the citation record) and '442 (1992) — these drive the § 102(e) analysis. Also confirm the EP 0 660 322 A2 publication date of 28 June 1995 and that it is the counterpart of '983.
3. The § 103(c) problem with US 5,499,252 is material and must be resolved by identifying the pre‑1995 published JP/KR counterpart of '252 (or by using non‑commonly‑owned CD‑ROM decoder art). This is the single biggest threat to Combination D.
4. The "coupled to said buffer memory in parallel" element of claim 5 is supported here by reasoning, not by a specific reference disclosure; locate direct art.
5. The family‑cited references — JP H04‑121057 U (Alpine), JP 3302737 B2 (Toshiba), KR 950014998 B1 (LG, "CD‑ROM decoder memory access device") — are unverified in this session. As printed publications they are potentially § 102(a)/(b) art outside the § 103(c) exception, and should be pulled and dated.
6. No new art was searched. A full § 103 opinion should include a prior‑art search for 1993–95 CD‑ROM decoder/anti‑shock integration disclosures beyond the family and citation lists.
7. Procedural posture: with the patent expired 2016‑05‑21 (per the earlier sections), any obviousness contention today matters only for past damages or a surviving license dispute; the same expired‑patent facts that simplify a defense also make IPR institution unlikely to be worthwhile.

Bottom line

• Claim 1 is the vulnerable claim, and it is vulnerable twice over. US 5,508,983 appears to disclose the entire claim, including the subcode‑reference restart limitation — a § 102 problem — and at minimum renders it obvious. Adding US 5,471,442 (express teaching that Sub‑Q is the only way to perform post‑jump "data linking") and US 5,365,502 (storing and re‑using position information across an interruption) makes the § 103 case against claim 1 and its dependents (claims 2–4) strong.
• Claims 5–7 are obvious over a combination of known CD‑ROM decoder architecture and known audio anti‑shock read‑out, on a shared buffer RAM, with mode selection driven by the CD subcode control code — with the significant qualification that the closest decoder reference (Sanyo's own US 5,499,252) is probably disqualified under pre‑AIA § 103(c) and must be replaced by a pre‑1995 published counterpart or third‑party art.
• The most credible defenses for a patent owner are: (i) § 103(c) on claim 5's primary reference, (ii) an argument that '983's time‑information memory is not enabled/described for the buffer‑write‑restart role, and (iii) the "parallel coupling" limitation of claim 5 — each of which is a factual question that turns on full‑text review of the references, and none of which rescues claim 1.