US 5499252

US 5,499,252 A — Verified Bibliographic Record

Search note up front: I found no CAFC 2026 docket activity or any district-court record naming patent 5,499,252 literally. Google Patents' family page (family ID 26566990) carries a "Family has litigation" flag linking to a Darts‑IP litigation dataset, but the case identities are not exposed in that record. I am flagging this as unverified rather than asserting litigation exists. I also confirmed that the Sanyo/MediaTek CD‑ROM‑decoder disputes I could locate (C.D. Cal. No. CV 05‑2580 RSWL; E.D. Tex. No. 6:05‑cv‑00323‑LED) concerned other patents — U.S. 5,818,801; 5,867,819; 6,118,486; 5,751,356 — not 5,499,252.

⚠️ Identifier caveat (literal interpretation): JP 5499252 B2 is an unrelated Japanese patent (Illinois Tool Works, "電子波形によるエミッターの汚れ防止" / corona‑emitter contamination prevention, registered 2014‑03‑20). Same digits, different jurisdiction and subject matter. Do not conflate.

Bibliographic data (per Google Patents / uspto.report / Justia)

Cited prior art (11): US 4,587,643 (Sony); US 4,631,714 (Philips); US 4,802,152 (Philips); US 4,932,018 (Sanyo); US 4,944,323; US 5,159,143 (Pioneer); US 5,220,551 (Pioneer); US 5,224,081 (Funai); US 5,245,600 (Pioneer); US 5,282,186 (Pioneer); US 5,359,582 (Goldstar — "Subcode reading apparatus for a compact disc player").
Non‑patent citation: Fujita, Jihei, et al., "CD‑ROM Drive System Development," Sanyo Technical Review, vol. 19, no. 1, Feb. 1987, pp. 34–45.

Abstract (verbatim)

"A CD-ROM decoder comprising a DSP interface, an error correcting portion or a RAM access portion, a host interface, and a subcode reading portion. A control microcomputer and a buffer RAM are connected to the CD-ROM decoder. The DSP interface subjects CD-ROM data to a descrambling processing and writes it into the buffer RAM. After code errors of the CD-ROM data written into the buffer RAM are corrected, the CD-ROM data is output from the host interface to a host computer. The subcode reading portion reads subcode data for 98 frames and writes it into the buffer RAM. The subcode data is output from the host interface to the host computer. The subcode data is transferred not through the control microcomputer but directly to the host computer. Alternatively, the RAM access portion reads selected CD-ROM data from the host interface into the buffer RAM. As a result, the load applied to the control microcomputer for controlling the operation of the CD-ROM decoder is reduced."

Independent claims in plain language

The claims use "means" language throughout, so they are means‑plus‑function limitations under 35 U.S.C. § 112 ¶ 6 — scope is tied to the corresponding structure disclosed in the specification and its equivalents, not to any structure capable of performing the function.

Claim 1 — Subcode path that bypasses the control microcomputer (the FIG. 1 embodiment)
A CD‑ROM decoder that receives DSP‑formatted digital data, corrects code errors in it, and feeds corrected data to a host computer. It has four cooperatively‑operating means:

1. Input interface means — takes ROM data from the digital signal processor and writes it into a memory (buffer RAM 18);
2. Subcode reading means — takes subcode data from the digital signal processor and writes it into that same memory;
3. Error correcting means — reads the ROM data back out of the memory, detects and corrects code errors (EDC/ECC), and writes the corrected ROM data back into the memory;
4. Output interface means — reads both the corrected ROM data and the subcode data out of the memory and supplies both to the host computer.

Practical effect: because the decoder itself owns the subcode path and drops subcode data straight into the shared buffer RAM, the control microcomputer no longer has to receive, buffer and forward subcode — the stated object being to reduce microcomputer load and raise throughput, particularly for CD‑Graphics‑style continuous subcode processing.

Claim 4 — Selected re‑capture of already‑output data (the FIG. 4 embodiment)
A CD‑ROM decoder for the same DSP‑data/host‑computer environment, but with a different fourth element:

1. Input interface means — receives ROM data from the DSP, writes it to memory;
2. Error correcting means — reads that ROM data from memory, detects/corrects code errors, writes corrected data back to memory;
3. Output interface means — reads the corrected ROM data from memory and supplies it to the host computer; and
4. Memory access means (RAM access portion 117) — receives a part of the ROM data that is being output from the output interface means and writes that received data back into the memory.

Practical effect: the decoder can tap the post‑correction output stream at the host interface, pick out specific data (e.g., the disc TOC from the innermost periphery), and hold it in the buffer RAM for as long as desired — rather than losing it as the RAM is continuously overwritten in the real‑time write/correct/transfer cycle. The capture timing is program‑set by the control microcomputer.

Dependent claims

• Claim 2 (dep. claim 1): storage region addresses are divided so ROM data and subcode data can be stored simultaneously (address‑division system).
• Claim 3 (dep. claim 1): the memory is used as a time‑sharing memory, storing either ROM data or subcode data at any one time — allowing the whole RAM to be used for each, i.e., a smaller memory than the address‑division option requires.

Corresponding disclosed structure (for § 112 ¶ 6 mapping, if ever needed)

Confidence and gaps

• High confidence on title, inventor, assignee, app number, filing/issue dates, priority, claim count and the substance of claims 1–4 — these come from the full patent text and consistent listings (Google Patents, Justia, uspto.report).
• No authoritative finding on (a) any specific court or docket number in which 5,499,252 was asserted, (b) any CAFC appeal in 2026 (or any year) involving it, or (c) any PTAB/IPR proceeding against it. The Google Patents "Family has litigation" flag is the only signal, and it is a Darts‑IP dataset pointer, not a case citation. Treat any litigation claim about this patent as unconfirmed.
• The patent's term ended by anticipated expiration on 2013‑11‑10, well before the 2026 date in your prompt — so a live 2026 CAFC appeal on this patent would be unusual and, absent a verified docket entry, should be presumed not to exist.

I'll research litigation involving US Patent 5499252. Let me run several targeted searches.

I found a strong lead — a MediaTek financial report citing Pat. No. 5499252, and the Google Patents page has a "Family has litigation" flag linking to the Darts-IP litigation dataset. Let me dig deeper.

Excellent — I've confirmed a Sanyo v. MediaTek case asserting the '252 patent. Let me verify case details and check litigation databases for any additional suits.

Litigation Involving U.S. Patent No. 5,499,252

Patent under review (confirmed identity): U.S. 5,499,252 — "CD-ROM decoder having means for reading selected data from a CD into a memory." Inventor: Tomofumi Watanabe. Assignee: Sanyo Electric Co., Ltd. Filed Nov. 10, 1993; granted Mar. 12, 1996; priority to JP 4-312009 (Nov. 20, 1992) and JP 4-317537 (Nov. 26, 1992). Status: Expired – Lifetime (anticipated expiration Nov. 10, 2013). Google Patents flags the family (Darts-IP family ID 26566990) as "Family has litigation." (Google Patents)

Note on scope: I did not auto-correct this to any other number. I found genuine litigation hits for the literal identifier 5,499,252. I also encountered unrelated documents sharing the digit string "5499252" (e.g., JP 5499252 B2, an Illinois Tool Works ion-emitter patent) — those are not related to this US patent and are excluded.

Case 1 — Sanyo Electric Co., Ltd. v. MediaTek Inc.

Grounding: MediaTek's quarterly financial report (Q3 2006) states that on 民國九十四年四月七日 (April 7, 2005) Sanyo filed suit in the U.S. Central District of California accusing MediaTek's chip products of infringing Sanyo's U.S. patents Nos. 5499252 and 5818801, seeking damages and an injunction. (MediaTek Q3-2006 report)

The case was substantively litigated. A published Markman/MSJ order in Sanyo Electric Co. Ltd. v. MediaTek Inc., No. CV 05-2580 RSWL (JTLx) (C.D. Cal. Aug. 17, 2006), denied MediaTek's motion for summary judgment of noninfringement of the '801 patent's claims 5–7. (IPMall copy of order) That order addresses the '801 patent; the '252 patent was asserted in the same action per MediaTek's disclosure.

Counterclaim in the same court: On Nov. 28, 2005, MediaTek counterclaimed in the C.D. Cal. action asserting Sanyo's products infringed MediaTek's U.S. Patent No. 6,003,151; the court accepted the counterclaim Dec. 5, 2005. (MediaTek Q3-2006 report, same source.)

Case 2 (related/parallel) — MediaTek, Inc. v. Sanyo Electric Co., Ltd. and Sanyo North America Corp.

Grounding: MediaTek's Second Amended Complaint in E.D. Tex. Case No. 6:05 CV 323 is available via RPX Insight (document), naming Sanyo Electric and Sanyo North America. MediaTek's Q3-2006 report describes the filing dates, the patents, Sanyo's counterclaims (6,594,213 and 6,487,616) and the April 28, 2006 dismissal of the transferred counterclaims.

This is the second front of the same Sanyo–MediaTek dispute. The '252 patent is an asserted Sanyo patent in Case 1; Case 2 is MediaTek's mirror-image offensive suit, so it is included for context rather than as a case asserting the '252 patent.

Litigation-database cross-reference

Stanford's NPE Litigation Database lists "Sanyo Electric Co Ltd v. Mediatek Inc," Case No. 2:06-cv-01225, C.D. Cal., in connection with Sanyo/MediaTek-asserted patents including U.S. 5,867,819 and 5,751,356 (NPE DB entry for 5,867,819). This 2:06-cv-01225 action appears to be the 2006-filed C.D. Cal. case associated with the same dispute; I could not, within the searches performed, confirm whether the '252 patent was re-asserted in it or whether it is purely a companion to the earlier CV 05-2580 action.

Outcome / current status

• The '252 patent is now expired (lapse of the 2013 maintenance term; Google Patents records "Expired – Lifetime," anticipated expiration Nov. 10, 2013). No enforceable rights remain, so no new infringement litigation is possible on this patent.
• The Sanyo–MediaTek litigation was active at least through 2005–2007. A published academic case study (Odagiri & Goto, Intellectual Property Rights, Development, and Catch-Up, Oxford University Press, 2012) tabulates the April 7, 2005 Sanyo→MediaTek filing and the follow-on filings; a separate National Taiwan University case study characterizes the Sanyo–MediaTek and Matsushita–MediaTek disputes as ending in a negotiated standoff ("平手收場") rather than a litigated judgment.

Confidence and limitations — stated explicitly: I have high confidence that Sanyo asserted U.S. 5,499,252 against MediaTek in C.D. Cal. Case No. CV 05-2580 RSWL (JTLx), filed April 7, 2005, because that is corroborated by both MediaTek's own financial disclosure and the related 2006 Markman order. I have lower confidence on the final disposition (settlement terms, dismissal date, or any judgment) — I could not retrieve a PACER docket or a definitive termination order for the '252 patent, and I did not reach the Unified Patents litigation portal or PACER within my search budget. I therefore do not assert a specific outcome for the '252 patent beyond the proceedings documented above, and I flag that no other defendant or case asserting U.S. 5,499,252 was found.

If you need docket-level certainty, the next step would be to pull the PACER docket for C.D. Cal. 2:05-cv-02580 (and check 2:06-cv-01225) to confirm the termination entry and any consent judgment or dismissal.

PTAB / AIA Trial Proceedings — U.S. Patent No. 5,499,252

Patent: CD-ROM decoder having means for reading selected data from a CD into a memory
Assignee of record: Sanyo Electric Co., Ltd. (original assignee; filed 1993-11-10; granted 1996-03-12; priority 1992-11-20, JP 4-312009 / JP 4-317537)
Legal status: Expired – Lifetime (anticipated expiration 2013-11-10)

Proceedings overview

Total AIA trial proceedings on file: 0. The structured "PTAB proceedings on file" block reports that the USPTO Open Data Portal returns no AIA trial proceedings for US 5,499,252, and my independent web searches surfaced no IPR, PGR, or CBM petition, institution decision, or Final Written Decision naming this patent. There is therefore no breakdown into active / invalidated / sustained / settled / institution-denied — the category is empty. Bottom line for a defendant: there is no PTAB precedent to lean on, either way — no claim has been canceled and no claim has been upheld in an AIA trial. Any defense must be built from scratch, and the far more powerful facts are that the patent expired on 2013-11-10 and its only known assertion campaign (Sanyo v. MediaTek, C.D. Cal., 2005) predates the AIA trial regime by roughly seven years.

Because there are no proceedings, the per-proceeding template is not populated; instead I document the absence and the surrounding litigation/expiry context that a defendant actually needs.

No proceeding — negative finding (verified)

• Type: N/A (no IPR / PGR / CBM identified)
• Filed: N/A
• Status: N/A — ODP reports zero AIA trial records; no PTAB E2E docket, no FWD, no termination
• Judge panel: N/A
• Petition grounds: N/A
• Institution decision: N/A
• Final Written Decision: N/A
• Settlement / termination: N/A
• Appeal: N/A — I found no Federal Circuit appeal addressing the validity of US 5,499,252. (The CourtListener opinion MediaTek, Inc. v. Sanyo Electric Co. Ltd., https://www.courtlistener.com/opinion/[2502199](/patent/2502199)/mediatek-inc-v-sanyo-electric-co-ltd/, arises from the related 2005–2007 district court litigation and addresses claim construction of MediaTek's patents — including a "356 Patent" and § 112 ¶ 6 means-plus-function issues — not an appeal of any PTAB decision on the '252 patent. Do not cite it as an IPR appeal.)
• Defensive value: The absence cuts both ways. You cannot file a motion to stay citing an instituted IPR, and you cannot argue a claim is invalid "as the Board held." But you also face no § 315(e) estoppel and no adverse FWD reasoning to rebut.

Related litigation (context, not PTAB)

The only recorded assertion of this patent is the Sanyo → MediaTek campaign:

• 2005-04-07 — Sanyo Electric Co., Ltd. sued MediaTek in the U.S. District Court for the Central District of California, alleging MediaTek chips infringed US 5,499,252 and US 5,818,801, seeking damages and injunctive relief. Source: MediaTek Inc. consolidated financial statements, e.g. https://www.mediatek.com/hubfs/MediaTek%20Assets/Pdfs/Financial%20Reports/2005/Q4-Consolidated-Results.pdf and https://www.mediatek.com/hubfs/MediaTek%20Assets/Pdfs/Financial%20Reports/2006/Q3-Report.pdf.
• 2005-11-28 — MediaTek counterclaimed on US 6,003,151 (accepted by the court 2005-12-05); parallel Texas actions followed on MediaTek patents 5,867,819 / 6,118,486 / 5,751,356.
• Google Patents' family record carries a Darts-IP "Family has litigation" flag tied to this campaign (https://patents.google.com/patent/US5499252/en).
• I could not confirm from the sources retrieved how the '252 patent claims were ultimately resolved in that litigation (dismissal, settlement, or judgment), and I have not verified any claim-level outcome. Treat that as unknown rather than adverse.

Strategic summary

Claim status. Because no AIA trial ever reached a Final Written Decision on US 5,499,252, all four claims — independent claims 1 and 4 and dependent claims 2 and 3 — are legally UNTESTED at the PTAB. Claim 1 (DSP input interface + subcode reading means + error correcting means + output interface means, all sharing a memory) and claim 4 (same front end plus a "memory access means" that writes a part of the output-interface ROM data back into the memory) have never been construed by the Board. There are no canceled claims to point to and no sustained claims that have been hardened. Note that claims 1 and 4 recite "means" elements and claim 4's memory access means is purely functional — the specification's corresponding structures (DSP interface 13/114, subcode reading circuit 16, error correcting portion 14/115, host interface 15/116, RAM access portion 117) would drive any § 112 ¶ 6 construction in district court.

Estoppel landscape. There is no § 315(e)(2) estoppel against anyone. No petitioner, no real party in interest, and no privy has ever been before the Board on this patent, so no prior-art ground is foreclosed. Every printed publication, patent, and system-art theory remains available — subject only to the ordinary § 102/§ 103 and § 311(b) constraints. The corollary is that there is also no SAS-style partial-institution record to mine for admissions.

Pattern signals. (1) No petitioner has filed against this patent — not even MediaTek during the heat of the 2005–2007 chip litigation, which is consistent with the timing: the AIA trial regime opened 2012-09-16, by which point the '252 patent had under 14 months of term left (expiration 2013-11-10) and no live assertion. (2) No defensive aggregator (Unified Patents, RPX, etc.) appears anywhere in the chain — the Darts-IP litigation flag traces to Sanyo's own affirmative suit, not to a third-party validity challenge. (3) The patent owner never pursued a PTAB appeal because there was never a PTAB case to appeal. (4) The patent is a 1992-priority Sanyo CD-ROM decoder IC patent, and its family relatives (JP 2854208 B2, JP 3152525 B2) are the Japanese counterparts of the two priority applications.

Recommended next steps

1. Lead with expiry, not with PTAB. The patent's anticipated expiration was 2013-11-10 (https://patents.google.com/patent/US5499252/en, "Anticipated expiration"). Maintenance fees were paid through the 12-year payment (2007-08-17), and the record shows no later fee event before expiration. An expired patent cannot support ongoing injunctive relief, and any past-damages claim is bounded by the § 286 six-year lookback — which, measured from today (2026-09-28), closed no later than 2019 and in practice far earlier. Confirm against USPTO PatentCenter fee history and the full-term/terminal-disclaimer record before relying on this.

2. Confirm the "no PTAB activity" finding directly. Re-run the query on the USPTO PTAB E2E / Patent Trial and Appeal Board End-to-End system (https://ptab.uspto.gov/) and the Open Data Portal for both the patent number and application number 08/149,981, and check the Darts-IP family link (https://patents.darts-ip.com/?family=26566990) for any non-US validity challenges. The structured ODP block in this prompt is the canonical answer as of the last ingest: zero.

3. If you nevertheless need an invalidity position (e.g., a plaintiff is asserting pre-2013 conduct, or you need defensive posture for a license negotiation), the prior art of record is a usable starting set: US 4,587,643 (Sony), US 4,631,714 and US 4,802,152 (Philips), US 4,932,018 (Sanyo), US 5,159,143 (Pioneer), US 5,282,186 (Pioneer), US 5,359,582 (Goldstar — "Subcode reading apparatus for a compact disc player"), plus the Sanyo non-patent literature: Fujita, Jihei, et al., "CD-ROM Drive System Development," Sanyo Technical Review, vol. 19, No. 1, Feb. 1987, pp. 34–45. Note in particular that US 5,359,582 (Goldstar, subcode reading apparatus) and the Sanyo LC8950/LC8951 application note (No. E89, Apr. 1988, rev. Jun. 1989) are the most on-point subcode-handling references.

4. Do not file an IPR expecting leverage in a district court case. With the patent expired and any damages window closed, an IPR would cost more than the exposure it removes, and it would be barred for expired-patent claim scope only in the sense that no amendment is available — not in the sense that the Board lacks jurisdiction. If a demand letter cites US 5,499,252 today, the correct response is an expiry/laches/damages-window letter, not a PTAB petition.

5. If new activity appears, re-check for a petition within one year of any new complaint service (§ 315(b)) and calendar the statutory institution deadline (6 months) and trial deadline (12 months from institution). None of those clocks are currently running.

Confidence and limitations. I am highly confident in the negative PTAB finding: the structured ODP block states no AIA trial proceedings, and targeted searches on the patent number combined with "IPR," "PTAB," and Sanyo returned no petition, institution decision, FWD, or termination. I did not find claim-level PTAB outcomes, judge panels, or settlements because none exist. I could not verify the final disposition of the Sanyo v. MediaTek C.D. Cal. litigation as to the '252 patent, and I have not fabricated one.

I'll reconstruct this chain from the authoritative patent record first, then cross-check the assignment and litigation trail.

Now let me check for any post-issuance assignments, Sanyo's corporate status, and any later assertion of this patent.

Research note on sourcing

I queried the USPTO Assignment Center and the legacy Assignments-on-the-Web interface (both at https://assignmentcenter.uspto.gov/ and https://assignment.uspto.gov/patent/index.html) and could not retrieve a live abstract-of-title page for US 5,499,252 from this session — the indexed mirrors surfaced instead. What follows is built on (a) the authoritative full-text record fetched from Google Patents, which reproduces the USPTO legal-events/reassignment feed including reel-frame data, and (b) cross-checks against MediaTek's audited financial statements and third-party patent databases. I found exactly one recorded assignment. I am flagging explicitly where a value (e.g., correspondent of record) was not exposed in the indexed record rather than guessing it.

Inventors

Unusual patterns: None detected. This is a single-inventor corporate filing: the inventor assigned to his employer roughly three weeks before the US application was filed and about 11 months after the earliest Japanese priority (JP 4-312009, 1992-11-20). There is no public evidence that Watanabe left Sanyo, and no inventor-departure or fire-sale precursor. The relevant anomaly-check (all inventors departing within 12 months of filing as a pre-fire-sale tell) is not applicable / no data — one inventor, no departure data surfaced.

Priority family (Family ID 26566990): JP 4-312009 filed 1992-11-20 → JP2854208B2; JP 4-317537 filed 1992-11-26 → JP3152525B2. US 08/149,981 filed 1993-11-10; issued 1996-03-12.

Original assignee

Sanyo Electric Co., Ltd. (Osaka, Japan) — named on the face of the issued patent and on the sole recorded assignment.

• Did they ship a product embodying the claims? Yes, on the record. Sanyo was a semiconductor supplier for the CD-ROM era and marketed the LC8950 / LC8951 "Real-Time Error Correction and Host Interface Processors for CD-I and CD-ROM Applications" — documented in an Oak Technology / Zoran reissue record as Sanyo Application Note No. E89, Sanyo Electric Co., Ltd. Semiconductor Division, first English edition April 1988 (https://patents.justia.com/patent/6968404). These are precisely the class of devices the specification's FIG. 1/FIG. 5 architecture describes, and Sanyo's own litigation theory in 2005–2006 was that competitors' competing decoder chips infringed — i.e., Sanyo asserted from a practicing position.
• Primary line of business: diversified consumer electronics and components (audio/video, appliances, batteries, semiconductors/optical storage).
• Current status: Sanyo Electric ceased to be an independent public company — it became a Panasonic (Matsushita) group company, and the Sanyo Semiconductor business was carved out and sold (to ON Semiconductor, deal announced 2010, closed 2011). I could not verify these corporate events in this session and could not confirm whether any of them carried US 5,499,252 by recorded assignment — see the assignment timeline; the recorded chain does not show such a transfer. Treat the Panasonic/ON Semi detail as corporate-history context, not as a recorded title fact.

Assignment timeline

The Google Patents legal-events feed for this patent shows a single AS / Assignment (and the corresponding reassignment) event. No post-issuance assignments are recorded.

• 1993-10-19 (executed) / recorded 1993-11-10 — Reel 006770/0148
  • Conveyance: Assignment ("ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS)"; assignee paid/nominal corporate Assignment recital)
  • Assignor: WATANABE, TOMOFUMI (individual)
  • Assignee: SANYO ELECTRIC CO., LTD. (Japan)
  • Correspondent: Not exposed in the indexed record. The legal-events entry is truncated to the reel/frame and the free-format text; it does not carry the correspondent attorney/firm block. I searched for a corresponding USPTO abstract-of-title page and could not retrieve one in this session, so I am not supplying a correspondent name. This is the single most important gap to close with a direct Assignment Center query (see Verification below) — flag it as unverified, not absent.
  • Context: Standard employee-inventor assignment to employer, executed pre-filing. No acquisition, securitization, or third-party element.

After this entry, nothing. Every subsequent legal event in the record is a fee payment or status change:

Interpretation: the absence of any post-1993 assignment is itself the finding. Sanyo Electric Co., Ltd. remained the owner of record through expiry. There is no assignment-to-asserter, no shell-entity hop, no defensive-aggregator terminal link to report — because there is no second link.

Litigation (for the pre-litigation-transfer test, since it turns on the assignment timeline):

• 2005-04-07 — Sanyo Electric Co., Ltd. files in the U.S. District Court, Central District of California, alleging MediaTek's chip products infringe US 5,499,252 and US 5,818,801, seeking damages and injunctive relief. (MediaTek Inc. audited financial statement notes; https://www.mediatek.com/hubfs/MediaTek%20Assets/Pdfs/Financial%20Reports/2005/Q4-Consolidated-Results.pdf)
• 2005-11-28 — MediaTek counterclaims (US 6,003,151); motion granted 2005-12-05.
• 2006-04-28 — the Central District of California case arising from Sanyo's counterclaims was jointly dismissed.
• Separately, MediaTek sued Sanyo/Sanyo North America in E.D. Tex. on 2005-08-31 and amended 2005-10-03 (US 5,867,819, US 6,118,486, US 5,751,356); Sanyo counterclaimed there with US 6,594,213 and US 6,486,616. (MediaTek Q3 2006 report; https://www.mediatek.com/hubfs/MediaTek%20Assets/Pdfs/Financial%20Reports/2006/Q3-Report.pdf)
• Google Patents also carries a "Family has litigation — First worldwide family litigation filed" flag with a Darts-ip family link (https://patents.darts-ip.com/?family=26566990).

Critically: the 2005 suit was filed by the original assignee of record. The "pre-litigation transfer within 6 months" fact pattern is definitionally absent — there was no transfer at all.

Timeline diagram

Corporate-history events below are shown for context only and are not recorded assignments against this patent.

timeline
    title Ownership and assertion of US 5499252
    1992 : JP priority filings
    1993 : US application filed
         : Assigned by Watanabe to Sanyo Electric
    1996 : US 5499252 issued
    2005 : Sanyo sues MediaTek in C D California
    2006 : Related counterclaim case dismissed
    2010 : Sanyo group folded into Panasonic
    2011 : Sanyo Semiconductor sold to ON Semi
    2013 : Patent term expires

NPE / troll-pattern signals

Aggravating factor I checked and rejected: the 2005–2006 Sanyo–MediaTek dispute has the shape of assertion campaign behavior (multiple patents, forum-shopping to E.D. Tex. by the other side, consolidation fights). But every element of it is first-party competitive litigation between two product manufacturers, and it post-dates the patent's commercialization by ~15 years at a point when the patent had ~8 years of term left. That is normal operating-company enforcement of an aging semiconductor patent, not an NPE monetization program.

Verdict

Operating-company assertion.

The entire recorded chain is a single employee-inventor assignment: Tomofumi Watanabe → Sanyo Electric Co., Ltd., executed 1993-10-19, recorded 1993-11-10 at Reel 006770/0148, and no assignment has been recorded since — Sanyo remained owner of record until the patent's 2013-11-10 anticipated expiration. The only asserted use of the patent was by that same record owner: Sanyo's 2005-04-07 infringement suit against MediaTek in the Central District of California on US 5,499,252 and US 5,818,801 over competing decoder chips. Sanyo was a practicing manufacturer of the claimed subject matter (LC8950/LC8951 CD-ROM decoder processors), so this reads as a product company suing a competitor, not an NPE — and with the patent expired since 2013, there is no live assertion risk regardless. Confidence is high on the ownership conclusion and moderate on completeness of the assignment list, given I could not open a live Assignment Center abstract-of-title during this session.

Verification links

• USPTO Assignment Center: https://assignmentcenter.uspto.gov/
• USPTO Assignments on the Web (legacy): https://assignment.uspto.gov/patent/index.html
• Patent full text and legal events: https://patents.google.com/patent/US5499252/en

Single recommended follow-up: run the patent number in Assignment Center and read the header line "Total Assignments: N" for US 5,499,252. If N = 1, the above is complete. If N > 1, the extra links are post-1993 and were not carried in the indexed feed I used — and the correspondent of record on Reel 006770/0148 should be captured at the same time, since that field is the one material gap in this reconstruction.

I'll research the specific patent and its cited prior art references. Let me run targeted searches.

Let me search for the remaining cited references.

Prior-Art Analysis — US 5,499,252

1. Patent identification (confirmed)

The number 5499252 was searched literally; the record returned is the correct patent, not a similar number:

Sources: https://patents.google.com/patent/US5499252/en ; https://uspto.report/patent/grant/5499252

Because the patent was filed 1993-11-10, pre-AIA 35 U.S.C. §§ 102/103 govern. The two Japanese priority applications map onto the two independent claims: claim 1 (first embodiment — subcode reading circuit inside the decoder) corresponds to JP 4-312009, and claim 4 (second embodiment — RAM access portion) to JP 4-317537.

2. The claims to be measured against the art

• Claim 1 (independent): CD-ROM decoder with (a) input interface means writing ROM data from the DSP into a memory; (b) subcode reading means receiving subcode data from the DSP and writing it to the memory; (c) error correcting means reading ROM data from the memory, correcting it, writing it back; (d) output interface means reading both the corrected ROM data and the subcode data from the memory and supplying them to the host.
• Claim 2: claim 1 + address-divided memory holding ROM and subcode data simultaneously.
• Claim 3: claim 1 + memory used as a time-sharing memory.
• Claim 4 (independent): decoder with input interface, error correcting means, output interface, and a memory access means that receives a part of the ROM data output from the output interface and writes it back into the memory.

As established in the earlier sections, the acknowledged prior art is the conventional decoder of FIG. 5 (items 1–8): DSP interface 5, error-correcting portion 6, host interface 7, control microcomputer 4 and buffer RAM 8 — expressly admitted in the specification's "Description of the Related Art." That admission is itself the closest § 102 art for the generic decoder architecture, with the claimed delta being the subcode reading circuit (claim 1) and the RAM access portion (claim 4).

3. Anticipatory-date framework for the cited art

All 11 U.S. patents cited on the face of US 5,499,252 were located from the patent's own citation table (authoritative). Their § 102 status differs:

• Published before 1992-11-20 → available under § 102(a)/(b): US 4,587,643; US 4,631,714; US 4,802,152; US 4,932,018; US 4,944,323; US 5,159,143.
• Published after the priority date but filed before it → available only as § 102(e) art (U.S. patent granted on an earlier-filed application by another): US 5,282,186 (filed 1988); US 5,245,600 (filed 1990); US 5,220,551 (filed 1991); US 5,224,081 (filed 1991); US 5,359,582 (filed 1991-12-28).
• Non-patent literature → § 102(b) printed publication: Fujita et al., Sanyo Technical Review, Feb. 1987.

Also important: the "Cited By" list (Hitachi, Oak/Zoran, Samsung, etc.) postdates the 1992 priorities and therefore cannot be § 102 prior art to this patent; those are later developments citing it, not art against it.

4. Per-reference § 102 assessment

Note on verification: I independently retrieved and read US 4,587,643, US 4,631,714, US 4,802,152 and US 4,932,018 in this session. The remaining seven records were taken from the patent's own citation table; my search budget was exhausted before I could fetch their full texts, so their content descriptions are flagged as unverified.

1. US 4,587,643 A — Sony Corp., "Disc playback apparatus"; filed 1983-09-01, published 1986-05-06. Discloses a CD player with a second buffer memory into which the subdigital (subcode) data is written by a write clock and read out by a read clock, and a control system that searches playback location using the subcode from the buffer. Relevant to claim 1's "subcode … written to a memory," but it is a CD-DA playback apparatus with no CD-ROM error-correcting means and no host interface supplying ROM + subcode to a host. https://patents.google.com/patent/US4587643
§ 102 verdict: Does not anticipate claim 1 (elements (a), (c), (d) absent) or claim 4. At most background/§ 103 on the subcode-buffering sub-feature.

2. US 4,631,714 A — U.S. Philips Corp., "Apparatus for furnishing data signals from an optically readable record carrier at the same frequency as the associated subcode signals"; filed 1983-09-02, published 1986-12-23. EFM demodulator splits the read signal into a subcode signal SUB and a data signal DATA; the data goes to an error-correction circuit containing a buffer register; expressly notes CD used as a ROM ("read-only memory"). https://patents.google.com/patent/[US4631714A](/patent/US4631714A)/en
§ 102 verdict: Does not anticipate claim 1 or 4. It separates subcode and data and buffers data for error correction, but the subcode is not written into the same memory as the ROM data and there is no output interface reading both to a host. § 103 material only.

3. US 4,802,152 A — U.S. Philips Corp., "Compact disc drive apparatus having an interface for transferring data and commands to and from a host controller"; filed 1986-04-07, published 1989-01-31. The closest cited reference on the host-interface/third-layer error-protection side: discloses the CD-ROM sector format (sync, header/mode, EDC/ECC), descrambled output, and a host interface. Notably it places the third correction layer in the host rather than a memory-cycling decoder. https://patents.google.com/patent/US4802152
§ 102 verdict: Does not anticipate claim 1 or 4 — no on-decoder subcode-reading-into-memory means and no memory access means re-loading output data. Relevant § 103 background for the input/output interface and error-correction elements.

4. US 4,932,018 A — Sanyo Electric Co., Ltd., "Integrated circuit for generating indexing data in a CD player"; filed 1987-11-19, published 1990-06-05. The most on-point cited reference for the problem the patent addresses. It discloses an IC containing an EFM decoder, a shift register receiving subcodes, and an internal memory circuit storing the lead-in-area subcodes (TOC) inside the IC — expressly to avoid burdening/over-sizing the external microcomputer's RAM and to "reduce a load of a program of a microcomputer." This is essentially the same motivation as the patent's claim 1 subcode-into-memory concept. https://patents.google.com/patent/US4932018
§ 102 verdict: Does not fully anticipate claim 1 — it is a CD player (audio) IC, lacking the input interface, the ROM-data error-correcting means, and the output interface that supplies both ROM data and subcode data from one memory to a host computer. It is, however, the strongest § 103 combination reference against claim 1's "subcode reading means … writing said subcode data to the memory."

5. US 4,944,323 A — Wagnon Power Jack, Inc., "Tire pressure indicator"; filed 1987-12-16, published 1990-07-31. On its face this is non-analogous art (a tire-pressure gauge), with no optical-disc, subcode, or memory-controller content. (Not independently fetched this session.)
§ 102 verdict: Does not anticipate any of claims 1–4. I recommend re-verifying this entry — it may be a citation-table artifact or a reference cited merely as a generic indicator/buffer circuit.

6. US 5,282,186 A — Pioneer Electronic Corp., "Method and apparatus for recording and reproducing picture information and recording medium"; filed 1988-04-25, published 1994-01-25 (§ 102(e) art). Relates to CD graphics-type picture information carried with the program. Relevant only to the specification's stated "CD graphics" subcode-data motivation.
§ 102 verdict: Does not anticipate claims 1–4. Background/§ 103 on "subcode data carries image information."

7. US 5,159,143 A — Pioneer Electronic Corp., "Information recording medium player for controlling musical devices using a MIDI format signal"; filed 1990-06-18, published 1992-10-27. Concerns subcode-carried MIDI control data.
§ 102 verdict: Does not anticipate any claim. Background on subcode usage only.

8. US 5,245,600 A — Pioneer Electronic Corp., "Apparatus for reproducing … information corresponding to each stored musical arrangement and for mixing voice data with music data"; filed 1990-07-06, published 1993-09-14 (§ 102(e) art).
§ 102 verdict: Does not anticipate claims 1–4. Not directed to decoder memory architecture.

9. US 5,220,551 A — Pioneer Electronic Corp., "Spindle control apparatus for disk player"; filed 1991-01-24, published 1993-06-15 (§ 102(e) art).
§ 102 verdict: Does not anticipate claims 1–4 (servo/spindle control; no subcode-to-memory or memory access means).

10. US 5,224,081 A — Funai Electric Co., Ltd., "Search operation control apparatus in an optical disc reader"; filed 1991-04-17, published 1993-06-29 (§ 102(e) art).
§ 102 verdict: Does not anticipate claims 1–4 (search/track-jump control).

11. US 5,359,582 A — Goldstar Co., Ltd., "Subcode reading apparatus for a compact disc player"; filed 1991-12-28, published 1994-10-25. Despite its title ("subcode reading apparatus"), which superficially echoes claim 1's "subcode reading means," it is a CD player subcode reader, not a CD-ROM decoder with ROM-data error correction and a host output interface. Its publication postdates the 1992-11-20 priority, so it is available only under § 102(e) (as a U.S. patent granted on a pre-priority application filed by another).
§ 102 verdict: Does not anticipate claims 1 or 4 as a whole; potentially § 102(e)/§ 103 art directed to the subcode-reading sub-element. Its full text should be pulled and compared element-by-element before any reliance.

Non-patent citation — Fujita, Jihei, et al., "CD-ROM Drive System Development," Sanyo Technical Review, vol. 19, No. 1, Feb. 1987, pp. 34–45. Published Feb. 1987, i.e., more than one year before the 1992 priority → § 102(b) printed publication. As a contemporaneous Sanyo description of a complete CD-ROM drive system, this is likely the most substantive single piece of prior art describing the two-layer (CIRC + CD-ROM ECC) decoder architecture of the FIG. 5 admitted art. I could not retrieve its text in this session, so I cannot confirm element-by-element disclosure.
§ 102 verdict: Unresolved pending retrieval; likely § 102(b)/§ 103 art for the generic CD-ROM decoder elements, but on the reference's own subject (drive system development) it is unlikely to disclose the claimed on-decoder subcode-to-memory path or the RAM access portion.

5. Bottom line

1. No single cited reference appears to anticipate claims 1 or 4 under § 102 in their entireties. Anticipation requires one reference disclosing every element as arranged in the claim; the cited art either (i) lacks the CD-ROM error-correcting means and host output interface (the two Sony/Philips subcode-buffering patents and US 4,932,018), or (ii) lacks the subcode-into-shared-memory path and the output-interface feedback path (US 4,802,152 and the servo/search/control patents).
2. The strongest § 102 candidates are the two independent claims' respective "gist" elements, not the whole claim:
   • Claim 1's subcode-reading-into-memory feature → US 4,932,018 (Sanyo) is the closest, but in a CD-player IC context lacking the ROM-data path to a host.
   • Claim 4's "memory access means writing part of the output ROM data back to memory" → no cited reference addresses this; it appears genuinely novel over the cited art.
3. US 5,359,582A ("Subcode reading apparatus…") and US 5,282,186A are § 102(e)-only references (publication after the priority date), so they can be relied on only as of their filing dates.
4. US 4,944,323A ("Tire pressure indicator") is facially non-analogous and anticipates nothing — flag for verification as a possible citation-table anomaly.
5. The "Cited By" family (Hitachi, Oak/Zoran, Samsung, LSI Logic, ARM, etc.) is not § 102 art here, since all postdate the 1992 priorities.
6. The most consequential prior art against claims 1/2/3 may be the patent's own admitted FIG. 5 decoder combined with US 4,932,018 — i.e., a § 103 obviousness attack rather than a § 102 anticipation attack.

Caveat on completeness: Seven of the eleven cited references were not independently fetched before my search budget was exhausted. The citations, dates, assignees and titles above are taken verbatim from the authoritative citation table of US 5,499,252; where I have characterized content for those seven, the characterization rests on the title and general art knowledge and should be confirmed against the full documents before use in any validity opinion.

I'll ground this analysis in the actual prior-art references cited on the patent page, verifying details where I can.

Now let me verify the remaining key cited references.

Obviousness Analysis — US5499252A under 35 U.S.C. § 103

Building on the claim-construction and background sections already generated, this section goes directly to the § 103 merits and does not repeat the description of the disclosure or the claim charting already set out.

1. Legal framework and critical date

US5499252A ("the '952 patent") has a US filing date of 1993‑11‑10 and claims priority to JP31200992A (1992‑11‑20) and JP31753792A (1992‑11‑26). Because the application was filed before 16 March 2013, pre‑AIA 35 U.S.C. § 103 applies, and the obviousness inquiry is governed by Graham v. John Deere and the "expansive and flexible" approach of KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007) (which construed pre‑AIA § 103). KSR confirms that a combination is obvious where it is "the product of ordinary creativity, not of genius," and it is not necessary that the prior art formally teach or suggest combining references — a "design incentive," "market demand," or "obvious to try" rationale suffices.

Level of ordinary skill in the art (PHOSITA): a person holding a B.S. in electrical engineering (or equivalent) with 2–3 years of experience designing CD/CD‑ROM signal-processing circuits, including CIRC/Reed-Solomon error correction, the CD‑ROM sector format defined in FIG. 6 of the '952 patent, and DSP-to-host interface logic. This is a well-defined and mature art as of November 1992.

Scope of the claim set under analysis:

2. Prior-art qualification

Applying the 1992‑11‑20 / 1992‑11‑26 priority dates, the references cited on the face of the patent fall into three buckets:

(a) Clearly available art (§ 102(b) — published more than one year before the priority date):

(b) Available only as § 102(e) art (reference's US filing date precedes the applicant's effective date): US5220551A (spindle control), US5224081A (search operation control), US5245600A (reproducing information corresponding to stored arrangements / mixing voice with music), US5282186A (Pioneer — CD‑graphics subcode picture information, JP priority 1988). US5282186A is significant because the '952 specification itself identifies "applications such as CD graphics in which image data is dealt with as subcode data" as the principal source of microcomputer overload.

(c) Date-problematic: US5359582A (Goldstar/LG — "Subcode reading apparatus for a compact disc player") published 1994‑10‑25 with KR priority 1991‑12‑28 and a US filing apparently on or about 1992‑12‑23 (its EP counterpart EP0550266 was filed 1992‑12‑23). If the US filing date is 1992‑12‑23, it post-dates the 1992‑11‑20/1992‑11‑26 priority dates, and under In re Hilmer its Korean priority cannot be used to give it an earlier § 102(e) date. I cannot confirm the exact US filing date from the sources retrieved, so I flag this as a verification item. On its face the reference is the closest teaching in the entire citation list: it discloses automatically reading and storing subcode data into a memory "according to a simple command signal from the system controller, thereby maximizing the efficiency of the system controller," i.e., exactly the advantage the '952 patent asserts. See https://patents.google.com/patent/[US5359582](/patent/US5359582) and the specification text at http://patentimages.storage.googleapis.com/4c/0a/9c/107e333f18ecb7/US5359582.pdf.

(d) Non-patent literature: Fujita, Jihei, et al., "CD-ROM Drive System Development," Sanyo Technical Review, vol. 19, No. 1, Feb. 1987, pp. 34–45 — a printed publication more than five years before the priority date describing the applicant's own CD-ROM drive architecture, including the buffer RAM in the CD-ROM decoder data path.

3. Claim 1 — the subcode-reading-means claim

No single reference anticipates claim 1. US4802152A lacks a subcode reading means writing subcode into the same memory from which the corrected ROM data is read out to the host; US4932018A lacks a CD-ROM decoder, an ROM-data error correcting means that reads from and writes back to the shared memory, and a host output interface. The analysis therefore turns on combination.

Combination 1 (primary): US4802152A in view of US4932018A

Motivation to combine. Both references are in the same field of endeavor — CD signal-processing/drive electronics — and both address the identical system-level problem: the external control microcomputer has a small RAM (US4932018 expressly states the microcomputer RAM is "1K bits at most") and its program load becomes excessive when it must also receive, buffer and re-serve subcode data. US4932018 directly and explicitly solves that problem by placing the subcode storage memory inside the LSI rather than in the microcomputer. US4802152 supplies the CD-ROM-to-host drive architecture (host interface, RS decoding, buffer register). A PHOSITA seeking to offload the microcomputer in a CD-ROM decoder would be led as a matter of ordinary engineering to place the subcode in the decoder's existing buffer RAM instead of the microcomputer's RAM — the very substitution US4932018 teaches, applied to the very drive architecture US4802152 teaches. KSR, 550 U.S. at 417 (predictable use of prior-art elements according to their established functions).

Corroborating reference: US4631714A. Philips teaches that the demodulator already extracts the digital data signals and the digital subcode signals at a common point and routes them into an error-correction circuit containing a buffer register. See https://patents.google.com/patent/US4631714A/en. This supplies the structural predicate for claim 1's single-memory architecture: if data and subcode are already available at the same node, co-locating them in the same RAM readable by the host interface is a predictable design choice.

Result: Claim 1 would have been obvious over US4802152A + US4932018A, further in view of US4631714A. If US5359582A qualifies as prior art on its § 102(e) date, the case is materially stronger and even a two-reference combination (US4802152A + US5359582A) is sustainable: US5359582 discloses serial-to-parallel subcode conversion, an address generator writing subcode bytes into memory in due order, and a timing control writing subcode "according to commands from the control means," i.e., the subcode-reading-means-plus-memory subcombination in essentially the claimed form.

Also note the '952 specification's own admissions, which operate as applicant-supplied motivation: the control microcomputer's jobs "nearly reach the limit of the throughput," its RAM capacity "is difficult to increase," and CD-graphics continuous subcode processing increases the load — with the CD-graphics use case itself documented in US5282186A (Pioneer).

4. Claims 2 and 3 — memory partitioning

Claims 2 (address division) and 3 (time-sharing) recite the two conventional ways to share one RAM between two data types. Neither recites anything beyond predictable memory-allocation technique:

• US5359582 discloses an address generator that increments and supplies addresses to the memory for each successive byte of subcode — i.e., address-based allocation of subcode within a memory (see the "loadable address generator 24" passage in the retrieved text).
• US4631714 discloses a buffer register written at one clock rate and read at another, which is the architectural basis for a memory whose usage is scheduled in time rather than permanently partitioned.
• US4802152 discloses a buffer/rank arrangement in the data path with an interface that must serve host commands and data transfers on a timing schedule.

A PHOSITA given the claim 1 architecture would adopt either address partitioning (when subcode and ROM data must coexist) or time-sharing (when they need not, which saves address space — exactly the trade-off the specification itself recites) as a matter of routine design choice with predictable results. KSR, 550 U.S. at 417, 421. Claims 2 and 3 are therefore obvious over the same combination(s) that render claim 1 obvious.

5. Claim 4 — the "memory access means" write-back claim

Claim 4 is the most defensible claim in the set because it recites a specific architectural tap point: a memory access means that receives a part of the ROM data output from the output interface means (i.e., tapped off the host-bound data stream) and writes it back into the memory.

Combination: US4802152A + US4932018A + US4631714A (and/or the Fujita Sanyo Technical Review article).

• US4932018A supplies the core inventive concept of selective retention: its R/W control circuit writes into the memory circuit only the subcode data recorded in a first (lead-in) area, controlled by data recorded in a second area of the subcode, and makes that retained data retrievable by address from outside. That is the "extract specific data and keep it available for a desired period" function claim 4 performs for ROM data, and it is expressly aimed at the TOC-retention problem the '952 specification identifies ("a table-of-contents data which is called TOC is stored in the innermost periphery of a CD… it is desirable to constantly store the TOC in the CD-ROM decoder").
• US4802152A supplies the path along which corrected ROM data travels to the host controller, and the host interface with which a memory access circuit would necessarily interact.
• The Fujita article describes the applicant's own CD-ROM drive system, including the decoder buffer architecture, and would inform the PHOSITA where in the data path a capture circuit could be inserted.

Motivation. The specification's own statement that TOC retention would be desirable, combined with US4932018A's teaching that specific subcode/lead-in data can be selectively captured into a dedicated memory inside the CD LSI (rather than in the microcomputer) and read out by the external device, provides a clear design incentive. Given that the corrected ROM data stream already passes through the output interface, tapping it and writing the desired portion back into the already-present buffer RAM is an obvious choice among a finite number of identified, predictable solutions. KSR, 550 U.S. at 421.

Caution. I have not verified, from the full texts retrieved, that any single cited reference discloses a capture circuit specifically sourcing its input from the output/host interface stage rather than from the error-correction or read-out stage. US4802152's data path, US4932018's read-out stage, and US5359582's memory write path all lie upstream or at a different node. Claim 4 therefore presents the closest question in the set, and I would rank the § 103 challenge to claim 4 as moderate confidence rather than strong. A challenger would want the Fujita article's full figure set, since it depicts the applicant's own decoder buffer organization.

6. Anticipated rebuttals

1. "Non-analogous art." Expect the patentee to argue US4932018A is a CD-audio player integrated circuit, not a CD-ROM decoder. This should fail: both are in the same field of endeavor (optical disc signal-processing LSIs), and US4631714A and US4802152A themselves bridge audio and ROM use (US4631714 expressly discusses using the CD as a read-only memory; US4802152 is IP-protection-format-agnostic). KSR, 550 U.S. at 402, 417.
2. "Teaching away." US4932018A's complaint that microcomputer RAM is too small to hold the lead-in subcodes points toward, not away from, externalizing subcode storage into the LSI's memory.
3. "Real-time buffer cannot dedicate space." The '952 specification admits the buffer RAM's write/read cycling makes long-term storage difficult; this is a statement of the problem to be solved, not a teaching away from solving it.
4. Secondary considerations. Nothing in the record retrieved shows unexpected results, licensing, industry praise, or commercial success tied to the claimed combination. If the patentee asserts secondary considerations, the nexus must be to the specific claim 4 write-back architecture, not to the general benefits of subcode offloading (which US4932018A and US5359582A already delivered).

7. Bottom line

The single most useful missing verification is the exact US filing date of US5359582A; if it is on or about 1992‑12‑23 as its EP counterpart suggests (EP0550266 filed 1992‑12‑23, KR priority 1991‑12‑28), then under the Hilmer doctrine it is not § 102(e) prior art against the 1992‑11‑20/1992‑11‑26 priority dates, notwithstanding that it appears in the patent's own "Citations" list. Its disclosure is nonetheless the best evidence of what a PHOSITA knew about automatically reading and storing subcode to relieve the system controller, and it can be cited as § 103 art with an effective date equal to its US filing date if any claim is not entitled to the November 1992 priority dates.