US 5913111

I'll search for this specific patent number as requested.

Let me search the USPTO database and CAFC 2026 dockets specifically.

Let me run targeted searches for litigation/appeal records and the USPTO record.

US 5,913,111 — Summary

Important caveat up front: I could not retrieve a USPTO PatentCenter page or any CAFC 2026 docket entry for this number. My searches returned no litigation, IPR/PTAB, or Federal Circuit activity tied to 5913111. The record below is grounded in the authoritative full text supplied for this task and corroborated by Espacenet (which I did retrieve). Where the record conflicts internally, I flag it rather than resolve it.

⚠️ Number-confusion warning: One search hit referenced an "IPR2023-00238" decision discussing "the '311 patent" — that shorthand refers to U.S. 10,334,311 B2, an unrelated patent. It is not US 5,913,111 and should not be conflated with it.

Bibliographic data

On the title: the granted record as fetched spells it "insulaed" (sic). Per the strict rule in this task, I am not auto-correcting it — the misspelling is reproduced literally, though the intended word is plainly "insulated."

Abstract (verbatim)

"This invention provides a transistor manufacture method comprising the steps of forming, on a semiconductor substrate, an insulating film being made open at least in an introducing portion through which an impurity for forming a drain region other than a lightly-doped region is introduced, then forming a gate electrode and a drain electrode each containing an impurity, and then introducing the impurity through between the gate electrode and the drain electrode to thereby form the lightly-doped region; and introducing the impurity from the drain electrode through the impurity introducing portion with heat treatment, to thereby form the drain region. A transistor manufactured by the above method is also provided."

The invention in a nutshell

The patent addresses a known weakness of LDD (lightly-doped-drain) MOSFETs: in the conventional process, the lightly-doped region is defined by side spacers made by etch-back of a CVD SiO₂ film. Because that film varies ~5–10% in thickness across a wafer, the spacer width — and hence the LDD length — varies, which swings transconductance (gm) and hurts device stability. This patent instead defines the lightly-doped region by the gap between two separately patterned electrodes (gate and drain/source), and forms the heavily-doped main drain/source by out-diffusing dopant from the doped polysilicon drain/source electrode through a pre-opened window in the underlying insulating film. The result is a self-aligned LDD structure with much tighter dimensional control.

Independent claims (claims 1 and 5)

The patent has 7 claims; only claims 1 and 5 are independent. Claims 2–4 depend from claim 1; claims 6–7 depend from claim 5.

Claim 1 — method on an insulated semiconductor body. A method of making an insulated-gate transistor having a first-conductivity-type channel and a drain region made of a heavily doped first semiconductor region (second conductivity type) plus an adjacent, more lightly doped second semiconductor region. Steps:

1. Form, on a semiconductor body on an insulator, an insulating film having openings at least at an "introducing portion" through which the impurity for the first (heavily doped) region will be introduced.
2. Form a gate electrode and a drain electrode, each by depositing a conductive layer containing an impurity of the second conductivity type, then patterning (etching) that layer to create gaps.
3. Introduce second-conductivity-type impurity through the gaps between gate and drain electrodes to form the second (lightly doped) semiconductor region.
4. Introduce second-conductivity-type impurity from the drain electrode's conductive layer, through the impurity-introducing opening, by heat treatment, to form the first (heavily doped) semiconductor region.

Plain language: pattern the gate and drain electrodes with a deliberate gap between them; implant through that gap to make the LDD zone; then bake so dopant diffuses out of the doped-poly drain electrode into the substrate to make the main drain. The gap — not a spacer — sets the LDD length.

Claim 5 — same method on an SOI substrate. Identical to claim 1 in every substantive step, differing only in that the insulating film is formed "on an SOI substrate" (rather than on "a semiconductor body on an insulator"). Because claim 1 already recites a body-on-insulator, the two independent claims are closely overlapping in scope; the distinction appears to be one of claim-drafting emphasis rather than a materially different process.

Dependent claims (brief)

• Claim 2 (←1): gate and drain electrodes are polycrystalline silicon containing second-conductivity-type impurity.
• Claim 3 (←1): the semiconductor body is composed of polycrystalline silicon (i.e., a TFT).
• Claim 4 (←1): the gate electrode is split into multiple separated portions, with an added step of forming a region of the same impurity concentration as the lightly doped region between those portions (the "dual-gate"/multi-gate TFT described in the Fourth Example).
• Claim 6 (←5): the conductive layer is patterned by photolithography using an excimer laser.
• Claim 7 (←5): same multi-portion gate limitation as claim 4, applied to the SOI version.

Supporting record and context

• Prior art cited on the face: 17 U.S. patent references, including US 5,200,352 (Motorola, "Transistor having a lightly doped region"), US 5,389,557 (Goldstar, LDD formation), US 4,532,943, US 4,071,545, US 4,991,389, and Canon's own US 5,200,639. Four non-patent citations include P. Ko, "SiGMOS—A Silicon Gigabit/S NMOS Technology," IEDM 1983 Tech. Dig., pp. 751–753, and T. Hosoya, "A Self-Aligning Contact Process For MOS LSI," IEEE Trans. Electron Devices, vol. ED-28, no. 1, Jan. 1981, pp. 77–82 — the latter being directly on-point for self-aligned contacts.
• Two certificate-of-correction-adjacent events: a Certificate of Correction is recorded 2000-03-07, and a first maintenance fee (4-year) was paid 2002-11-22.
• Termination: maintenance-fee reminder 2007-01-03; lapse for failure to pay 2007-06-15; patent discontinued 2007-07-16; lapsed 2007-08-07 (effective 2007-06-15). Anticipated expiration would have been 2016-01-17.
• Family: EP 0723286 A2/A3 (ceased) and JP H08255907 A. The patent has an extensive forward-citation footprint, largely to Semiconductor Energy Laboratory TFT filings.

Confidence and open items

• High confidence on bibliographic data, abstract, and claim text — these are corroborated by both the supplied full patent text and the retrieved Espacenet record.
• Uncertain / not found: I found no CAFC 2026 docket entry, appeal, IPR, or district-court proceeding involving US 5,913,111. That is a null result, not affirmative proof of absence — I could not query the CAFC docket system or USPTO PatentCenter directly with the tools available. Notably, the patent lapsed in 2007, so active 2026 appellate litigation over it would be unusual.
• Source note: the title misspelling ("insulaed") appears in the granted record as fetched; do not infer that the official title is spelled with a double-s.

I'll search for litigation records involving US patent 5913111.

The initial results reference a different patent (10,334,311). Let me search more specifically for litigation involving US 5,913,111.

Let me check litigation databases directly.

Litigation Search Results: US Patent 5,913,111

No litigation involving US Patent 5,913,111 was found.

I searched for this specific patent number across the sources you indicated (Unified Patents litigation portal, CourtListener/PACER-adjacent records, RPX/insight, CAFC opinions, and general litigation reporting) and returned zero matching results for the exact number 5,913,111 (or "5,913,111"). Searches using the exact string returned either unrelated patents (e.g., US 10,334,311 and US 10,652,111, which are different patents entirely) or non-patent coincidental matches (e.g., a Brazilian corporate registration number).

Why no litigation is likely

This is consistent with the patent's profile as reflected in the authoritative patent record:

• Patent: US 5,913,111 — "Method of manufacturing an insulaed gate transistor"
• Inventors: Yuzo Kataoka; Shunsuke Inoue
• Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Priority date: 1995-01-18; Filed: 1996-01-17; Granted: 1999-06-15
• Subject matter: A method of manufacturing an LDD (lightly-doped-drain) insulated-gate transistor using self-aligned lightly-doped regions
• Legal status: Expired – Fee Related. According to the patent's legal-events record, maintenance fees lapsed and the patent expired on 2007-06-15 due to non-payment of maintenance fees under 37 CFR 1.362.

A patent that (a) was held by its original operating-company assignee (Canon) rather than a monetization entity, and (b) went abandoned/expired in 2007, is a strong indicator that it was never asserted in litigation. The record also shows no reissue, no IPR, and no other post-grant challenge documented on the patent page (only a 2000-03-07 certificate of correction and routine fee events).

Important caveats

• Patent term: Even had it been asserted, the patent's enforceable term ended in 2007 (20 years from the 1996 filing / 1995 priority). Any litigation would necessarily predate 2016–2017 at the latest.
• My search coverage is not exhaustive. I could not fully access all of PACER, Docket Navigator, or the complete Unified Patents case list within this search. Terrestrial district-court suits from the late 1990s–2000s are also unevenly digitized, so a very old, low-profile suit cannot be entirely ruled out. However, nothing surfaced, and the patent's expiration-without-assertion profile makes litigation unlikely.
• Distinguish similar numbers: If you intended a different patent, note that US 10,334,311 and US 10,652,111 (both appear in current litigation/IPR activity, e.g., Arista/Cisco/Juniper disputes) are not US 5,913,111.

Bottom line

If you need a definitively negative answer for a freedom-to-operate or diligence opinion, I'd recommend a paid Docket Navigator or Lex Machina query (which have deeper historical coverage than public web sources), but based on all available public evidence, there is no known litigation involving US 5,913,111.

I'll verify the structured data with targeted web searches before reporting.

Let me run additional targeted checks to confirm the absence before reporting.

Proceedings overview

Zero AIA trial proceedings are on file for US 5,913,111. The canonical USPTO Open Data Portal block reports no IPR, PGR, or CBM for this patent, and independent web searches surfaced no PTAB petition, institution decision, Final Written Decision, or Federal Circuit appeal referencing this patent number. The breakdown is therefore 0 active / 0 claims-invalidated / 0 claims-sustained / 0 settled / 0 institution-denied — and the bottom line for a defendant is not "hardened patent" but something stronger: the patent is expired and was never PTAB-tested, so there is no inter partes record to work with, but there is also very likely no live assertion risk.

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No proceedings to enumerate

Because the proceedings list is empty, there is no {PROCEEDING_NUMBER} — {Petitioner} v. {Patent Owner} entry to populate. Stating that plainly rather than padding the section: I found no IPR/PGR/CBM number, no petitioner, no panel, no FWD, and no CAFC docket for this patent in either the structured data or the searches I ran.

False-positive flag (do not import into a chart): My searches repeatedly surfaced U.S. Patent No. 10,334,311 and its IPR2023-00238 (a display-device / external-device-icon case), plus U.S. Patent No. 11,818,591 and U.S. Patent No. 9,799,913. These are different patents that share the trailing "311" or similar numerals. Confusing them with 5,913,111 would put fabricated proceeding numbers into a validity chart. The '311 patent at issue here is the Canon LDD transistor patent, titled "Method of manufacturing an insulaed gate transistor" (sic — the typo is in the granted title).

Searches run: "US5913111 IPR inter partes review PTAB"; "5913111" patent PTAB proceeding petitioner v Canon; "5,913,111" patent IPR petition challenged; Canon "5913111" patent litigation asserted IPR PTAB E2E; "US 5,913,111" OR "5,913,111" ex parte reexamination Canon LDD transistor litigation. None returned a proceeding against this patent. I could not open PTAB E2E or CourtListener directly within this session, so the negative result rests on the structured ODP block plus these searches — strong, but not a substitute for a live E2E docket query.

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Strategic summary

Claim status across the patent. Because no AIA trial was ever instituted, no claim of 5,913,111 has been canceled, confirmed, or amended by the Board. Claims 1–7 all remain in the form in which they issued on 1999-06-15, subject only to a Certificate of Correction recorded 2000-03-07 (a clerical fix, not a substantive narrowing). Independent claim 1 recites the core method — forming an insulating film with openings at the main-drain impurity-introducing portion, forming gate and drain electrodes from a second-conductivity-type conductive layer, patterning by etching to create gaps, implanting through those gaps to form the lightly-doped second semiconductor region, then driving the impurity out of the drain electrode by heat treatment to form the first semiconductor region. Claim 5 is the SOI-substrate variant; claim 6 adds excimer-laser photolithography; claims 4 and 7 cover the split/dual-gate electrode with an intervening lightly-doped region. For a defendant's purposes, all seven claims are UNTESTED by the PTAB — there is no adjudicated invalidity finding to lean on. That is a genuine gap in the defensive record.

Estoppel landscape — essentially none, because no FWD ever issued. Section 315(e)(2) estoppel attaches only to "the petitioner in an inter partes review ... that results in a final written decision under section 318(a)." With no instituted trial and no 318(a) FWD, no petitioner, real party in interest, or privy is estopped as to any claim of this patent. Practically, that cuts both ways: there is no prior petitioner whose estoppel you could inherit or exploit, but equally there is no petitioner-blocked art you'd have to route around. Every § 102/§ 103 ground based on patents and printed publications remains theoretically available to a fresh challenger — the prior-art references cited on the face of the patent (US 3,887,993; US 4,069,067; US 4,072,545; US 4,341,009; US 4,536,943; US 4,992,389; US 4,731,318; US 5,031,010; JPH0194666; US 4,945,070; US 5,200,639; US 5,389,557; US 5,312,518; US 5,200,352; EP0588087; US 5,700,700; US 5,733,803) and the two non-patent citations (P. Ko, SiGMOS—A Silicon Gigabit/s NMOS Technology, IEDM 1983 Tech. Dig. 751–53; T. Hosoya, A Self-Aligning Contact Process For MOS LSI, IEEE Trans. Electron Devices, vol. ED-28, No. 1, Jan. 1981, 77–82) were all before or contemporaneous with the examiner and were largely overcome.

Pattern signals — none, and the reason matters. There is no repeat-petitioner pattern, no defensive aggregator (no Unified Patents, no RPX affiliate) in the chain, and no patent-owner appellate history, because there is no proceeding at all. The more informative signal is the patent's own lifecycle: it lapsed for failure to pay maintenance fees. The legal events are unambiguous — a maintenance-fee reminder mailed 2007-01-03, lapse for failure to pay on 2007-06-15, then "Patent Expired Due to Nonpayment of Maintenance Fees Under 37 CFR 1.362" recorded 2007-07-16, effective 2007-06-15, with the "Lapsed due to failure to pay maintenance fee" entry following on 2007-08-07. The ODP status is "Expired - Fee Related." The patent's 20-year term from the 1995-01-18 priority date would in any event have run out on 2016-01-17 (the anticipated-expiration entry in the structured data). The low assertion history is consistent with this: a patent that lapsed in 2007 and whose term ended in 2016 would not attract IPRs, because there is nothing left to invalidate that a challenger would pay to invalidate.

Statutory note on availability. This is a pre-AIA patent (effective filing 1995-01-18, filed 1996-01-17, granted 1999-06-15). Post-Grant Review is categorically unavailable — it applies only to patents with an effective filing date on or after 2013-03-16. Covered Business Method review is unavailable — this is an LDD transistor fabrication patent, not a "financial product or service" patent. IPR was technically available from 2012-09-16 onward and, per § 311(c), could be filed at any time after the later of 9 months post-grant or PGR termination; the absence of any petition is a function of the patent's commercial death, not of statutory unavailability.

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Recommended next steps

If you are a defendant facing an assertion of 5,913,111: the first move is not a prior-art search, it is to confirm the patent is unenforceable-by-expiration. Per 35 U.S.C. § 286, damages are recoverable only for infringement committed within six years before the complaint is filed, and no infringement can be committed after a patent expires. This patent lapsed on 2007-06-15 and its term would have ended 2016-01-17 regardless. Any demand letter or complaint citing claims 1–7 for conduct after 2007-06-15 (and certainly after 2016-01-17) is asserting a dead patent. Pull the maintenance-fee record from USPTO Patent Center (https://patentcenter.uspto.gov/) to document the lapse, and confirm the pre-§ 1.362 expiration entry dated 2007-07-16.

On the invalidity side, note the gap honestly. There is no FWD to quote, so I cannot give you a disposition — no claim has been canceled, and I will not represent otherwise. If you nonetheless need an invalidity position (for example, to support a declaratory-judgment count or to defeat a pre-expiration damages theory for accused conduct in 2001–2007), you are starting from scratch: no petitioner has been estoppel-bound, but no petitioner has done the work for you either. The strongest structural attack is likely to target the claim-1 limitation requiring the lightly-doped second semiconductor region to be self-aligned to both the gate electrode and the drain electrode via the etch-patterned gap, using the Hosoya self-aligned contact reference (IEEE Trans. Electron Devices, Jan. 1981) and the Ko SiGMOS paper, neither of which appears to have been squarely applied to the "drive-out-diffusion from the drain electrode" step. That said, I cannot vouch for that theory without a full art search, and you should commission one before filing anything.

If you are advising on portfolio or licensing: treat this patent as a shell. The absence of PTAB activity is not a signal of patent strength here — it is a signal that nobody bothered, consistent with a fee lapse in 2007. Do not cite a lack of IPRs as evidence of validity in any diligence memo on this asset.

I'll verify the assignment record against the live sources before reconstructing the chain.

Inventors

Both inventors are named on the US application 08/587,661 (filed 1996-01-17), and both executed the inventor→Canon assignment recorded at Reel 007842 / Frame 0854 with an effective date of 1996-01-05 (12 days before the US filing date). Employer attribution to Canon is an inference from the fact that the sole assignee of record is Canon Kabushiki Kaisha and the assignment was executed pre-filing — the fetched Google Patents record does not expose per-inventor employment lines.

Unusual patterns: none detectable. There is no evidence of inventor departure, no co-assignment to a third party, no reversion, and no partial-interest assignment. The two inventors also appear as joint inventors on the Japanese priority filings (JP7-005808, 1995-01-18; JP7-312344, 1995-11-30), consistent with an in-house Canon R&D team rather than a group assembled for a portfolio sale.

Original assignee

Canon Kabushiki Kaisha (Canon Inc.) — named as original assignee on the issued patent and confirmed as original assignee in the USPTO assignment record (Reel 007842 / Frame 0854).

• Line of business: Precision optics, imaging, and business machines — cameras, copiers, printers, semiconductor and flat-panel lithography equipment, and display components. The patent's own specification ties the LDD transistor to Canon's core product lines: "integrated circuits such as liquid crystal devices and image sensors," with the description further noting that "if a liquid crystal panel is formed by placing a liquid crystal between a substrate including the transistors manufactured according to the present invention and a transparent plate such as a glass base plate, a good liquid crystal device of TFT active matrix type can be provided."
• Did they ship a product embodying the claims? Canon is a large, vertically integrated manufacturing company whose LCD, image-sensor, and ink-jet heater-head businesses are exactly the field the specification addresses. However, I cannot point to a specific commercial part number that practices US 5913111 from the sources available. Treat "Canon shipped products in the claimed technology space" as likely but not independently verified here.
• Current status: Operating, publicly traded, not bankrupt. Canon has never filed for Chapter 7/11 protection. The patent itself, however, is expired for nonpayment of maintenance fees — see the timeline below.

Assignment timeline

The live sources I can reach are consistent, and the record is short. There is exactly one recorded assignment for US 5913111, the original inventor→employer transfer. No post-issuance assignment, security interest, merger, change of name, license, or release has been recorded.

• 1996-01-05 (executed) / recorded 1996-01-17 — Reel 007842 / 0854
  • Conveyance: Assignment — "ASSIGNMENT OF INTEREST" (inventor-to-employer transfer of the entire right, title, and interest)
  • Assignor: YUZO KATAOKA and SHUNSUKE INOUE (joint inventors)
  • Assignee: CANON KABUSHIKI KAISHA (30-2, 3-chome, Shimomaruko, Ohta-ku, Tokyo, Japan)
  • Correspondent: Not exposed in the fetched record. The Google Patents legal-event line for this entry gives only the reel/frame and the free-format text; it does not surface the attorney or agent of record who filed the recording. Because the chain contains only a single link, the "repeat correspondent" heuristic is structurally inapplicable here regardless — there is no second recording to compare against. I will not guess a firm name.
  • Context: Internal first-recordation of an employee invention — the standard pre-issuance inventor-to-employer assignment filed the same day as the US application. Not a fire-sale, not a securitization, not a transfer-to-asserter.

Subsequent USPTO legal events are prosecution/maintenance events only, not conveyances:

Note for accuracy: the nominal 20-year term would have run to 2016-01-17, but the patent actually died on 2007-06-15 for fee nonpayment. Google Patents lists status as "Expired - Fee Related."

Timeline diagram

timeline
    title Ownership of US 5913111
    1995 : Priority filings in Japan
    1996 : US application filed
         : Assigned to Canon Kabushiki Kaisha
    1999 : Patent issued as US 5913111
    2000 : Certificate of correction
    2007 : Lapsed for unpaid maintenance fee

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. No assignment out of Canon exists in the record. The only recorded conveyance (Reel 007842/0854, 1996-01-05) runs inward to the operating company, not outward to a licensing vehicle.

2. Known asserter in the chain — Not present. Neither current nor prior assignee matches any NPE list. The complete set of assignees of record is {Canon Kabushiki Kaisha}. Canon is an operating manufacturer, not on any RPX/Unified/Patent Progress assertion list.

3. Repeat correspondent across the chain — Not present / not applicable. The chain has a single link, so recurrence is impossible by construction. Separately, the correspondent of record is not exposed in the fetched assignment data, so no attorney name can be cited. (Flagging honestly: absence of data here, not a negative finding about any attorney.)

4. Cascading transfers — Not present. Zero transfers in the 24 months after filing, and zero transfers ever after the 1996 first recordation. No chained LLCs, no shared correspondent addresses, no common principals.

5. Pre-litigation transfer — Not present. No infringement suit naming this patent appears in the record, and there is no assignment within 6 months preceding any such suit — indeed there is no post-1996 assignment at all.

6. Bankruptcy fire-sale — Not present. Canon has not filed Chapter 7 or Chapter 11. The ending of the asset's life is a maintenance-fee lapse (2007-06-15, LAPS/STCH), which is an abandonment decision by a solvent owner, not a distressed sale.

7. Privateering — Not present. No NPE assignee exists to assert on Canon's behalf; no SEC 8-K/10-K disclosure of such a transfer is implicated because there is no transfer.

8. Defensive aggregator (anti-NPE) — Not present, but with a related note. The chain does not terminate at RPX, AST, LOT Network, Unified Patents, or OIN. The patent was not neutralized by acquisition; it was neutralized by abandonment — Canon simply stopped paying, and the claims lapsed into the public domain on 2007-06-15. Same practical effect for a would-be asserter, different mechanism.

Verdict

Insufficient data — specifically the "only the original assignment" branch.

The entirety of the recorded chain is a single inventor-to-employer assignment to Canon Kabushiki Kaisha, executed 1996-01-05 and recorded 1996-01-17 at Reel 007842 / Frame 0854; there is no second assignment, no security interest, and no change of name on record. Canon remains the last and only assignee of record, and as an operating manufacturer it is neither on an NPE list nor a defensive aggregator, so none of the eight signals can be marked present — most are affirmatively not present rather than merely unclear. The only event of consequence after issuance is the 2007-06-15 lapse for nonpayment of maintenance fees, which terminated the property before its 2016-01-17 nominal expiry and removed it from assertion entirely.

Verification links:

• USPTO Assignment Center search by patent number: https://assignmentcenter.uspto.gov/
• Alternate USPTO assignment index: https://assignment.uspto.gov/patent/index.html
• Google Patents legal events and assignee record: https://patents.google.com/patent/US5913111/en
• Family members carrying the same priority (JP7-005808 / JP7-312344): EP0723286A2/A3, JPH08255907A

Caveat on sourcing: I was able to confirm the single reel/frame entry (007842/0854) and the full set of USPTO legal events from the fetched Google Patents record, and web searches surfaced no additional assignments. I could not retrieve the correspondent of record (filing attorney/firm) or a reel/frame line item from the Assignment Center UI directly in this session — the live Assignment Center query interface was not reachable through my tools. If you need the correspondent name to complete the repeat-player analysis, that field must be pulled manually from Reel 007842 Frame 0854 in the Assignment Center; I have deliberately not invented it.

I'll search for the USPTO record and prior-art citations for US Patent 5,913,111.

Let me examine the most relevant prior-art references in detail.

Prior-Art Analysis — US Patent 5,913,111

0. Record confirmation (USPTO/patent-family data)

The number 5,913,111 resolves to this Canon LDD-manufacture patent. Similar numbers that appear in unrelated litigation (10,334,311 / 10,652,111 / 7,633,805's citation lists) are different patents and are not treated here.

Methodology note / caveat: The citation list below is taken from the authoritative Google Patents/USPTO record for 5,913,111. I verified the technical substance of the four most relevance-critical references via live search (US 5,200,352, US 5,389,557, US 4,992,389, US 5,733,803). I could not retrieve full specifications/claims of every one of the 17 cited documents in this session, so the per-reference § 102 mapping below is a best-effort analysis flagged as "potential." Anticipation under § 102 requires a single reference to disclose every element of a claim; several references below are more properly § 103 (obviousness) art, and I say so explicitly.

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1. The claim set being tested

• Claim 1 — method on "a semiconductor body on an insulator": form insulating film with openings at the impurity-introducing portion → deposit a second-conductivity-type impurity-containing conductive layer and pattern it by etching to form gaps for gate and drain electrodes → implant through the gaps to form the lightly-doped (second) region → out-diffuse impurity from the drain-electrode conductive layer through the opening to form the heavily-doped (first) region.
• Claim 2 — poly-Si gate/drain electrodes.
• Claim 3 — poly-Si semiconductor body.
• Claim 4 — split (plural) gate electrode with a lightly-doped region formed between the gate portions (dual-gate).
• Claim 5 — claim 1 practiced on an SOI substrate.
• Claim 6 — patterning by photolithography using an excimer laser.
• Claim 7 — claim 4 features on the SOI substrate of claim 5.

The two-point inventive core (per the specification's own framing) is: (a) the lightly-doped region is defined by the etched gap between a doped gate electrode and a doped drain electrode (self-aligned, no spacer dependence), and (b) the heavily-doped region is formed by out-diffusion from the impurity-containing drain electrode.

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2. Full cited-reference inventory (17 patents + 2 NPL)

Dates are as recorded on the 5,913,111 face of the patent.

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3. Detailed § 102 mapping for the most relevant references

A. US 5,200,352 A — Motorola (1991-11-25 / 1993-04-06) — closest LDD art

"Transistor having a lightly doped region and method of formation."

Substance: An LDD process in which a spacer adjacent the gate (and an adjacent dielectric) is removed to create a "doping-accessible portion" of the substrate; the lightly-doped region is then formed through that accessible portion, and a heavily-doped region is formed adjacent the LDD region. Claims 10–20 expressly recite forming LDD source/drain by using a spacer-removal-defined access window, then forming heavily-doped regions, with the LDD region's doping depth greater than the heavily-doped region's. It also describes protecting/separately doping the gate and forming the epitaxial regions, and a bipolar/BiCMOS variant.

Potential § 102 mapping: This reference teaches the general "define the lightly-doped region through an opening between the gate and an adjacent structure, then form the heavily-doped region" concept, which corresponds to the first half of claim 1 (the "second semiconductor region" formed through the gap/opening) and the structural premise of claims 1/5 (LDD contacting a heavier region).

Why it likely does not strictly anticipate claim 1: Motorola's heavy regions are ion-implanted, not formed by out-diffusion from an impurity-containing drain electrode, and its opening is defined by a removed spacer rather than by etching a deposited, impurity-containing conductive layer to create inter-electrode gaps. Those two elements are the novelty of 5,911,111. So US 5,200,352 is best characterized as § 103 art against claim 1 (and would be the primary reference a challenger would combine with a diffusion-source electrode reference such as item C below).

B. US 5,389,557 A — Goldstar/LG (1990-06-30 / 1995-02-14)

"Process for formation of LDD transistor, and structure thereof."

Substance (from the record): Reduces junction capacitance and body effect by arranging that the n+ source/drain junction thicknesses are smaller than the n− region junction thicknesses, with a p-type pocket formed only near the gate. Its lineage (divisional of US 5,262,664, itself a continuation of Ser. No. 07/719,837) is a spacer-based LDD process.

Potential § 102 mapping: Relevant to the structure recited in the preamble of claims 1/5 (n− "second region" of lower concentration in contact with an n+ "first region") and to the dual/junction-depth aspects raised in claim 4's neighborhood. It does not disclose the gap-defined, electrode-out-diffusion method, so it is § 103 background, not anticipation.

C. US 4,072,545 A — IBM (1974-12-03 / 1978-02-07)

"Raised source and drain IGFET device fabrication."

Substance: Raised (elevated) source/drain formed over the substrate, with dopant driven from the raised conductive material into the underlying semiconductor. This is the classic teaching of using a doped conductive electrode as a solid diffusion source into an underlying body.

Potential § 102 mapping: This reference is the strongest § 102 candidate for the "introducing the impurity … from said conductive layer serving as said drain electrode … with heat treatment, to thereby form said first semiconductor region" step of claim 1. However, on its own it does not teach the LDD "second semiconductor region" of lower concentration in contact with the first region nor the gap-defined lightly-doped region, so it does not anticipate claim 1 as a whole; it is the natural § 103 partner to US 5,200,352. (Note: US 3,887,993 and US 4,341,009 are related "doped layer/contact diffusion" teachings in the same vein.)

D. US 4,992,389 A — Toshiba (1985-02-08 / 1991-02-12)

"Making a self aligned semiconductor device."

Substance: A self-aligned device-fabrication technique in which impurity regions are aligned to a patterned electrode structure. Relevant to the self-alignment concept central to claims 1 (self-aligned lightly-doped region) and to the examiner's citation of it as self-aligned-MOS background.

Potential § 102 mapping: Supports the self-alignment premise; does not, on the retrieved record, disclose the specific gap + drain-electrode-out-diffusion combination, so it is § 103 background rather than a single-reference anticipation.

E. US 5,733,803 A — Siemens (1995-09-28 / 1998-03-31)

"Method for producing a multiplicity of microelectronic circuits on SOI."

Substance: SOI-based circuit fabrication.

Potential § 102 mapping: Goes directly to the "on an SOI substrate" element of claim 5 (and claim 7). Two important caveats:

1. Its filing date (1995-09-28) is after the 1995-01-18 priority date, so it is only potentially available as § 102(e) art (and only if its own effective date precedes the relevant invention date) — not § 102(a)/(b). It cannot anticipate claims 1–4/6.
2. Even as to claim 5/7, it is at most art on the substrate element; it does not teach the LDD gap/out-diffusion steps.

F. EP 0 588 087 A2 — Sony (1992-08-20 / 1994-03-23) and US 5,312,518 A — Sony (1991-05-31 / 1994-05-17)

Anti-reflective-layer exposure-condition method; Dry etching method.

Potential § 102 mapping: These are patterning-tool references, relevant at most to the manner of patterning in claim 6 (photolithography) and the "patterning by etching" step of claim 1. Neither discloses excimer-laser photolithography directed to the claimed method; they are § 103 background for claim 6 at most.

G. US 5,700,700 A — Hyundai (1995-06-20 / 1997-12-23)

"Transistor in a semiconductor device and method of making the same."

Caveat: Filed 1995-06-20, after the '111 priority date. It is therefore not § 102(a)/(b) prior art; it could only be considered under § 102(e) (if its own filing/priority precedes the '111 invention date) or as § 103 art. Its inclusion on the face of the patent is most consistent with § 102(e)/103 treatment. I could not retrieve its full text in this session to complete a per-element mapping — flagging as unverified.

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4. Additional relevant art found but NOT on the '111 citation list (flagged)

While researching, a related reference surfaced that is arguably more on-point than some cited items and should be noted for completeness:

• EP 0 145 927 A (discussed within EP 0 293 588 B1's background): teaches forming openings where source, drain and gate will be, forming a highly doped conductive layer on the sidewalls of the openings, and using it to diffuse source/drain regions into the device. This is conceptually close to the '111 gap/out-diffusion approach. It is not listed among the 17 citations of 5,913,111, so it was not part of the examiner's considered art — I flag it because a third party challenging claims 1/5 would likely find it attractive as § 103 art.

I have not verified EP 0 145 927's exact publication/filing dates in this session; treat the above as a lead, not a confirmed citation.

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5. Bottom line

Important legal caveats:

• No single cited reference appears to fully anticipate any of claims 1–7. The distinctive combination in the '111 claims — (i) gaps created by etching an impurity-containing conductive layer, (ii) an implanted lightly-doped region self-aligned in those gaps, and (iii) a heavily-doped region formed by heat-driven out-diffusion from the drain electrode itself — is not, on the retrieved record, met by any one reference. The cited art is overwhelmingly § 103 (obviousness) material.
• Claims 4/7 (split/dual gate with an inter-gate lightly-doped region) and 6 (excimer-laser photolithography) appear to have the thinnest cited-art coverage among the set.
• Claims 5/7's "SOI substrate" limitation is addressed by US 5,733,803, but that reference post-dates the priority date and is available only as § 102(e)/103 art.
• Where I could not retrieve a reference's full specification, I have said so rather than infer its disclosure. If you need a definitive, element-by-element anticipation chart (claim charts against claim 1 and claim 5), I would pull the full text/claims of US 5,200,352, US 4,072,545, US 5,389,557, and US 5,733,803 — that is the set most likely to matter.

I'll ground this obviousness analysis by pulling abstracts/details for the key references listed on the patent page, since the page itself gives only titles and dates.

Obviousness Analysis Under 35 U.S.C. § 103

U.S. Patent No. 5,913,111 — "Method of manufacturing an insulaed gate transistor"

Assignee: Canon Kabushiki Kaisha | Priority: 1995‑01‑18 (JP 7‑005808) | Filed: 1996‑01‑17 | Granted: 1999‑06‑15

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0. Verification / scope note (read first)

This analysis is built on the Prior Art section of the Google Patents page for US 5,913,111 (https://patents.google.com/patent/US5913111/en) — i.e., the 17 examiner‑cited patent references, the 2 examiner‑cited non‑patent publications, and the "Cited By"/family art.

I was able to substantively verify the disclosures of only a subset of the listed references via live search:

Where I assert a reference's disclosure below based only on its title, I flag it. No assertion here should be used in a rejection without pulling the full text. This is an analytical reconstruction, not an infringement- or validity-grade opinion.

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1. Legal framework applied

Under Graham v. John Deere, 383 U.S. 1 (1966), I address: (a) scope and content of the prior art; (b) differences between the claims and the prior art; (c) level of ordinary skill; (d) secondary considerations. Under KSR Int'l v. Teleflex, 550 U.S. 398 (2007), a combination is obvious where the elements are known, the combination is "a predictable variation," and there existed a "design need or market pressure" or "any need or problem known in the field."

Critically, the specification itself supplies the problem and the motivation. US 5,913,111 at col. 1 (Background) expressly concedes that in the conventional sidewall-spacer LDD flow, "a thickness of the SiO₂ film 9 is varied about 5 to 10 % in the wafer plane," and that "variations in the thickness of the SiO₂ film 9 directly affect variations in the size of the side spacers." The stated object (§ "SUMMARY") is only to "improve dimensional accuracy of a lightly-doped region." That is a dimension-control objective, not a new device physics objective — the classic setting for a § 103 rejection.

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2. Level of ordinary skill in the art (POSITA)

As of January 1995: a B.S. in EE/Materials Science (or equivalent) plus 2–4 years of MOS/TFT process-integration experience, familiarity with (i) LDD processing via sidewall spacers, (ii) self-aligned contact/silicide processes, (iii) doped–polysilicon diffusion sources, (iv) ion implantation and drive-in anneals, and (v) conventional i-line/DUV photolithography. Both inventors are Canon process engineers; the art is a mature, crowded one (the 17 cited references span 1972–1995).

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3. Claim 1 — element-by-element mapping

Claim 1 requires, in substance:

No single cited reference appears to disclose all of A–E — in particular, the combination of (i) an LDD defined by a lithographically patterned gap between a gate electrode and a drain electrode patterned from a common doped conductive layer and (ii) an S/D formed by out-diffusion from that drain electrode through an insulating-film opening. The correct statutory ground is therefore § 103, not § 102.

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4. Grounds of rejection

Ground A (strongest) — Admitted prior art + US 5,200,352 + US 4,341,009 / US 3,887,993 (and Hosoya 1981)

The Admitted Prior Art (US 5,913,111 FIGS. 26–30: gate oxide → poly‑Si gate → phosphorus LDD implant → CVD SiO₂ → spacer etch-back → arsenic S/D implant) discloses the complete LDD‑MOS flow except for how the LDD length is set.

US 5,200,352 (Motorola) closes that gap. Verified text and claim 20 teach precisely the concept of defining a doping-accessible LDD window by removing material between two patterned masking structures, then implanting through it — i.e., the LDD length is set by a patterned gap, not by re‑optimizing spacer deposition. '352's LDD regions 28 are "diffusion critical regions," and columns of the specification describe protecting the gate from the LDD implant (KSR "predictable variation").

US 4,341,009 (IBM) and US 3,887,993 (Nippon Electric, "Method of making an ohmic contact with a semiconductor substrate") — titles flagged — supply the "opening in an insulating film through which contact/doping is made" element, which is also old in the admitted art.

Result: Claim 1 obvious. Dependent claims 2 and 3 fall with it: US 4,536,943 and US 5,389,557 both use poly‑Si electrodes, and the '111 specification itself states poly‑Si "is advantageously employed" (col. on Step S3) and that the body may be poly‑Si (Step S1).

Ground B — US 5,200,352 + US 4,072,545 + US 5,389,557

Why a POSITA would look here: IBM '545 (verified) teaches that the S/D can themselves be patterned, protruding conductive regions ("epitaxial regions which are grown from the surface of the silicon substrate so as to protrude above same… serve as low resistivity contacts and have very shallow junctions"). Once S/D are elevated, discretely-patterned conductive structures (i.e., an "electrode" separate from the gate), the '111 structure follows directly. Goldstar '557's verified disclosure of poly‑Si layers, mask‑defined gaps, ion implantation, and subsequent impurity diffusion/activation supplies the remainder.

Ground C — US 5,389,557 + US 3,887,993 / US 4,061,067

Goldstar '557 as primary (LDD, poly‑Si, patterned masks, implant + diffusion), in view of the doped‑layer diffusion‑source art (US 3,887,993; US 4,061,067, Matsushita — titles flagged). Weaker than A/B because Goldstar '557 defines the pocket/LDD relative to a resist mask and sidewall spacer.

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5. Dependent claims

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6. Motivation to combine (the crux)

A POSITA would have been motivated to combine these teachings, for reasons both explicit and inherent:

1. The problem and the solution were both in the art. The '111 Background diagnoses the exact defect (CVD‑thickness variation → spacer‑width variation → gm variation). US 5,200,352 had already addressed LDD‑dimension control by patterning a masking structure and creating a doped gap rather than relying on spacer etch‑back. Motivation: improve reproducibility of a "diffusion critical region" ('352's own words).
2. Doped polysilicon as a diffusion source was standard practice. By 1995, self‑aligned contact/out‑diffusion processes (Hosoya 1981, examiner‑cited; the Toshiba self‑aligned‑device art) were textbook. Using the drain electrode metallization as the S/D dopant source eliminates an implant step and self‑aligns the heavily doped region to the contact opening — an art‑recognized efficiency (compare US 4,072,545, where S/D "serve as low resistivity contacts").
3. Predictable, finite set of options. Defining an LDD window by (a) spacer width, (b) resist mask, or (c) patterned conductive gap is a closed set of known techniques with predictable results — KSR's "combination of familiar elements according to known methods."
4. Design incentive / market pressure. Sub‑micron gate lengths, LCD/image‑sensor TFT integration, and the excimer‑lithography transition are all recited in the '111 specification itself as the field's drivers.
5. Reasonable expectation of success. The elements are structurally compatible: poly‑Si gate and poly‑Si drain electrode patterned from one layer; one implant through the gap; one drive‑in. The '111 examples (FIGS. 4–8) show exactly this — a single poly‑Si deposition, a single pattern step, one implant, one anneal.

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7. Secondary considerations (objective indicia)

The record shows no evidence of secondary considerations:

• No unexpected results — the specification claims only "improve[d] dimensional accuracy," the acknowledged goal.
• No commercial success nexus — Canon never asserted the patent; it expired 2007‑06‑15 for failure to pay maintenance fees (per the patent's legal‑events table).
• No teaching away — the admitted prior art (spacer LDD) and Motorola '352 point in the same direction.
• No licensing program / no industry praise in the record.

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8. Caveats and contradictions to flag

1. Two cited references are NOT prior art on their face. The patent page lists:

• US 5,700,700 (Hyundai) — priority/filing 1995‑06‑20
• US 5,733,803 (Siemens) — filing 1995‑09‑28

Both post‑date the 1995‑01‑18 priority date. They therefore cannot be § 102(a)/(b) or § 102(e) art against this patent (a US application filed after the applicant's invention date is not § 102(e) prior art). Their presence in the citation list is inconsistent with their use in any § 103 rejection — flagging this as an apparent contradiction on the page. In particular, US 5,733,803 cannot be used to render claims 5/7 obvious, and its listing is the reason I could not map the SOI limitation to properly‑dated cited art.
2. EP 0 588 087 A2 (Sony) is directed to "optimum optical conditions for an anti‑reflective layer" — a lithography/optics reference, only tangentially related to the transistor claims. It is likely an IDS/claim‑6‑adjacent citation.
3. US 5,200,639 (Canon) is the assignee's own earlier work — a possible § 103(c)/common‑ownership consideration if ever combined.
4. Under‑verification risk. US 3,887,993, US 4,061,067, US 4,341,009, US 4,992,389, US 4,945,070, US 5,031,010, US 4,731,318, JPH0194666A, US 5,312,518 and both non‑patent publications were mapped by title/citation only. The strongest verified pillars of this rejection are US 5,200,352, US 4,072,545, US 5,389,557 and US 4,536,943.

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9. Bottom line

Overall: Claims 1–4 and 6 are, in my assessment, likely invalid under § 103 as a combination of the admitted LDD prior art with US 5,200,352 (Motorola) and the well‑known self‑aligned/doped‑diffusion‑source contact art (Hosoya 1981; US 4,341,009; US 3,887,993). Claims 5 and 7 are likewise obvious on the merits, but the only SOI reference appearing in the citation record (US 5,733,803) is not prior art by date, so a rejection of those claims from this record alone is unsupported — a properly dated pre‑1995 SOI/TFT reference would be needed.