Invalidity dossier

US 5745727

Linked caches memory for storing units of information

Current assignee: Avago Technologies International Sales Pte Ltd

Added 9/23/2026, 5:02:00 PM

At a glanceNo PTAB challengesNo litigation on file

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Patent summary

Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.

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Patent Overview — US5745727A ("Linked caches memory for storing units of information")

Bibliographic data (from the supplied record). U.S. Patent 5,745,727 A; application US08/843,315, filed 1997-04-15; granted and published 1998-04-28; priority date listed as 1995-05-26; status "Expired – Lifetime," with anticipated expiration 2015-05-26. Inventors: Vi Chau, Stuart Berman, Peter Fiacco. Original assignee: Emulex Corp; current assignee listed as Avago Technologies International Sales Pte Ltd. Classifications: G06F12/08, G06F12/0802, G06F12/0893, G06F12/0897. Source: https://patents.google.com/patent/[US5745727](/patent/US5745727)/en

Purpose. The invention relates to storing information in a computer memory, and more particularly to efficiently storing, in a cache, context information related to frames of data received over a communications link. A stated application is a communications protocol controller such as a Fibre Channel Sequence and Exchange Manager, where each frame has an "Exchange Context" and a "Remote Port Context."

Plain-language scope. Two independent caches are "linked" rather than combined. Each unit in the first cache (e.g., Exchange Context) includes an index—a "Port Context Index"—pointing to its associated unit in the second cache (e.g., Port Context). Because the second cache stores each Port Context only once even when several Exchange Contexts reference it, redundancy and total cache size are reduced. A first cache controller checks the first cache; on a miss, coordination control logic has a microcontroller read the Exchange Context from a main context memory array ("context array"). The index is then passed to the second cache controller to locate the Port Context. A coordination controller ensures misses are handled properly and that information is output only when both caches hit, so the linked caches appear externally as a single "virtual" cache.

What the excerpt does not establish. It gives no complete claim language, so claim scope is not determined. Figures (1, 2a, 2b, 3) and omitted text (including part of the coordination controller description) are not reproduced. It does not establish litigation, ownership-transfer accuracy, validity, or prior art.

Generated 10/1/2026, 9:43:55 PM

Cases on file (0)

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Litigation summary

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Proceedings on file (0)

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PTAB challenges

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Assignment history

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Prior art

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Obviousness

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Extensions

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Derivative works

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