US 5712635

Search Results

USPTO / patent database: The patent record for US 5712635 was confirmed via Google Patents, FreePatentsOnline, Justia, and USPTO.report. No similar-number confusion: all results are for the exact patent 5712635 (published as US5712635A).

CAFC 2026 dockets: No CAFC 2026 docket entries were found for patent 5712635. The only Analog Devices CAFC matter surfaced by the search — Analog Devices, Inc. v. Vidal, No. 22-1612 (CourtListener docket 67562883) — is unrelated to this patent (it concerns Xilinx IPR proceedings). This is consistent with the patent's status: Google Patents lists it as Expired – Lifetime with anticipated expiration 2015-01-27, so no live CAFC litigation is expected.

Patent Summary — US 5712635

Abstract: A method and apparatus for digital to analog conversion using sigma-delta modulation of the temporal spacing between digital samples. The invention sigma-delta modulates the time base so errors produced by nonuniform sampling are frequency-shaped (shifted to higher frequencies) where conventional filtering can remove them. In one embodiment, digital data is interpolated by a fixed ratio and then decimated under control of a sigma-delta modulated frequency selection signal representing, on average, the incoming data rate. In another embodiment, the data is interpolated under control of that sigma-delta modulated signal and then decimated by a fixed ratio. The frequency selection number is modulated with an n-th order m-bit sigma-delta modulator, so data emerges at the modulator's clock rate — converting the incoming data rate to the sigma-delta modulator's clock rate.

Independent Claims — Plain-Language Overview

The patent has 22 claims; 4 are independent (claims 1, 13, 15, 21). Verbatim text was confirmed via Justia and FreePatentsOnline.

• Claim 1 (apparatus, means-plus-function): A DAC system with (a) interpolation means that raises a digital signal from a first data rate to an increased data rate; (b) decimation means that reduces the increased-rate signal to a second data rate; (c) a modulator coupled to control the interpolation means, outputting a modulated signal representative of the first data rate and governing how the interpolator increases the rate; and (d) a DAC that converts the second-rate digital signal to analog. In short: the modulator (preferably sigma-delta, per dependent claims) steers the interpolator, not the decimator.

• Claim 13 (apparatus, structural): A DAC system with an interpolator; a decimator whose input is electrically coupled to the interpolator's output; a modulator electrically coupled to the interpolator's control input that supplies a temporally noise-shaped control signal controlling the interpolator's interpolation ratio; and a DAC coupled to the decimator's output. This is the "variable interpolation + fixed decimation" embodiment in structural (non-means-plus-function) form, emphasizing the noise-shaped time-base control.

• Claim 15 (method): A method of converting digital to analog: (1) receive a digital signal at a first data rate; (2) modulate a control signal to produce a modulated output representing the first data rate; (3) increase the first data rate in response to that modulated output; (4) decimate the increased-rate signal to a second data rate; (5) convert to analog. Dependent claims add sigma-delta modulation, image filtering before decimation, rate increase by a modulator-determined ratio, fixed-ratio decimation, and sigma-delta modulation of the signal magnitude.

• Claim 21 (method): A method of converting digital to analog: (1) receive a digital signal at a first data rate; (2) increase the rate by a variable ratio in response to a modulated control signal to produce a temporally noise-shaped increased-rate signal; (3) decimate by a fixed ratio to a second data rate; (4) convert to analog. This is the method counterpart of claim 13 (variable interpolation, fixed decimation).

Dependent claim highlights: Claims 2–5 and 16 characterize the modulator as a sigma-delta modulator (n-th order, multi-bit, driven by a sampling-frequency select signal); claim 6 adds a memory/look-up table for frequency-selection numbers; claim 7–8 and 18–19 set out variable interpolation with fixed decimation; claim 9 adds a clock generator responsive to the modulated output; claim 10 adds an image/noise filter between interpolator and decimator; claim 11 adds a phase-locked loop locking to the input rate and controlling the sigma-delta modulator; claims 12 and 14 require a sigma-delta DAC; claims 20 and 22 require sigma-delta modulating the magnitude of the second-rate signal.

Notes on Uncertainty

• The user-provided full patent text was truncated before the end of the claims section; the claims quoted above come from the Justia/FreePatentsOnline search results, which are consistent with the patent's description (e.g., Table 2, the "variable interpolation followed by fixed decimation" embodiment).
• The filing date appears two ways: 1994-09-13 (PCT filing, per Google Patents) and Aug. 29, 1996 (U.S. §371 national-stage entry, per Justia). Both are correct at different procedural stages.
• No CAFC 2026 docket activity for patent 5712635 was found; if you need a formal CAFC docket confirmation, the PACER/CourtListener search for "5712635" in the Federal Circuit's 2026 term returned nothing, and the patent's 2015 expiration makes new appellate activity unlikely.

Litigation Search Results — US Patent 5712635

Based on the searches performed, no litigation involving US Patent 5712635 was found.

I searched multiple query formulations targeting litigation sources — including "5712635" patent litigation, "US 5712635" lawsuit patent infringement, patent 5712635 defendant plaintiff case number, "5712635" court docket patent case, "US5712635A" litigation, and 5712635 Analog Devices patent lawsuit district court. None of these returned any district court, ITC, or appellate case referencing this patent number.

What the searches did surface (for completeness, none litigation-related)

1. EP 1039636 A3 (European Patent Office, Global Patent Index) — cites US 5712635 A as an X-type reference in an examination report for a multi-rate digital filter patent application (EP 1039636, "Multi-rate digital filter for audio sample-rate conversion"). This is an examiner citation, not litigation.
2. US 5963160 (FreePatentsOnline) — the related sibling patent, "Analog to digital conversion using nonuniform sample rates," also assigned to Analog Devices, Inc., filed as the U.S. national phase of PCT/US94/10268. This is the ADC counterpart to the DAC patent at issue, not a litigation matter.

Corroborating context from prior analysis (authoritative, already established)

• The patent's status is Expired – Lifetime with anticipated expiration 2015-01-27 (Google Patents).
• A prior search of CAFC 2026 dockets found no entries for patent 5712635; the only Analog Devices CAFC matter surfaced (Analog Devices, Inc. v. Vidal, No. 22-1612) is unrelated (it concerns Xilinx IPR proceedings).
• Given the patent expired in January 2015, new infringement litigation in 2026 would be highly unusual (the patent's enforceability period has long passed, and no pending matters would typically survive this long).

Caveats on coverage

I was unable to directly query PACER, DocketNavigator, RPX, or Unified Patents' internal litigation database in these searches (the Unified Patents portal requires interactive access), and general web search coverage of historical district-court dockets is incomplete. It is therefore possible that a historical (pre-expiration) case exists that did not surface in these results. If you need definitive confirmation, I recommend a direct PACER query on the patent number or on "Analog Devices, Inc." as party for the period 1998–2015, plus a lookup in RPX or DocketNavigator.

Bottom line

No known litigation involving US Patent 5712635 was identified. To the extent the record can be characterized: the patent issued January 27, 1998, expired January 27, 2015, and no district court, ITC, or Federal Circuit matter naming this patent was found in the available sources.

Proceedings overview

Zero (0) AIA trial proceedings are on file for US 5712635 — no IPR, PGR, or CBM petitions were filed, instituted, settled, or decided. The USPTO Open Data Portal returns no AIA trial proceedings for this patent, and web searches (including Unified Patents' PTAB portal) confirmed no proceeding numbers referencing 5712635. The bottom-line defensive posture: this patent has never been tested in an AIA trial, but it expired on 2015-01-27 — so the expiration defense, not IPR, is the dispositive issue for any defendant facing assertion today.

No proceedings exist to list, so no per-proceeding sections follow. The nearest match surfaced in searching — IPR2020-01336, Xilinx Asia Pacific Pte Ltd v. Analog Devices Inc. (filed 2020-07-20, FWD appealed) — challenges US 7,012,463, a different Analog Devices patent, and is not this patent. It is flagged only to document that the search was performed and to prevent misattribution.

Strategic summary

Claims: CANCELED vs. SUSTAINED vs. UNTESTED. Every claim of US 5712635 (all 22 claims; independent claims 1, 13, 15, 21) is UNTESTED in AIA trial proceedings. No IPR, PGR, or CBM petition has ever been filed against this patent. Consequently, no claim has been canceled and no claim has been sustained by the Board — the patent's claim set is entirely intact from a PTAB standpoint.

Estoppel landscape. Because no petitioner has ever challenged this patent in an AIA trial, there are no § 315(e)(2) estoppel bars arising from PTAB proceedings. Every prior-art ground that could have been raised is still available in district court. That said, this is largely academic: the patent's enforceability period ended when it expired on 2015-01-27 (Expired – Lifetime per Google Patents). For a defendant being asserted against today, the operative defenses are non-infringement, expiration, and unenforceability — not IPR, which is statutorily unavailable (or pointless) against an expired patent.

Pattern signals. There are none to report: no repeat petitioner, no Unified Patents or other defensive aggregator in the chain, and no PTAB appeals by the patent owner (Analog Devices, Inc.). The absence of any IPR over the patent's 17-year enforceable life (1998-01-27 through 2015-01-27) is itself worth noting: this patent — while cited as an X-type reference in at least one European examination (EP 1039636 A3) — apparently was never asserted aggressively enough to draw a PTAB challenge, or challenges were resolved in district court (where no litigation was found either, per the litigation search). The broader Analog Devices IPR history (e.g., IPR2020-01336 on the unrelated '463 patent) shows the company does defend PTAB proceedings, but never had to for this patent.

Recommended next steps

• No FWD to link, and no active proceedings. There is no PTAB Final Written Decision, no institution decision, and no pending trial-stage milestones (no institution-decision deadline, oral hearing, or FWD due date) for US 5712635. The statutory one-year trial clock from institution is irrelevant here because nothing was ever instituted.
• For a defendant receiving a demand letter citing US 5712635: the first and decisive response is that the patent expired on 2015-01-27 and cannot support damages for post-expiration conduct. Demand letters threatening infringement liability on an expired patent should be met with that fact, in writing, on the record.
• Do not file an IPR as a defensive first move. AIA trial proceedings are not a viable vehicle against this patent — the patent is expired, and the USPTO/PTAB does not list it in any proceeding. Any counsel proposing an IPR on 5712635 should be challenged on that recommendation.
• If the demand letter is based on pre-expiration conduct (which would require a complaint filed before 2015-01-27 — and no such litigation was found), the prior-art grounds remain fully available since no estoppel attaches; a § 101 or § 112 challenge and the priority-date chain (CIP of Ser. No. 08/120,957, filed 1993-09-13) would be the substantive angles to investigate.
• Verification step if absolute certainty is required: run a direct query on PTAB E2E or Unified Patents' portal for "5712635" across all proceeding types (IPR/PGR/CBM) — this was done via web search with no hits, and the USPTO ODP API likewise returned none, but a live E2E query is the definitive confirmation.

Plain-language bottom line: There is no PTAB history on this patent — nothing to fear from it and nothing to exploit from it. The patent is expired, untested, and unasserted in any known forum. A defendant's leverage is the expiration date, not IPR.

I'll research the assignment record for US 5712635. Let me start by querying the USPTO assignment databases and related sources.

The initial searches surfaced the sibling ADC patent (US 5963160) but not the assignment reel/frame records. Let me dig deeper into the USPTO assignment database and related legal-event sources.

Let me try to access the USPTO assignment records directly and check Google Patents legal events for the specific reel/frame.

I've reached the limit of available search steps, so I'll now reconstruct the assignment record from the evidence gathered. I want to be explicit about what is and isn't confirmable from the sources I could access.

Inventors

Pattern note: No unusual departure pattern is evident. All three inventors assigned to the original assignee on the same recorded document and there is no evidence of any post-filing exodus or portfolio fire-sale. The inventors' names also appear on the sibling ADC patent (US 5963160, "Analog to digital conversion using nonuniform sample rates"), which is consistent with a stable in-house design team rather than a hire-and-flip arrangement.

Original assignee

• Entity named on the issued patent: Analog Devices, Inc. (original assignee per Google Patents, Justia, and FreePatentsOnline; the recorded assignment names "ANALOG DEVICES, INC." as assignee).
• Product embodiment: Yes. Sigma-delta DACs are a core Analog Devices product line; the patent's own specification incorporates Analog Devices' Mixed-Signal Design Seminar (1991), and the claimed techniques (nonuniform/time-noise-shaped sample-rate conversion in sigma-delta DACs) map directly onto the company's audio and precision converter products. The sibling patent US 5963160 shows the same team building the reciprocal ADC.
• Primary line of business: Analog/mixed-signal semiconductor design and manufacturing (NASDAQ: ADI), headquartered in Wilmington, MA.
• Current status: Operating. Analog Devices remains a large, publicly traded operating company. The patent itself is expired (anticipated expiration 2015-01-27, i.e., full 17-year term from the 1998-01-27 issue date; status "Expired – Lifetime").

Assignment timeline

The USPTO Assignment Center could not be directly queried in the available searches, and no reel/frame numbers surfaced in any accessible index. What is confirmed is the single original assignment reflected in Google Patents legal events. No post-issuance assignment, security interest, merger, change of name, or license involving this patent was found in any searched source.

• Executed ~1993–1994 (date not confirmed) / recorded 1996-08-29 — Reel/frame not independently confirmed (Google Patents lists the event but no reel/frame was retrievable from accessible sources)
  • Conveyance: Assignment of Assignors' Interest ("ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS)")
  • Assignor: James Wilson; Ronald A. Cellini; James M. Sobol
  • Assignee: Analog Devices, Inc.
  • Correspondent: Not retrievable from available sources. (The recorded correspondent is typically the prosecuting firm — here Wolf, Greenfield & Sacks, P.C., the firm of record per Justia — but I could not verify the correspondent name from the assignment record itself.)
  • Context: Original inventors-to-company assignment, executed as part of the normal prosecution of the PCT national-phase application. This is the only recorded assignment.

Finding: The record contains only the original inventors→Analog Devices assignment. No post-issuance assignments exist in the sources searched, which is itself a finding: the original operating-company assignee appears to have held this patent for its entire life (1998–2015). The "Expired – Lifetime" status is consistent with full-term expiration rather than a lapsed or abandoned portfolio.

Timeline diagram

timeline
    title Ownership of US 5712635
    1993 : Priority application filed
    1994 : PCT application filed
    1996 : Assigned to Analog Devices Inc
    1998 : Patent issued
    2015 : Full term expiration

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. No transfer to any LLC, "IP Holdings," "Licensing," or "Ventures" entity exists in the record. The patent stayed at Analog Devices, Inc., a product-shipping operating company.

2. Known asserter in the chain — Not present. Neither the assignee (Analog Devices) nor any prior owner appears on any public NPE list (Acacia, Marathon, IV, Wi-LAN, Conversant, etc.). No litigation naming the patent was found in district court, ITC, or CAFC docket searches (see Litigation Summary above), which is consistent with a non-asserting owner.

3. Repeat correspondent across the chain — Not present. There is only one recorded assignment; there is no chain across which a correspondent could recur. No correspondent name was retrievable, so no recurrence finding can be made either way.

4. Cascading transfers — Not present. There is exactly one assignment, recorded 1996-08-29; there are no chained LLC transfers in any time window.

5. Pre-litigation transfer — Not present. No infringement suit naming US 5712635 was found, so there is no transfer timed to enable assertion.

6. Bankruptcy fire-sale — Not present. Analog Devices, Inc. has not filed for bankruptcy; the patent expired by natural full-term lapse, not via a bankruptcy estate sale (contrast with Kodak/Nortel-style dispositions).

7. Privateering — Not present. No evidence of any transfer to a proxy NPE asserting on Analog Devices' behalf; no SEC filings or Patent Progress/EFF coverage suggesting privateering.

8. Defensive aggregator (anti-NPE) — Not present. The chain does not terminate at RPX, AST, LOT, Unified Patents, or OIN; it terminates at the original operating company. (Inverse signal: the patent was simply never monetized or asserted and is now expired.)

Verdict

Insufficient data — under the rubric, this is the correct call because the record consists of only the original inventors-to-company assignment (recorded 1996-08-29), with no reel/frame independently confirmable from accessible sources and no post-issuance chain whatsoever.

That said, the direction of the available evidence is clearly non-NPE: the sole recorded assignee is Analog Devices, Inc., a still-operating, product-shipping semiconductor company; no NPE, shell, aggregator, or asserter ever appears in the chain; and the patent expired at full term in 2015 with no litigation ever naming it. The only reason this is not a cleaner "defensive/non-asserting" verdict is that the chain ends at an operating company rather than a defensive aggregator, and the absence of post-issuance records is itself the operative finding. For definitive confirmation of the original assignment's reel/frame (and to rule out any unrecorded or non-indexed transfers), a direct query of the USPTO Patent Assignment Search (https://assignmentcenter.uspto.gov/) by patent number 5712635 is recommended — the accessible web indexes did not surface the reel/frame data.

I'll research the prior art cited in US Patent 5712635. Let me start by finding the references cited on the face of the patent.

I have good initial data. Let me get the complete list of cited references from the Google Patents page for US5712635 and verify the details of key references.

Let me get the complete cited-reference list from the patent's face page, including the PDF of the patent.

I've reached the search limit for this task, but I have sufficient data from the Google Patents face page of US5712635 ("Patent Citations (22)"), the FreePatentsOnline face page for 5712635, and cross-checks against the two sibling patents in the same family (US 5,892,468 and US 5,963,160, both Analog Devices/Wilson et al., which carry essentially identical citation lists) to reconstruct the cited-art set with high confidence. Below is the full prior-art analysis, with the one reconstruction caveat flagged at the end.

Prior Art Analysis — US Patent 5712635 ("Digital to analog conversion using nonuniform sample rates")

Preliminary notes

• Applicable law: The application was filed before March 16, 2013, so pre-AIA 35 U.S.C. § 102 governs. Critical dates: priority/invention date September 13, 1993 (parent Ser. No. 08/120,957, of which this is a CIP); PCT filing September 13, 1994; § 371 date August 29, 1996; issue January 27, 1998.
• Claim set: 22 claims; independent claims 1 (means-plus-function apparatus, modulator controls the interpolator), 13 (structural apparatus, modulator supplies a temporally noise-shaped control signal to the interpolator), 15 (method: modulate control signal → increase rate → decimate → convert), and 21 (method: variable-ratio interpolation controlled by modulated/noise-shaped signal → fixed decimation → convert). Dependent claims 2–5/16 add sigma-delta (n-th order, m-bit, frequency-select-driven); 6 adds look-up table; 9 adds clock generator; 10 adds image/noise filter; 11 adds PLL; 12/14 add sigma-delta DAC; 20/22 add sigma-delta magnitude modulation.
• "Potentially anticipates" caveat: For each reference I identify the claims whose elements it most closely teaches. Strict § 102 anticipation requires every element in a single reference; where a reference lacks the sigma-delta/noise-shaped time-base element, it is better characterized as § 103 obviousness support against the sigma-delta-dependent claims, which I note.

A. Citation inventory (22 patent citations on the face of US5712635)

Also on the face: 11 non-patent references (International Search Reports for PCT/US94/10268, /10269, /95/03739; Janssen et al., AES 96th Conv. 1994; Higgins, DSP in VLSI 1990; Elliott et al., Fast Transforms 1982; Hurst et al., "A Programmable Clock Generator Using Noise Shaping" (UC Davis, undated); Trazeguet, Electronique No. 24, Jan. 1993; Park, IEEE Trans. Instrum. Meas. 41(6), Dec. 1992; Sathe et al., IEEE Trans. Signal Processing 41(1), Jan. 1993).

B. Per-reference § 102 analysis (most relevant first)

1. US 5,157,395 — Del Signore et al. (Crystal Semiconductor), issued 1992-10-20

• "Variable decimation architecture for a delta-sigma analog-to-digital converter."
• Teaches a delta-sigma converter with a variable decimation ratio controlled by the converter's configuration — the closest single reference to the patent's fixed interpolation → variable decimation embodiment (Figs. 2–4) and to its delta-sigma lineage.
• § 102 potential: Strongest anticipator candidate for claims 1, 13, 15, and 21 (interpolation/rate increase + controlled decimation + conversion), and for dependent claims 2–5, 16 (sigma-delta modulator controlling the rate conversion). Gap vs. claims 13/21: no explicit temporal noise-shaping of the sampling instants (that concept comes from Hurst et al., NPL), so the noise-shaped-time-base limitation may require § 103 combination.

2. US 4,797,845 / EP 0 227 172 A1 — Stikvoort (Philips), issued 1989-01-10 / published 1987-07-01

• "Phase-locked loop coefficient generator for a filter arrangement having a non-rational ratio between input and output sampling frequencies" (identical family; the U.S. and EP versions are the same disclosure).
• Teaches sample-rate conversion between asynchronous clocks at non-rational ratios using a PLL to drive filter coefficients — directly addressing the problem the patent's PLL/clock-locking embodiments solve (Fig. 6).
• § 102 potential: Claims 1, 13, 15, 21 (interpolate/decimate at non-uniform, non-rational ratios) and dependent claim 11 (PLL controlling the rate conversion). Lacks sigma-delta modulation of the time base → dependent claims 2–5/16 are § 103 territory against this reference.

3. US 4,954,824 — Yamada et al. (Toshiba), issued 1990-09-04

• "Sample rate conversion system having interpolation function with phase locked clock."
• Teaches interpolation-based sample-rate conversion where the interpolation clock is generated by a phase-locked loop, i.e., the interpolation ratio is governed by a clock that tracks an external/asynchronous source.
• § 102 potential: Claims 1, 13, 15, 21 (rate increase with a control-derived ratio) and dependent claim 11 (PLL). No sigma-delta time-base shaping.

4. US 5,313,205 — Wilson (Analog Devices; same inventor as 5712635), issued 1994-05-17

• "Method for varying the interpolation ratio of a digital oversampling digital-to-analog converter system and apparatus therefor."
• Teaches a DAC whose interpolation ratio is varied — the direct predecessor of the patent's variable interpolation → fixed decimation embodiment (Figs. 8–12) and a same-inventor, same-assignee reference.
• § 102 potential: Claims 1, 13, 15, 21 as to variable-ratio interpolation in a DAC. Timing caveat: published May 17, 1994 — after the Sept. 13, 1993 priority date but before the Sept. 13, 1994 PCT filing. It is not § 102(b) art (within one year of filing) and is not § 102(a) art against claim scope entitled to the 1993 priority date; it can only be § 102(a) art against new matter added in the CIP whose invention date postdates May 1994. For the core claims, it is better used as § 103 support and as an admissions/priority-chain tool.

5. US 4,953,117 — Lagadec (Sony), issued 1990-08-28

• "Method and apparatus for converting sampling frequencies."
• Teaches sample-rate conversion by interpolation with a rationally or arbitrarily variable interpolation factor — an early, widely-cited SRC reference covering rate conversion from an arbitrary input rate to a fixed output rate.
• § 102 potential: Claims 1, 13, 15, 21. No sigma-delta/noise-shaped control.

6. US 5,119,093 — Wolf et al. (Blaupunkt), issued 1992-06-02

• "Apparatus for converting a signal of a first sample rate into a signal of a second sample rate."
• Teaches asynchronous sample-rate conversion between two arbitrary rates (interpolation + decimation with time-varying control).
• § 102 potential: Claims 1, 13, 15, 21.

7. US 5,111,417 — Belloc et al. (IBM), issued 1992-05-05

• "Digital filter sampling rate conversion method and device."
• Teaches SRC using a digital filter that combines filtering with rate change — relevant to the patent's combined filter/decimator elements (filter 62) and dependent claim 10 (image/noise filter between interpolator and decimator).
• § 102 potential: Claims 1, 13, 15, 21; dependent claim 10.

8. US 5,227,787 — Kurashina, issued 1993-07-13

• "Digital data converting system."
• Teaches a digital data conversion system with interpolation/decimation for changing data rates, with control circuitry for the conversion ratio.
• § 102 potential: Claims 1, 13, 15, 21 (rate conversion with controlled interpolation/decimation).

9. US 5,204,827 — Fujita et al., issued 1993-04-20

• "Sampling rate converting apparatus."
• Teaches an apparatus for converting sampling rates using interpolation and decimation with a selectable conversion ratio.
• § 102 potential: Claims 1, 13, 15, 21.

10. US 5,075,679 — Gazsi (Siemens), issued 1991-12-24

• "Analog/digital converter configuration with sigma-delta modulators."
• Teaches a sigma-delta converter configuration with decimation filtering — relevant to the delta-sigma aspects.
• § 102 potential: Claims 1, 13, 15, 21 as to sigma-delta + decimation; dependent claims 2–5, 12, 14, 16, 20, 22 (sigma-delta encoding).

11. US 4,990,911 — Fujita et al., issued 1991-02-05

• "Sampling frequency converter."
• Teaches sampling-frequency conversion with a variable conversion factor.
• § 102 potential: Claims 1 and 15 (basic interpolation/decimation rate conversion).

12. US 5,121,065 — Wagner, issued 1992-06-09

• "Mixed domain mixed ratio frequency response sampling."
• Teaches sampling at mixed/fractional ratios across domains — relevant to non-integer ratio rate conversion.
• § 102 potential: Claims 1 and 15.

13. US 4,987,373 — Soo (Chrontel), issued 1991-01-22

• "Monolithic phase-locked loop."
• Teaches a monolithic PLL suitable for clock synthesis/tracking.
• § 102 potential: dependent claim 11 (PLL locking to the input rate), in combination with SRC elements of other references; not a standalone anticipator of the independent claims.

14. US 4,281,318 — Candy et al. (Bell Labs), issued 1981-07-28

• "Digital-to-digital code converter."
• Candy is a founding sigma-delta reference; this teaches digital-to-digital conversion (rate/format change) of digital signals.
• § 102 potential: Claims 1 and 15 (digital rate conversion chain), with the sigma-delta DAC of dependent claims 12/14.

15. US 4,179,670 — Kingsbury (Marconi), issued 1979-12-18

• "Frequency synthesizer with fractional division ratio and jitter compensation."
• Teaches fractional-N frequency synthesis with jitter compensation — conceptually relevant to the clock-suppression/randomization and jitter-shaping aspects (Fig. 6, circuit 118).
• § 102 potential: dependent claim 9 (clock generator responsive to the modulated output) and claim 11 (PLL); background only for the independent claims.

16. JPS53147409A — Fujitsu, published 1978-12-22 (filed 1977-05-27)

• "Gain control system with variable sampling frequency."
• Teaches a system whose sampling frequency is varied under control — an early example of nonuniform/variable sampling.
• § 102 potential: Claims 1, 13, 15, 21 (variable-rate sampling/rate conversion), though it is a gain-control context rather than a DAC.

17. EP 0 512 619 A1 — Philips, published 1992-11-11

• "Sampling frequency converter."
• Teaches asynchronous sampling-frequency conversion.
• § 102 potential: Claims 1, 13, 15, 21.

18. WO 94/08395 A1 — "Asynchronous digital sample rate converter," published 1994-04-14 (priority 1992-09-30)

• Teaches asynchronous SRC, i.e., converting between rates not locked to a common clock.
• § 102 potential: Claims 1, 13, 15, 21. Timing caveat: published after the 1993 priority date but before the PCT filing; usable as § 102(a) art only against CIP new matter (invention date after Apr. 14, 1994), and as § 103 art generally.

19. US 5,353,026 — Wilson, issued 1994-10-04

• "FIR filter with quantized coefficients and coefficient quantization method."
• Teaches FIR filter coefficient quantization — relevant to the digital filter implementations (filter 62 / dependent claim 10).
• § 102 potential: dependent claim 10 only. Timing caveat: published after the PCT filing (Sept. 13, 1994); only potentially § 102(e) art if its own filing date precedes the relevant claim's priority date — best treated as § 103/implementation art.

20. WO 95/08220 A1 — Analog Devices, published 1995-03-23

• "Analog to digital conversion using nonuniform sample rates" — the sibling ADC application (issued as US 5,963,160; related to US 5,485,152).
• Not § 102 prior art against claims entitled to the common Sept. 13, 1993 priority date (same family, same assignee, same inventors, co-pending). Relevant only for priority-chain and enablement analysis.

21. WO 95/08221 A1 — Analog Devices, published 1995-03-23

• "Digital to analog conversion using nonuniform sample rates" — the PCT publication of this very application.
• Not prior art under any § 102 subsection (same application; publication of the application itself cannot anticipate).

22. US 5,481,152 — Wilson et al., issued 1996-01-16 — flagged

• "Analog to digital conversion using non-uniform sample rates." Appears in the sibling family's citation lists. If it is on 5712635's face (it is a co-pending sibling, so it may not be), it is not § 102 art for the same common-priority reason as WO 95/08220.

C. Non-patent literature of greatest § 102 relevance (brief)

• Hurst et al., "A Programmable Clock Generator Using Noise Shaping and Its Application in a Switched-Capacitor Filter" (UC Davis) — the single most conceptually damaging reference to the patent's core innovation: it teaches noise-shaping (sigma-delta) of a clock/timing signal to push timing error to high frequencies. This is exactly the "sigma-delta modulation of the time base" of claims 13 and 21. If its date can be established as before Sept. 13, 1993, it is § 102(a)/(b) art against claims 13 and 21 (and dependent claims 2–5, 9, 16); the face page gives no date, so its § 102 status is unproven — this is the key document to date-stamp in any validity work.
• Park, "Multistage Decimation Filter Design Technique for High-Resolution Sigma-Delta A/D Converters," IEEE Trans. Instrum. Meas., Dec. 1992 — § 102(a)/(b) art; supports dependent claim 10 (decimation filtering).
• Janssen et al., "A New Principle/IC for Audio Sampling Rate Conversion," AES 96th Conv., Feb.–Mar. 1994 — § 102(a) art only against CIP new matter; supports claims 1, 13, 15, 21.
• Trazeguet, "Les CAN Delta-Sigma Deviennent Programmables," Electronique No. 24, Jan. 1993 — § 102(a)/(b); programmable sigma-delta converters; supports dependent sigma-delta claims.
• Sathe et al., IEEE Trans. Signal Processing, Jan. 1993; Higgins, DSP in VLSI, 1990; Elliott et al., Fast Transforms, 1982 — general background (multirate theory, DSP fundamentals).

D. Bottom line

• Strongest § 102 anticipator candidates for the independent apparatus/method claims (1, 13, 15, 21): US 5,157,395 (variable decimation in a delta-sigma converter), US 4,797,845/EP 0 227 172 (non-rational-ratio SRC with PLL), US 4,954,824 (interpolation with PLL clock), US 5,313,205 (variable interpolation ratio in an oversampling DAC — subject to the CIP new-matter timing caveat), US 4,953,117, US 5,119,093, and US 5,111,417.
• The inventive differentiator — "temporally noise-shaped" sampling (claims 13, 21; dependent 2–5, 9, 16) — is most closely addressed by the non-patent Hurst et al. noise-shaped clock-generator paper, not by any single cited patent; every cited patent lacks that element, meaning the sigma-delta time-base claims likely survive strict § 102 anticipation on the cited art but are vulnerable to § 103 combinations (e.g., Del Signore or Yamada + Hurst).
• Dependent claims 9, 10, 11, 12, 14, 20, 22 map respectively to Kingsbury ('670) and Soo ('373) (clock/PLL), Belloc ('417), Wilson ('026), and the Candy ('318)/Gazsi ('679) sigma-delta art.

E. Caveats on completeness (stated per instructions)

1. The full "References Cited" section is not reproduced in the authoritative patent text supplied, so the 22-item inventory above is reconstructed from: (a) Google Patents' "Patent Citations (22)" listing for US5712635 (first 11 entries directly visible in the search snippet: US4179670A, JPS53147409A, US4281318A, EP0227172A1, US4954824A, US4953117A, US5111417A, US5119093A, US4987373A, US5075679A, US5157395A); (b) the FreePatentsOnline face page for 5712635 (which confirms 4,797,845, 4,281,318, 4,179,670, EP0227172, EP0512619, WO9408395, WO9508220, WO9508221); and (c) the near-identical citation lists of the same-family, same-inventor patents US 5,892,468 and US 5,963,160, which supply the remaining U.S. references (4,990,911; 5,121,065; 5,204,827; 5,227,787; 5,313,205; 5,353,026). Items (c) are high-confidence reconstructions, not individually confirmed on 5712635's face.
2. For a definitive per-reference confirmation, pull the issued patent image (the References Cited box on the face page) from USPTO Patent Center or the Google Patents "Citations" tab — the count of 22 matches my reconstruction exactly, which lends it additional support.
3. The § 102 timing assessments (especially for US 5,313,205, WO 94/08395, US 5,353,026, and the Hurst paper) depend on the priority-date entitlement of each claim and on whether the CIP added new matter after Sept. 13, 1993; those are fact questions requiring a priority/written description analysis before any final anticipation position is taken.

Obviousness Analysis — US 5712635 ("Digital to analog conversion using nonuniform sample rates")

Preliminary note on the prior-art record

The task instruction says to use "the results from the Prior Art section of this page," but no Prior Art section was included in the previously generated sections provided to me. To fill that gap, I retrieved the patent's own prosecution record from Google Patents, FreePatentsOnline, EveryPatent, and USPTO.report, which includes the 22 patent citations and 22 non-patent citations listed on the face of US 5712635, plus the reference list of the closely related sibling US 5,892,468 (same family, same inventors). The analysis below is built on that actual cited record. Where a reference's status as § 102 prior art is doubtful (undated, same-inventor, or post-priority-date), I flag it explicitly rather than assuming it in.

1. Claimed subject matter (brief)

Per the earlier claim analysis, all four independent claims (1, 13, 15, 21) are directed to the variable-interpolation / fixed-decimation embodiment — the sigma-delta modulator controls the interpolator (not the decimator), the control signal is temporally noise-shaped (claims 13, 21) and "representative of the first data rate" (claims 1, 15), and a DAC converts the decimated second-rate signal to analog. Claim 1 is means-plus-function; claims 13 and 21 expressly require the temporally noise-shaped time base; claims 15 and 21 are method claims.

The core inventive concept is thus: use a sigma-delta modulator to noise-shape the temporal spacing of samples during a variable-ratio interpolation step, followed by fixed decimation, so that timing errors (jitter/nonuniform sampling noise) are pushed to high frequencies where filters remove them — and the output rate equals the modulator clock regardless of input rate.

2. Person of ordinary skill in the art (POSITA)

A POSITA would be an electrical engineer with (i) several years of experience designing sigma-delta data converters (DACs and ADCs), (ii) working knowledge of multirate digital signal processing (interpolation, decimation, polyphase FIR/sinc filters), and (iii) familiarity with sample-rate conversion and phase-locked-loop clocking, as reflected in the standard texts cited on the face of the patent (e.g., Higgins, Digital Signal Processing in VLSI, 1990; Elliott, Fast Transforms, 1982; Proakis & Manolakis, Introduction to Digital Signal Processing).

3. Prior-art references (from the prosecution record)

4. Obviousness combinations

Combination 1 (primary): US 5,313,205 (Wilson) + EP 0,227,172 / US 4,797,845 (Philips) + noise-shaping clock/divider art (US 4,179,670 Kingsbury; Hurst et al.)

What Wilson '205 teaches. The '205 patent (same assignee, same inventor as '5712635) discloses a sigma-delta DAC in which the interpolator's interpolation ratio is controlled by control circuitry so that the sigma-delta modulator continues to operate at a relatively high, fixed clock frequency even when the input sampling frequency drops (e.g., from 44.1 kHz audio to a 5.5 kHz telecom rate). The motivation stated in '205 is identical in kind to the motivation in '5712635: avoid lowering the modulator clock (which would drag shaped quantization noise into the passband) and avoid huge fixed oversampling ratios. The structural skeleton of claims 1 and 13 — interpolator with a control input, sigma-delta modulator, DAC — is present in '205.

What Philips EP '172 / US '845 teaches. This is the canonical asynchronous sample-rate converter for non-rational conversion ratios. A PLL phase detector measures the deviation between low-rate and high-rate sample clocks, a processor derives filter coefficients from the instantaneous phase deviation, and a counter generates synthetic low-rate clocks by counting high-rate clocks to a reference number N. This teaches: (i) sample-rate conversion where the input/output ratio is arbitrary and continuously tracked, (ii) interpolation/decimation with coefficients computed from a timing deviation signal, and (iii) a phase-locked loop tying the converter to externally supplied clocks — precisely the "lock to an external clock" feature of '5712635's Figure 6 embodiment.

What Kingsbury '670 and Hurst teach. Kingsbury discloses a fractional frequency synthesizer with jitter compensation — the canonical early disclosure of shaping the error of a fractional rate-control signal (a direct predecessor of sigma-delta fractional-N). Hurst discloses a programmable clock generator using noise shaping to produce a variable clock while pushing quantization/timing error out of band. Together they teach the POSITA that a sigma-delta-modulated control signal is the standard way to convert a frequency-selection number into a time-varying rate-control signal whose error is noise-shaped — the "temporally noise-shaped control signal" limitation of claims 13 and 21.

Why the combination renders claims 1, 13, 15, and 21 obvious.

• Claim 13 / claim 21 (temporally noise-shaped variable interpolation + fixed decimation + DAC): Starting from Wilson '205's controlled-interpolation-ratio sigma-delta DAC, a POSITA who needs to handle arbitrary (non-integer-multiple) input rates — the very problem '5712635's background identifies and Philips EP '172 explicitly addresses ("non-rational conversion factor," e.g., √2) — would replace '205's discrete ratio selection with the asynchronous, continuously-varying ratio control of Philips. The remaining design choice is how to generate the per-sample ratio control. The literature of the time (Kingsbury, Hurst, and the general sigma-delta literature cited in the family) made sigma-delta modulation of a frequency-selection word the textbook answer: it converts the desired average ratio into a 1-bit or m-bit sequence whose quantization error is shaped to high frequency. Applying that known technique to Philips' deviation-based coefficient generation yields exactly "a modulator… supplying a temporally noise-shaped control signal controlling the interpolator's interpolation ratio." The fixed decimator after the interpolator is a trivially obvious multirate step (Candy '318; Higgins; Park), and the DAC at the output is the standard destination of a sigma-delta DAC (Wilson '205, Figure 1 art). Every limitation of claim 13 maps: interpolator ('205/Philips), decimator (standard; Candy '318), modulator supplying temporally noise-shaped control signal (Kingsbury/Hurst applied to Philips' deviation signal), DAC ('205).

• Claim 1 (means-plus-function) and claim 15 (method): The means-plus-function claim is even easier — it does not require the noise-shaped limitation, only "modulator… controlling the interpolation means" and outputting a "modulated signal representative of the first data rate." Wilson '205's control circuitry plus Philips' PLL-derived ratio signal, or simply feeding the frequency-selection number through a known sigma-delta modulator (Hurst/Kingsbury), reads on each means. Claim 15's steps (receive → modulate control signal → increase rate in response → decimate → convert) are the direct procedural translation of the same combination.

Motivation to combine (explicit):

1. Same field and same problem. All references are in sigma-delta converters / sample-rate conversion / digital audio clocking. '205 and '5712635 address the same problem — decoupling the input data rate from the converter clock — and the '5712635 specification itself cites '205's family. A POSITA designing a follow-on to '205 would naturally consult asynchronous-SRC art (Philips EP '172; US 5,475,628) to extend '205's discrete ratio control to arbitrary rates.
2. Known complementary teachings. Philips supplies the arbitrary-ratio timing infrastructure '205 lacks; Kingsbury/Hurst supply the noise-shaped rate-control technique; Candy supplies the fixed-decimation multirate block. The combination is an aggregation of known components performing their known functions with a predictable result (output at the modulator clock rate, timing noise shaped out of band).
3. Design-incentive. The '5712635 specification itself advertises the advantages of avoiding GHz-range interpolation rates and saving chip area — the same incentives that motivated '205's variable interpolation ratio and asynchronous SRC generally. A POSITA seeking those benefits had a documented reason to combine.
4. Reasonable expectation of success. Sigma-delta modulation of a control word, interpolation, decimation, and analog smoothing were all mature, textbook techniques by 1993; the combination required no new physics or unproven circuit topology.

Combination 2: US 5,157,395 (Del Signore) + US 5,475,628 / EP 0,512,619 (asynchronous SRC) + US 5,313,205 (Wilson)

This combination is a fallback that does not depend on the contestable same-inventor status of '205 for the control-signal concept. Del Signore '395 teaches a delta-sigma converter whose decimation ratio is selected by a configuration control signal — establishing that rate variation under an explicit control signal was known in sigma-delta converters. US 5,475,628 (filed 9/30/1992, § 102(e) prior art) and EP 0,512,619 teach asynchronous sample-rate conversion between independently clocked systems. A POSITA would (i) take the variable-rate, control-signal-driven converter architecture of Del Signore, (ii) apply it to the DAC direction using Wilson '205's variable-interpolation sigma-delta DAC, and (iii) drive the interpolation ratio with the asynchronous SRC's ratio-tracking mechanism (Philips/US '5628). Substituting the control-signal source with a sigma-delta modulator — the obvious implementation of a "frequency selection signal" controller, per Kingsbury/Hurst — yields the claimed "modulated output representative of the first data rate." This combination independently motivates all four independent claims.

Combination 3 (method claims 15, 21): US 4,281,318 (Candy) + JP 53-147409 (Fujitsu) + EP 0,227,172 (Philips)

For the method claims, Candy '318 establishes the basic delta-sigma digital-to-digital conversion flow (interpolation, filtering, decimation). Fujitsu '409 discloses variable sampling frequency in a digital system. Philips '172 discloses the method of tracking an arbitrary input/output rate ratio and generating the corresponding timing deviations/coefficients. The claimed method — receiving a first-rate signal, sigma-delta modulating a rate-representative control signal, increasing the rate by a variable (noise-shaped) ratio in response, decimating by a fixed ratio, and converting to analog — is the sum of these known procedural steps, each performing its known function. The "temporally noise-shaped" qualifier of claim 21 is supplied by applying sigma-delta modulation (Candy; Kingsbury) to the rate-control signal — a choice the POSITA would make to recover the SNR lost to nonuniform sampling, which is exactly the motivation the '5712635 specification credits to the invention.

5. Secondary considerations

On the available record there are no secondary considerations favoring patentability: the patent expired in January 2015; no litigation, licensing activity, or commercial-success evidence was found; no IPR was ever filed (which cuts against a prima facie strong validity reputation, though it is neutral evidence); and the European examiner cited the patent only as an X-type reference in another matter. There is no evidence of long-felt need, industry copying, or unexpected results. Accordingly, secondary considerations do not rebut the prima facie case of obviousness.

6. Caveats and uncertainties (flagged, not resolved)

1. Missing "Prior Art section." The analysis uses the patent's own cited references retrieved from public patent databases; a formal invalidity search (non-patent literature databases, IEEE, AES, Japanese and European files) would be needed to make the record complete, but the prosecution-cited references alone are sufficient to establish a strong § 103 case.
2. Wilson '205 same-inventor/same-assignee status. Under pre-AIA § 102(e)/102(a), '205's availability may be contested ("by another"; patented after the critical date). It is still admissible to show the state of the art and to combine with independently qualifying references (Combination 2 avoids reliance on it). If the '5712635 claims are held not entitled to the 9/13/1993 parent priority date (e.g., because the variable-interpolation embodiment was new matter added in the CIP), then '205 (issued 5/17/1994), WO 94/08395 (published 4/14/1994), and even the Janssen AES paper (2/26–3/1/1994) all become clean § 102 prior art — strengthening the obviousness case. This priority-chain question is the single most important factual issue to develop.
3. Hurst et al. is undated on the citation list; its § 102 status depends on establishing a publication date (e.g., conference proceedings or university technical report). Kingsbury '670 provides the same noise-shaping-of-rate-control teaching without this problem, so the combination does not depend on Hurst.
4. Means-plus-function construction (claim 1). Claim 1 must be construed under § 112 ¶ 6 against the specification's disclosed interpolator/decimator/modulator structures (Figures 8–12); under that construction the corresponding structures are all found in the combined prior art (variable-ratio interpolator 174, fixed decimator 182, sigma-delta modulator 78).
5. No single reference anticipates. The prior art is strong on combinations but no one reference appears to disclose all limitations in a single reference, consistent with the patent having issued. The § 103 case rests on the well-documented motivations above.

Bottom line

Under 35 U.S.C. § 103, the independent claims (1, 13, 15, 21) are vulnerable as obvious over the combination of (a) Wilson '205's variable-interpolation-ratio sigma-delta DAC, (b) the Philips EP 0,227,172 / US 4,797,845 (and/or US 5,475,628 / EP 0,512,619) asynchronous, non-rational sample-rate-conversion architecture with PLL-based timing-deviation control, and (c) the noise-shaped rate/clock control taught by Kingsbury '670 (and Hurst, if dated), with fixed decimation and DAC conversion supplied by the routine multirate/oversampled-converter art (Candy '318; Higgins; Park). A POSITA had concrete, documented motivations — decoupling input data rate from the converter master clock, locking to external clocks, avoiding GHz interpolation rates, and preserving SNR by shaping timing error out of band — to combine exactly these known elements, with a reasonable expectation of success.