Invalidity dossier
US 5483173
Current measuring structure for testing integrated circuits
Current assignee: STMicroelectronics SRL
Added 9/23/2026, 11:25:25 AM
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Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Patent Overview — US 5,483,173 A
Title: Current measuring structure for testing integrated circuits
Assignee/Original Assignee: STMicroelectronics SRL; originally SGS Thomson Microelectronics SRL
Inventor: Franco Pellegrini
Dates: Priority 1992-09-30; filed 1993-09-30; granted/published 1996-01-09; anticipated expiration 2013-09-30; status listed as "Expired – Fee Related" [as printed: "Expired - Fee Related"]
Purpose: The patent addresses testing of integrated circuits, including wafer testing (EWS—Electrical Wafer Sort) and final testing of packaged chips. Measuring high currents at wafer test is problematic due to high-energy voltage spikes from parasitic inductance, pad/probe wear and aging, and difficulty correlating wafer and final test measurements caused by differing power dissipation. Reducing the limiting-circuit reference voltage V R for wafer testing is described as limited by amplifier offset (1–2 mV) and noise, yielding excessive measurement spread.
Plain-language scope: A current measuring circuit for testing integrated circuits includes a current sensor having an electrical resistance, plus current measuring means connected to the sensor that generates a signal based on current through the resistance, and means integrated with the sensor for varying that resistance. In the described embodiment, the resistance comprises a first metal strip; the varying means comprises a second metal strip connected to the first at a common terminal; each strip has an end with a second terminal connected to inputs of the current measuring means, preferably an operational amplifier. Current is measured at the common terminal and at the second terminal of the second strip. A contact coupled to the terminal may be connected or left floating, selectively varying the resistance. A resistive element formed in the integrated circuit and series-connected to the current/voltage resistor is activated during testing, providing a scaling factor K between nominal intervention currents at final and wafer test. Good matching of contiguous resistors formed at the same manufacturing stage is emphasized; scaling factors of 10–15 with mismatching estimated at a few percent. The structure may also modulate current supply to a terminal during normal operation.
Source: https://patents.google.com/patent/US5483173/en
Not established by the excerpt: Complete claim wording, full description and figures, prosecution history, the exact meaning of "Expired – Fee Related," and any litigation, ownership transfer, validity, or prior-art determinations.
Generated 10/1/2026, 9:53:58 PM
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Prior art
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