US 5010355

I'll verify current status via search, then summarize.

US Patent 5,010,355 — Verification & Summary

Search status / caveat up front: I ran targeted searches for the exact number 5010355 / 5,010,355. I found no district court docket, IPR/PGR, or CAFC appeal involving this patent. Note that I cannot directly query PACER or the CAFC docket system — that conclusion rests on web-search indexing, so treat it as "nothing found," not as a certified negative. It is also consistent with the record itself: the patent is marked Expired – Lifetime with an anticipated expiration of 2009‑12‑26, so a pending 2026 CAFC appeal is essentially implausible. No results for similar numbers were substituted.

Bibliographic data

Source: https://patents.google.com/patent/US5010355/en

Term note: For an application filed before 1995‑06‑08, the URAA term is the greater of 17 years from issue (2008‑04‑23) or 20 years from filing (2009‑12‑26) — hence the 2009‑12‑26 expiration date. Maintenance fees were paid at years 4 (1994), 8 (1998), and 12 (2002).

Minor record discrepancy (flagged, not corrected): the Google Patents "Priority Applications" table lists the DE family member (DE69013480T2) under the title "Color jet print head with ionic passivation of the electrical circuits," whereas the EP/JP/US family members carry the "Ink jet printhead…" title. The DE abstract content is not in the record I have, so I can't resolve whether this is a translation/record artifact or a different family member.

Abstract (as issued)

An improved ink jet printhead of the type having parallel ink flow channels terminating in droplet-emitting nozzles, a heating element with a cavitational protective layer in each channel, and MOS electronic circuitry monolithically integrated in the printhead for pulsing the heating elements so that bubbles form on the protective layer and expel droplets. The improvement is multi-layer ionic passivation of the ink-exposed MOS circuitry: a first layer of doped or undoped silicon dioxide (200 Å to 2 µm) followed by a second layer of plasma nitride (1000 Å to 3 µm). The nitride is etched from the heater protective layers and the external-contact pads so the oxide is exposed, then the oxide is etched from those same areas. In an alternate embodiment, the passivation is three thin films: polyimide (ink-facing) / silicon nitride / doped-or-undoped silicon dioxide (metallization-facing).

Plain-language overview of the independent claim (claim 1)

Claim 1 is a Jepson-style improvement claim. The preamble assumes the conventional architecture: parallel capillary ink channels, each open at one end as a nozzle and communicating at the other end with an ink reservoir; a heating element with a cavitation-protective layer over it, positioned a set distance upstream of each nozzle; and MOS driver circuitry monolithically integrated on the printhead to pulse the heaters and create the ejection bubbles.

The recited improvement is ionic passivation of that MOS circuitry by a two-layer thin-film stack:

1. Layer 1 — doped or undoped silicon dioxide, 200 Å to 2 µm, deposited directly over the MOS circuitry and over the heating elements/protective layers.
2. Layer 2 — plasma nitride (silicon nitride), 1000 Å to 3 µm, over the oxide.

Then the defined patterning sequence (which the claim expressly makes functional):

• The nitride is dry etched over the heater protective layers and the external-power contact pads, exposing the underlying oxide.
• The oxide is then etched to remove it from those same protective layers and pads.

The claim states the resulting advantages: the etch sequence prevents attack on both the contact pads and the heater protective layers; the MOS circuitry is concurrently protected from mobile ions in the ink; and the printhead remains cost-effectively manufacturable with a cavitation-protective heater layer for longer heater life. The underlying rationale in the specification is that tantalum protective layers are roughened by dry etching (shortening heater life), so the oxide must be removed by a wet etch selective against Ta — which is why the oxide is the layer directly on the heater.

Analyst note on numeric ranges: claim 1's ranges are broader than the preferred embodiment disclosed for FIG. 2 (oxide 500 Å–1 µm, preferred 1000 Å; plasma nitride 2500 Å–2 µm, preferred 1 µm). The claim also quantifies the etch order and method (dry etch for nitride, then etch for oxide) rather than leaving it functional — likely the point of novelty relative to the cited sealing/passivation art (e.g., Haskell, US 4,686,559).

Dependent claims (2–6), briefly

• Claim 2 (dep. 1): Adds a photopatternable thick-film layer (≥ 8 µm) on the silicon nitride, patterned to form heater pits for bubble containment and an ink flow passage between reservoir and channels.
• Claim 3 (dep. 1): Adds a third layer of polyimide, ≥ 1.5 µm, etched off the heaters and contact pads. Stated benefits: added resistance to ionic contamination, lower electric fields within the film, and excellent adhesion to the plasma nitride.
• Claim 4 (dep. 3): The polyimide is ≥ 8 µm, so it itself provides the heater pits and reservoir-to-channel ink passage — eliminating the separate thick-film layer of claim 2.
• Claim 5 (dep. 3): Instead, a separate photopatternable thick film (≥ 8 µm) is deposited on the polyimide and patterned for bubble-containing pits and the ink flow passage.
• Claim 6 (dep. 3): The third layer is two polyimide layers — a first (≥ 1.5 µm) on the nitride left intact, and a second (≥ 8 µm) patterned for pits and the flow passage — preserving the full polyimide / silicon nitride / phosphorus-doped-or-undoped silicon dioxide three-layer passivation for maximum ionic protection.

Note the claim set therefore covers three distinct routing schemes for the hexaflorinated "pit + flow passage" function: thick film over nitride (2), thick polyimide alone (4), thick film over polyimide (5), and dual polyimide (6).

Prior art cited on the face (11 references)

US 4,298,629 (Nozaki, Fujitsu); US 4,463,359 (Ayata, Canon); US 4,647,472 (Hiraki, Tokyo Shibaura); US 4,686,559 (Haskell, AMD); US 4,699,825 (Sakai, Hitachi); US 4,638,337 (Torpey, Xerox); US Re. 32,572 (Hawkins, Xerox); US 4,719,477 (Hewlett‑Packard); US 4,774,530 (Hawkins, Xerox); JP 61‑135755 (Watanabe, Canon); JP 61‑291149 (Katano, Ricoh).

Two of these (4,647,472 and 4,686,559) are the passivation/sealing references most directly relevant to the claimed multi-layer scheme; 4,774,530 and Re. 32,572 are the assignee's own printhead-architecture references, and 4,638,337 is the thick-film/bubble-containment reference. The specification also cross-references co-pending US App. Ser. No. 354,941 (filed 1989‑05‑22, Hawkins et al.) for separately optimized heater passivation, and Ser. No. 336,624 (continuation filed 1989‑04‑07) for the MOS switch itself (that application's subject matter corresponds to US 4,947,192).

Forward citations of note (per Google Patents; the page inconsistently reports both a 38‑entry and a 57‑entry "Cited By" table): US 5,187,499 (Canon — protective layer with ion exchanger), US 5,969,392 (Xerox — power MOS drivers with enhanced transconductance), US 5,729,261 and US 5,751,316 (Xerox — ink-resistant coatings), and US 6,549,911/EP 1,125,746-type ink-barrier adhesion art.

Explicit uncertainties

• Litigation: No case, docket number, or CAFC appeal for '355 was located. This is a search-based negative, and given the 2009 expiration the assertion that no 2026 CAFC matter exists is well-founded but not from a primary docket source.
• Current ownership: The last assignment of record is to Samsung Electronics (2005). Whether Samsung (or a successor) still nominally holds the expired patent is not determinable from the record; no post-2005 assignment appears in the Google Patents legal-events list.
• Google Patents "Cited By" counts are internally inconsistent (38 vs. 57), so forward-citation counts should not be relied on without checking USPTO Patent Center directly.

I'll research litigation involving US Patent 5010355.

Let me search more targeted litigation databases.

Let me check litigation-specific databases with more targeted queries.

Litigation Search Results: US Patent 5,010,355

Bottom line: I found no record of any litigation — district court, ITC, or Federal Circuit — involving US Patent 5,010,355.

Here is what I was able to determine, along with explicit limitations on my search.

What I checked

The literal string "5010355" returns only unrelated Brazilian court docket numbers, Greek operational-program codes, and a financial-disclosure investment ID — nothing patent-related.

Patent context relevant to litigation likelihood

• Patent: US 5,010,355 — "Ink jet printhead having ionic passivation of electrical circuitry"
• Inventors: Hawkins, Burke, Roll, Hartman, Atkinson
• Original assignee: Xerox Corp. (filed 1989-12-26; granted 1991-04-23)
• Assignment history (recorded, not litigation): Xerox → Samsung Electronics Co., Ltd. (recorded 2005-02-18, effective 2005-01-13); multiple security-interest and release events involving Bank One and JPMorgan Chase
• Current listed assignee: [Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.
• Legal status: Expired – Lifetime (anticipated expiration 2009-12-26)
• Family: EP 0434946B1, JP H0688414B2, DE 69013480T2 — all also expired/not active

The assignment/security-interest records above are ownership transfers, not infringement suits, and should not be mistaken for litigation.

Important caveats — please read

1. I could not directly query the authoritative litigation databases. I was not able to open and search PACER (CM/ECF), the CAFC docket, or the Unified Patents litigation portal (portal.unifiedpatents.com/litigation/caselist) directly; my tool returned aggregated search results rather than those databases' records. My conclusion is therefore based on secondary/aggregated sources, not a first-hand docket check.
2. Xerox historically litigated its thermal ink jet patents, but generally against competitors over the fundamental printhead architecture patents (e.g., the Re. 32,572 family) — and I have no verified evidence tying '355 itself to any such suit.
3. This is not a legal opinion on whether the patent was ever asserted. Absence of a hit in the sources I could reach is not proof of absence of litigation.

Recommended verification steps (authoritative)

To reach a definitive answer, the following should be run directly:

• Unified Patents Litigation Portal: https://portal.unifiedpatents.com/patents/5010355
• USPTO Patent Center "Litigation" / assignment tabs for 07/456,431
• PACER full-text search across all district courts for "5,010,355" or "5010355"
• CAFC docket search for the patent number
• Westlaw / LexisNexis / Docket Alarm patent-number search (these index complaint exhibits by patent number)

If you would like, I can make additional targeted attempts against any one of those sources (e.g., the Unified Patents portal URL directly) if you can confirm I should retry a specific site.

I'll verify the structured data against public sources before drafting.

Proceedings overview

Total AIA trial proceedings on file for US 5,010,355: zero (0). There are no IPRs, no PGRs, and no CBMs — active: 0; claims invalidated: 0; claims sustained: 0; settled: 0; institution denied: 0. The USPTO Open Data Portal returns no AIA trial proceedings, and independent keyword searching of PTAB materials for the patent number surfaced none. This is not, however, a signal that the patent has "survived" anything: the reason there are no AIA trials is structural — the patent expired on 2009-12-26, roughly two and a half years before inter partes review even became available (IPR petitions first became possible on 2012-09-16). No petitioner ever had an economically rational window in which to file one. For a defendant today, the bottom line is not "this patent is hardened" but "this patent is a corpse" — its entire term ran out on 2009-12-26, so the only theoretically live exposure is back damages, and only for acts within the § 286 six-year lookback measured from the filing of any complaint.

No proceedings to report

Structural bars, not "no one tried": The patent's term expired 2009-12-26 (Google Patents records the status as "Expired - Lifetime," with anticipated expiration on that date). AIA trials did not exist during the patent's entire enforceable life. See the patent record: https://patents.google.com/patent/US5010355/en.

Verification performed. I searched PTAB-specific sources and general web indexes for the patent number in combination with IPR/PGR/CBM terminology. Results returned only unrelated matters (other patents' institution decisions discussing Fintiv and § 315(e), a Brazilian court case with the docket number 5010355-65.2018.4.03.6100, and a citation of the EP counterpart EP0434946 in a PCT search report). No PTAB proceeding number for this patent appeared.

Confidence and limits — stated explicitly:

• High confidence that no IPR/PGR/CBM was ever instituted against US 5,010,355.
• Lower confidence that literally no petition was ever filed and denied institution. The ODP block provided to me is the canonical AIA-trial list and is empty; denial decisions are reviewable only in limited circumstances and leave little public trace. I could not hit PTAB E2E (https://ptacts.uspto.gov/ptacts/) or Docket Navigator directly in this session. Treat "zero filings" as ~90% confident and "zero institutions" as high confidence.
• Important scope gap: the ODP field covers AIA trials only. It does not capture ex parte reexamination, inter partes reexamination (available for this 1989-era patent), or pre-AIA interferences. My web searches surfaced no reexamination certificate for this patent either, but I would not represent that as established. Pull the patent's full file wrapper on USPTO Patent Center before relying on this.
• Note also the family member whose Google Patents title reads "Color jet print head with ionic passivation of the electrical circuits" (DE69013480T2) — that title appears to be a data artifact; it does not indicate a separate US proceeding.

Cross-reference links for the record: USPTO PTAB decisions — https://www.uspto.gov/patents/ptab/decisions ; PTAB E2E — https://ptacts.uspto.gov/ptacts/ ; CourtListener — https://www.courtlistener.com/ .

Strategic summary

Claim status. All six claims — 1 (independent) and dependents 2–6 — are UNTESTED by any AIA tribunal. Nothing has been canceled, nothing has been confirmed. There is no FWD, no certificate of cancellation, and therefore no claim-level invalidation to lean on. Equally, there is no adverse PTAB holding you must work around. The claims as issued are the claims you face, and they have never been construed by the Board. (Claim 1 recites the two-layer oxide/plasma-nitride ionic passivation with the specific dry-etch-nitride-then-wet-etch-oxide sequence; claims 3–6 add polyimide layers and the ≥8 µm "pit" variants.)

The real defense here is the calendar, not the PTAB. The patent expired 2009-12-26. That means: (a) no injunctive relief is available as a practical matter; (b) damages reach only acts before expiration and, per 35 U.S.C. § 286, only those within six years before the complaint was filed; (c) any accused product must have been on sale/used in that window; and (d) for an expired patent the Board will not permit claim amendments in an IPR, which removes a patent owner's usual escape hatch. Because no IPR was ever instituted, § 315(e)(2) estoppel binds no one — a defendant retains the complete universe of § 102/§ 103 art, including art the examiner never saw (the file history credits Re. 32,572; U.S. 4,463,359; 4,638,337; 4,774,530; 4,717,477; 4,298,629; 4,647,472; 4,686,559; 4,699,825; JP 61-135755; and JP 61-291149 as the cited art). Since this is a 1989-filed patent, an IPR remains legally available even now (the Board does institute on expired patents), but institution requires an economic reason, and there is generally none post-expiration.

Pattern signals. There is no petitioner, so no repeat-petitioner pattern; no PTAB appeal history, so no aggressive appellate posture by the patent owner; and no defensive aggregator (Unified Patents or similar) in the chain. The ownership trail runs Xerox → Samsung Electronics Co., Ltd. (assignment recorded 2005-02-18, effective 2005-01-13), with the intervening Bank One / JPMorgan Chase security-interest assignments typical of Xerox — those are liens, not ownership transfers, and have all been released. The absence of any IPR is not a "well-asserted patents attract IPRs" signal in this instance, because the assertion-relevant life of the patent predates the IPR regime entirely. Do not read the clean PTAB record as evidence of validity or as evidence of assertability.

Recommended next steps

1. Lead with expiration, not invalidity. Before spending on prior art, confirm standing to sue and the damages window. If a demand letter cites US 5,010,355, the dispositive question is whether the accused activity occurred before 2009-12-26 and within § 286's six-year lookback from the complaint date. If not, the demand has no damages theory, and there is no injunction to buy off.
2. Pull the complete file wrapper on USPTO Patent Center (https://patentcenter.uspto.gov/) and confirm in writing that there is no ex parte reexamination certificate, no reissue, and no certificate of correction affecting the claims. My searches found no reexamination, but the ODP block I was given covers only AIA trials — this gap must be closed before you rely on "no PTAB activity" in any filing or opinion letter.
3. Confirm the AIA-trial picture directly. Query PTAB E2E (https://ptacts.uspto.gov/ptacts/) by patent number and by the parties (Xerox Corporation and [Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.) rather than by patent number alone, and search Docket Navigator / Lex Machina for any district court case naming the patent so you can tie any § 315(b) clock to a service date.
4. If you are drafting an invalidity position: use the freedom from § 315(e)(2) estoppel. Because no IPR was instituted, you are not limited to "grounds you raised or reasonably could have raised" before the Board — you may raise any § 102/§ 103 combination, including art in the cited-art list above, in district court.
5. Do not oversell the absence of proceedings. The correct statement to a client is: "No AIA trial has ever been brought against this patent, because it expired in 2009 — two and a half years before IPR existed. That tells us nothing about validity and everything about timing." If you need a one-line defensive posture: the patent is expired with no PTAB record; there are no canceled claims to cite and no surviving-claim narrowing to attack — the case is a damages-window case, or it is nothing.

I'll verify what I can about the ownership chain before writing this up.

Two quick follow-ups to confirm the 2005 Xerox→Samsung deal and whether any correspondent data is retrievable.

Assignment Record Reconstruction — US 5010355

Data provenance note (important): The reel/frame numbers, conveyance types, execution dates and recording dates below are taken from the free-format assignment data in the Google Patents legal-events record for this patent (source: https://patents.google.com/patent/US5010355/en, fetched 2026-09-24). The source does not expose the "correspondent of record" field — no attorney, firm, or service address is present in any of the eight entries — and the USPTO Assignment Center record could not be retrieved in this session. I have therefore left correspondent fields explicitly marked not available rather than inferring them. Signal #3 below is reported as unclear for that reason, not as "not present."

Inventors

Patterns: None unusual. All five inventors assigned to Xerox Corporation ~5 weeks after the 1989-12-26 filing date — the routine employment-obligation assignment, not a late or forced conveyance. No inventor reappears as an assignor, assignee, or party in any later recording in this chain. There is no evidence of the team departing Xerox within 12 months of filing, and no evidence of any inventor-side entity (inventor-holding LLC, etc.) later surfacing. Specific Xerox site (Webster NY vs. Wilsonville OR) is not determinable from the record.

Original assignee

Xerox Corporation, Stamford, Connecticut, a corporation of New York (per the 1990-02-09 recording, Reel 005258/0502).

• Product embodiment: Yes — Xerox was the originator of the two-part thermal ("bubble") ink jet printhead described here and commercialized it in its desktop/SOHO inkjet product line. Xerox's own 10-K describes the subsequent "disengagement from SOHO, our former consumer/personal [printing] business" (https://xerox.gcs-web.com/static-files/cddb748c-dfa7-4c79-a7c6-7179fe7779f5), which is the strategic context for the 2005 divestiture of the inkjet portfolio.
• Primary line of business: Document technology — copiers, printers, MFPs, supplies.
• Current status: Operating. Renamed Xerox Holdings Corporation (2018–2019); no Change of Name conveyance was recorded against this patent.

Current recorded owner of record: Samsung Electronics Co., Ltd. (Suwon, KR), per the assignment effective 2005-01-13, Reel 015687/0884, and confirmed as "Current Assignee" on Google Patents.

Family/bibliographic oddity worth flagging: the German family member DE69013480T2 is titled "Color jet print head with ionic passivation of the electrical circuits" — the trailing "s" and the inserted "Color" do not match the US/EP title. I have not verified whether this is a translation artifact of a family filing or a distinct document; noted for accuracy, not relied on for any conclusion below.

Assignment timeline

Eight assignment-type events are recorded against US 07/456,431. Listed chronologically by recording date:

• 1990-02-01 (executed) / recorded 1990-02-09 — Reel 005258/0502

  • Conveyance: Assignment
  • Assignor: Hawkins, William G.; Burke, Cathie J.; Roll, Daniel O.; Hartman, Pamela J.; Atkinson, Diane
  • Assignee: Xerox Corporation (Stamford, CT, a corp. of NY)
  • Correspondent: not available in source
  • Context: initial inventor-to-employer assignment of rights.

• 2002-06-21 (executed) / recorded 2002-06-28 — Reel 013153/0001

  • Conveyance: Security Interest
  • Assignor: Xerox Corporation
  • Assignee: Bank One, NA, as Administrative Agent (Illinois)
  • Correspondent: not available in source
  • Context: securitization — a blanket portfolio lien, not a patent-specific transaction. The same reel/frame 013153/0001 appears in the recorded history of unrelated Xerox patents (e.g., US 5,850,476), confirming a portfolio-wide credit facility.

• 2003-06-25 (executed) / recorded 2003-10-31 — Reel 015134/0476

  • Conveyance: Security Agreement
  • Assignor: Xerox Corporation
  • Assignee: [JPMorgan Chase Bank, as Collateral Agent (Texas)](/asserters/jpmorgan-chase-bank-as-collateral-agent-texas)
  • Correspondent: not available in source
  • Context: securitization — second blanket portfolio lien, replacing/superseding the Bank One facility.

• 2005-01-13 (executed) / recorded 2005-02-18 — Reel 015687/0884

  • Conveyance: Assignment (of interest — outright transfer, not a license)
  • Assignor: Xerox Corporation
  • Assignee: Samsung Electronics Co., Ltd. (Korea, Republic of)
  • Correspondent: not available in source
  • Context: portfolio/business divestiture — Xerox exited the consumer/SOHO inkjet business and its inkjet patent estate moved to Samsung. Corroborating third-party evidence of the same transfer across the Xerox inkjet estate: the UK/EP register for a related Xerox inkjet case records Samsung Electronics Co. Limited registered as proprietor in place of Xerox Corporation "by virtue of deed of assignment dated 01.04.2005" (https://www.search-for-intellectual-property.service.gov.uk/cy/EP89312194.7/history). Note the deed date on that sibling case (2005-04-01) differs from the US effective date (2005-01-13); these may reflect staged closings, and I do not treat the EP date as governing the US record.

• 2005-03-30 (executed) / recorded 2005-04-01 — Reel 016408/0016

  • Conveyance: Release (Release of Patents)
  • Assignor: JPMorgan Chase Bank, N.A.
  • Assignee: Xerox Corporation
  • Correspondent: not available in source
  • Context: lien release — release of the 2003 security agreement against the divested assets.

• 2003-06-25 (executed) / recorded 2014-06-06 — Reel 033098/0737

  • Conveyance: Release of Security Interest
  • Assignor: Bank One, NA
  • Assignee: Xerox Corporation (New York)
  • Correspondent: not available in source
  • Context: lien cleanup — release of the 2002 security interest, recorded ~11 years after execution.

• 2006-12-04 (executed) / recorded 2014-11-24 — Reel 034435/0817

  • Conveyance: Release by Secured Party
  • Assignor: JPMorgan Chase Bank, N.A.
  • Assignee: Xerox Corporation (New York)
  • Correspondent: not available in source
  • Context: lien cleanup — a second, later-dated JPMorgan release.

• 2022-08-22 (executed) / recorded 2022-09-07 — Reel 066728/0193

  • Conveyance: Release by Secured Party
  • Assignor: JPMorgan Chase Bank, N.A., as successor-in-interest administrative agent and collateral agent to JPMorgan Chase Bank
  • Assignee: Xerox Corporation (Connecticut)
  • Correspondent: not available in source
  • Context: final lien cleanup — administrative release of residual security interests, recorded 17 years after the asset had already been sold to Samsung.

Structural note on entries 5–8: Each release names Xerox, not Samsung, as the released party. That is because these are blanket corporate-lien releases executed against the grantor of record for the security interests (Xerox), not re-conveyances of this patent. They do not undo the 2005 Samsung assignment. A reader skimming the "Assigned to XEROX CORPORATION" labels in 2014 and 2022 could easily misread the chain as reverting to Xerox — it does not. There are exactly one title-transferring assignment (2005, Reel 015687/0884) and nine security/release events.

No NPE assignment of any kind appears in this chain, and no assignment to HP Inc. is recorded, notwithstanding HP's 2016–2017 acquisition of Samsung's printer business — Samsung remains the assignee of record for this patent. Whether that business transaction carried this specific patent is not evidenced by any recorded assignment; treat as unclear.

Timeline diagram

timeline
    title Ownership of US 5010355
    1989 : Filed 26 December by Xerox inventors
    1990 : Inventors assign to Xerox Corp
    1991 : Patent issued 23 April
    2002 : Security interest to Bank One
    2003 : Security agreement to JPMorgan Chase
    2005 : Assigned to Samsung Electronics
         : Lien release recorded
    2009 : Patent term ends
    2014 : Lien releases recorded
    2022 : Final lien release recorded

NPE / troll-pattern signals

1. Shell-entity transfer — not present. The only title-transferring assignment is Reel 015687/0884 (effective 2005-01-13), Xerox Corporation → Samsung Electronics Co., Ltd., a publicly listed operating manufacturer. No entity bearing an "IP / Patents / Licensing / Holdings / Ventures" suffix appears anywhere in the chain. The bank parties (Bank One, JPMorgan Chase) are collateral agents under security agreements, not licensing vehicles.

2. Known asserter in the chain — not present. Neither assignee nor assignor in any of the eight entries matches a public NPE list (Acacia, Marathon, IV, IPNav, Wi-LAN, Mosaid/Conversant, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Document Generation Corp, Spangenberg entities). I found no RPX/Unified Patents listing tying this patent number or its two owners to NPE assertion activity. Note: the "estimated economic value" figure shown on third-party aggregator pages (e.g., patentleaderboard.com/patent/5010355) is a valuation estimate, not evidence of assertion, and I do not treat it as a signal.

3. Repeat correspondent across the chain — unclear / unverifiable from the source used. The Google Patents legal-events data for US 5010355 does not carry the correspondent-of-record field, so I could not determine whether one attorney or firm filed all eight recordings. The only recurrence visible in the data is a party recurrence, not a correspondent recurrence: JPMorgan Chase Bank appears as secured party in Reels 015134/0476, 016408/0016, 034435/0817, and 066728/0193. That is a lender with a captive portfolio, not a shell-LLC attorney. Action item for verification: pull each of the eight reel/frame entries in USPTO Assignment Center and record the correspondent; if a single attorney recurs across the 2005 Samsung assignment and the 2014/2022 releases, that would be a genuine finding — but it cannot be asserted from the data available here.

4. Cascading transfers — not present. One substantive title transfer in 20 years of recorded history (1989 filing → 2009 term end), plus one 2005 release. No chained LLC-to-LLC conveyances, no shared correspondent addresses, no transfers clustered inside 24 months.

5. Pre-litigation transfer — not present. No infringement action naming US 5010355 was located in the searches performed. Independent of that: Google Patents records the patent as "Expired – Lifetime" with an anticipated expiration of 2009-12-26 (20 years from the 1989-12-26 filing), and the last maintenance-fee event in the source is the year-12 payment recorded 2002-08-26. A patent whose term ended in 2009 could not have been the subject of a post-2009 pre-litigation transfer. (I flag the apparent absence of a later maintenance-fee payment event as unclear — that may be a gap in the aggregated data rather than a lapse.)

6. Bankruptcy fire-sale — not present. Xerox did not file for bankruptcy protection, and no Chapter 7/11 sale order or trustee conveyance appears in the record. The 2002 and 2003 security interests are ordinary corporate credit-facility liens, evidenced by the fact that the identical Reel 013153/0001 lien appears against unrelated Xerox patents.

7. Privateering — not present. The 2005 transfer ran from an operating company to a competing operating company (Samsung), i.e., a market-exit divestiture, not an operating company placing patents with an NPE to assert against rivals. No accompanying offensive campaign against Xerox competitors is evidenced for this patent.

8. Defensive aggregator (anti-NPE) — not present. The chain terminates at Samsung Electronics, an operating manufacturer. It does not reach RPX, AST, LOT Network, Unified Patents, or OIN.

Verdict

Operating-company assertion

The entire recorded chain consists of operating companies — inventors → Xerox Corporation (Reel 005258/0502, 1990) → Samsung Electronics Co., Ltd. (Reel 015687/0884, effective 2005-01-13) — with the intervening entries being a blanket portfolio lien and its releases (Reels 013153/0001, 015134/0476, 016408/0016, 033098/0737, 034435/0817, 066728/0193), none of which is a licensing-vehicle transaction. Zero of the eight NPE signals is present at high confidence; the one "unclear" (signal 3, repeat correspondent) is a data-availability gap, not an observed pattern. Caveat on the label: the "assertion" prong is not demonstrated — I found no infringement suit naming US 5010355, and the patent's recorded term ended 2009-12-26 — so the practical conclusion is "clean operating-company ownership chain, no NPE involvement," which is the closest available match among the enumerated verdicts.

Verify at: USPTO Assignment Center — https://assignment.uspto.gov/patent/index.html (search patent number 5010355) and https://assignmentcenter.uspto.gov/ — check the correspondent-of-record on Reels 005258/0502 and 015687/0884 to close out signal 3, which is the only open question in this chain.

I'll start by searching for the specific patent number to confirm its identity and citation data.

Let me gather details on a few of the cited references to ground the analysis.

I searched for and confirmed the patent. Below is the prior-art analysis. Note on methodology: the "prior art" that the examiner actually cited against US 5,010,355 is the set of 11 references appearing on the face of the patent as "Patent Citations (11) — * Cited by examiner." I have used that set (not the "Cited By" forward citations such as US5187499 or US5969392, which post-date the patent). All 11 cited references have publication dates before the '355 priority date of 1989‑12‑26 and therefore qualify as prior art under 35 U.S.C. § 102(a)/(b).

Identification of US 5,010,355

The invention is a two‑part thermal ink jet printhead whose heater plate carries monolithically integrated MOS driver circuitry that is protected from the mobile ions in the ink by a multi‑layer ionic passivation (SiO₂ + plasma nitride, optionally + polyimide). The independent claim is claim 1; claims 2–6 are dependent.

The 11 examiner‑cited references

1. US 4,463,359 A — Ayata et al.

• Full citation: US 4,463,359 A, "Droplet generating method and apparatus thereof," Canon Kabushiki Kaisha. Priority 1979‑04‑02 (JP); granted 1984‑07‑31.
• Description: The foundational bubble‑jet/thermal ink jet reference. Discloses a substrate bearing heater elements H1–H7 and electrodes, overlaid by an SiO₂ protective layer K (~1 µm), a grooved plate forming liquid chambers over the heaters, and a bubble formed on the heater to eject a droplet. Also discloses time‑division drive circuitry.
• § 102 relevance: This is the primary structural reference for the "thermal ink jet printhead … heating element … protective layer" environment of claim 1 and for the SiO₂ protective layer. It does not disclose MOS driver circuitry integrated in the printhead, plasma nitride, or the oxide/nitride etch sequence, so it does not anticipate claim 1 or any dependent claim. It is best characterized as a § 103 base reference (the admitted prior art in the '355 background).

2. US 4,471, NOT — corrected: US 4,719,477 A — Hewlett‑Packard

• Full citation: US 4,719,477 A, "Integrated thermal ink jet printhead and method of manufacture," Hewlett‑Packard Company. Filed/priority 1986‑01‑17; granted 1988‑01‑12.
• Description: A combined printhead and on‑chip pulse‑driver IC. A first level of metallization (refractory metal) defines the lateral dimension of the printhead resistor; a passivation layer or layers are deposited atop this metallization and patterned with openings for a second level of aluminum metallization that interconnects the resistors to MOSFET drivers fabricated in the same silicon substrate. This "on‑chip driver" construction is expressly stated to move pulse‑driver transistors onto the printhead substrate.
• § 102 relevance: Most relevant single reference. It teaches the "MOS electronic circuitry monolithically integrated within the printhead" element of claim 1 and a patterned passivation layer over the metallization. It does not disclose the claimed doped/undoped‑SiO₂‑then‑plasma‑nitride stack, the 200 Å–2 µm / 1000 Å–3 µm thickness ranges, or the dry‑etch‑nitride/wet‑etch‑oxide sequence, and it is silent on mobile‑ion passivation versus ink. It therefore does not anticipate claim 1; it is a strong § 103 reference. (Notably, this HP patent is listed on the face of the '355 patent but is not discussed in the '355 background section.)

3. US Re. 32,572 E — Hawkins et al.

• Full citation: US Re. 32,572 E, "Thermal ink jet printhead and process therefor," Xerox Corporation. Listed priority 1985‑04‑03; granted 1988‑01‑05.
• Description: Two‑part printhead in which a flat heater plate (linear array of heating elements plus addressing electrodes) is aligned and bonded to a channel plate having an anisotropically etched manifold and parallel grooves; mass‑fabrication via wafer‑level alignment and dicing. Cited in the '355 background as the source of the dicing/isotropic‑etch means for opening the grooves to the manifold.
• § 102 relevance: Relevant to the printhead architecture of claim 1 (channels, nozzles, reservoir, heating elements) and to the "other means of providing the flow path" discussion supporting claims 2/5/6. No MOS integration and no ionic passivation, so it does not anticipate claim 1.

4. US 4,638,337 A — Torpey et al.

• Full citation: US 4,638,337 A, "Thermal ink jet printhead," Xerox Corporation. Filed/priority 1985‑08‑02; granted 1987‑01‑20.
• Description: Thermal ink jet printhead in which each heating element sits in a recess; a thick‑film organic structure (e.g., Riston®) between the heater plate and channel plate forms recesses/pits directly over the heating elements to contain the bubble and suppress vapor blowout/air ingestion.
• § 102 relevance: Directly relevant to the "pit for the heating elements to aid in the suppression of ingestion of air" limitations of claims 2, 4, 5 and 6. It does not disclose the ionic‑passivation stack of claim 1, so it cannot anticipate any claim alone.

5. US 4,774,530 A — Hawkins

• Full citation: US 4,774,530 A, "Ink jet printhead," Xerox Corporation. Filed/priority 1987‑11‑02; granted 1988‑09‑27.
• Description: Upper and lower substrate mated with a thick insulative layer sandwiched between; recesses patterned in the thick layer expose the heating elements (placing them in a pit) and provide an ink flow path from the manifold around the closed groove ends.
• § 102 relevance: Highly relevant to the thick‑film layer, heating‑element pit and reservoir‑to‑channel flow passage recited in claims 2, 4, 5 and 6, and to the base printhead environment of claim 1. No MOS drivers, no SiO₂/plasma‑nitride ionic passivation → no anticipation of claim 1.

6. JP 61‑135755 A — Watanabe (Canon)

• Full citation: JP 61‑135755 A, "Preparation of liquid jet recording head," Canon Inc. Published (laid open) 1986‑06‑23; priority 1984‑12‑06.
• Description: Thermal ink jet printhead with an array of heating elements and addressing electrodes on a substrate; the electrodes and heating elements are covered by an SiO₂ layer; a light‑curable photosensitive layer is patterned to form flow‑passage walls, and a glass plate is adhered to form the channels.
• § 102 relevance: Relevant to the SiO₂ overcoat over heaters and electrodes and to thick‑film photosensitive flow‑passage walls (cf. claim 2's photopatternable thick film). Does not disclose nitride/polyimide ionic passivation or monolithic MOS drivers → no anticipation.

7. US 4,298,629 A — Nozaki et al.

• Full citation: US 4,298,629 A, "Method for forming a nitride insulating film on a silicon semiconductor substrate surface by direct nitridation," Fujitsu Limited. Filed/priority 1979‑03‑09; granted 1981‑11‑03.
• Description: Direct nitridation of silicon in a nitrogen‑containing gas plasma at 800°–1300 °C to form a dense, low‑oxygen silicon‑nitride film.
• § 102 relevance: Materials/process reference supporting the concept of a silicon‑nitride (plasma nitride) passivation layer. It is a non‑analogous‑art‑type teaching for the "second layer of plasma nitride" of claim 1; it does not disclose a printhead and does not anticipate any claim.

8. US 4,686,559 A — Haskell

• Full citation: US 4,686,559 A, "Topside sealing of integrated circuit device," Advanced Micro Devices, Inc. Filed/priority 1984‑08‑03; granted 1987‑08‑11.
• Description: Hermetically sealing an IC with a silicon‑nitride layer deposited directly on the surface, followed by a second protective oxide layer; the nitride and oxide are concurrently patterned to expose the metallization for electrical contact. Nitride thickness 2000–6000 Å, deposited at 300°–450 °C.
• § 102 relevance: The closest of the materials references to the multi‑layer nitride‑over‑oxide (reverse order) passivation concept and to exposing contact pads by patterning. It is a thin‑film IC passivation teaching, not a printhead, and does not disclose the claimed oxide‑then‑nitride order or the ink‑immersion/mobile‑ion environment; no anticipation.

9. US 4,699,825 A — Sakai et al.

• Full citation: US 4,699,825 A, "Method of forming silicon nitride film and product," Hitachi, Ltd. Filed/priority 1984‑11‑14; granted 1987‑10‑13.
• Description: Low‑pressure CVD formation of a uniform silicon‑nitride film on silicon wafers (pressure 0.05–0.25 Torr; temperature 650°–1000 °C).
• § 102 relevance: Process reference for depositing the silicon‑nitride layer. Supports the feasibility of the "plasma nitride" layer of claim 1 but is not a printhead and does not anticipate.

10. US 4,647,472 A — Hiraki et al.

• Full citation: US 4,647,472 A, "Process of producing a semiconductor device," Tokyo Shibaura Denki Kabushiki Kaisha. Filed/priority 1982‑12‑24; granted 1987‑03‑03.
• Description: Planar semiconductor device covered with a protective film of amorphous or polycrystalline silicon carbide containing H, N, O or a halogen, formed by plasma CVD or reduced‑pressure CVD; an optional additional insulating layer (Al₂O₃, Si₃N₄, Nb₂O₃, HfO₂, Ta₂O₃ or low‑melting glass) increases voltage withstand. The patent expressly discusses ion‑diffusion blocking and external‑field shielding for high‑voltage devices.
• § 102 relevance: Most relevant of the materials references to the purpose of claim 1 (blocking contaminating‑ion diffusion in a semiconductor protective film). It uses silicon carbide rather than the claimed SiO₂/plasma‑nitride stack and is not a printhead; no anticipation.

11. JP 61‑291149 A — Katano (Ricoh)

• Full citation: JP 61‑291149 A, "Antistatic treatment of ink jet head," Ricoh Co. Ltd. Published (laid open) 1986‑12‑20; priority 1985‑06‑19.
• Description: Applying a fluorocarbon water repellent to the nozzle face and a surfactant anti‑static surface to reduce dust adhesion and droplet misdirection.
• § 102 relevance: Least relevant of the cited references. It concerns the outer nozzle face, not the electrical circuitry or its passivation, and does not anticipate any claim.

Overall § 102 conclusion (and the honest caveat)

I could not, from the record before me, identify any one of the 11 examiner‑cited references that discloses every element of claim 1 arranged as claimed. Claim 1 requires the combination of (i) MOS driver circuitry monolithically integrated within the printhead, (ii) a first doped/undoped‑SiO₂ layer of 200 Å–2 µm directly over that circuitry and over the heater protective layer, (iii) a plasma‑nitride layer of 1000 Å–3 µm over the oxide, and (iv) a dry‑etch‑nitride‑then‑wet‑etch‑oxide removal sequence that clears the contact pads and heater protective layer without attack. No cited reference teaches all of these elements, so no reference is a clean § 102 anticipation of claim 1 (nor, a fortiori, of dependent claims 2–6, each of which incorporates all of claim 1).

Where the references actually bite is under § 103 and as support for specific dependent limitations:

• Closest single reference / primary § 103 reference: US 4,719,477 (Hewlett‑Packard) — monolithic MOSFET drivers on the printhead substrate plus a patterned passivation layer over the metallization.
• Secondary combination references for the ionic‑passivation stack: US 4,686,559 (nitride+oxide IC sealing/patterning to expose pads) and US 4,647,472 (protective film to block ion diffusion in a high‑voltage semiconductor).
• References supporting the nitride‑deposition process limitations: US 4,298,629 and US 4,699,825.
• Base thermal‑ink‑jet environment (channels/nozzles/reservoir/heater/protective layer): US 4,463,359 and US Re. 32,572.
• References supporting the pit / thick‑film flow‑passage limitations of claims 2, 4, 5, 6: US 4,638,337, US 4,774,530, and JP 61‑135755.
• Least probative: JP 61‑291149 (nozzle‑face antistatic treatment).

If you want, I can produce a formal claim‑chart mapping each element of claims 1–6 against each of these references, or pull the full text of the two most relevant references (US 4,719,477 and US 4,686,559) to build the § 103 combination in detail. Note also that two related Xerox applications are referenced in the '355 specification but are not among the examiner citations — Ser. No. 354,941 (Hawkins et al.) and Ser. No. 336,624 (which issued as US 4,947,192), the latter being the source of the FIG. 4 MOS transistor switch.

Sources: https://patents.google.com/patent/US5010355/en ; https://patents.google.com/patent/US4719477 ; https://patents.google.com/patent/[US4463359A](/patent/US4463359A)/en ; https://patents.google.com/patent/US4647472 ; https://uspto.report/patent/grant/[5,010,355](/patent/5010355)

I'll verify a few of the cited references before building the § 103 analysis.

Obviousness Analysis — U.S. Patent 5,010,355

Patent: US 5,010,355 A, "Ink jet printhead having ionic passivation of electrical circuitry"
App. No.: US 07/456,431 | Filed / Priority: 1989‑12‑26 | Granted: 1991‑04‑23
Original assignee: Xerox Corp. (later [[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.) Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%20Ltd.); page also shows a DE family member titled "Color jet print head with ionic passivation of the electrical circuits" — reproduced literally, as the record states it)
Inventors: Hawkins, Burke, Roll, Hartman, Atkinson
Governing law: Because the application was filed before 16 March 2013, pre‑AIA 35 U.S.C. § 103(a) applies; the Graham v. John Deere framework (scope/content of prior art, differences, PHOSITA level, secondary considerations) controls, as do the KSR v. Teleflex rationales.

1. The hypothetical person having ordinary skill in the art (PHOSITA)

For this record a PHOSITA is a worker with a B.S. in electrical engineering, materials science or mechanical engineering and roughly 3–5 years of experience in either (a) thin‑film silicon thermal ink jet printhead fabrication, or (b) silicon integrated‑circuit passivation and metallization. Critically, this is a predictable-arts field: by 1989 both thermal ink jet printheads and MOS passivation were mature, heavily documented engineering disciplines, and the two had already been merged (see § 2 below).

2. The prior art of record and what each reference actually teaches

The eleven references cited on the face of the patent, with the specific teachings that matter here:

Two further items appear on the same page and are relevant: the specification's own reliance on copending application Ser. No. 336,624 (Hawkins et al., "Monolithic Silicon Integrated Circuit Chip for a Thermal Ink Jet Printer"), which matured into US 4,947,192 (listed under "Similar Documents"), and US 4,899,181 (Drake & Hawkins, "Large monolithic thermal ink jet printhead," filed 1989‑01‑30, listed under "Similar Documents," not in the USPTO citation list on this page). US 4,899,181 contains the explicit statement that the printhead's passivation film provides an "ion barrier," that "[o]ther ion barriers may be used, such as, for example, polyimide, plasma nitride, as well as the above‑mentioned phosphorous doped silicon dioxide, or any combinations thereof," and that "[a]n effective ion barrier layer is achieved when its thickness is between 1000 angstrom and 10 micrometers." (uspto.report) I flag that this reference is not among the eleven citations on the '355 face — it comes from the "Similar Documents"/related‑work portion of the page — but it is squarely material.

Denouement: with one exception, every element of claim 1 appears, verbatim or in substance, in the cited art. The only true "missing piece" of any single reference is the specific stacked combination and its etch sequence; and that is exactly where the KSR/MPEP 2143 rationales bite hardest.

3. Claim 1 — element-by-element mapping

There is no anticipation — no single reference shows the full stack plus the ordered etch. But claim 1 is, in my assessment, highly vulnerable under § 103.

4. Grounds of rejection

Ground 1 (principal) — Claim 1 obvious over Hess '477 in view of Re. 32,572 and Haskell '559, optionally with Nozaki '8629 / Hiraki '472

Why Hess '477 as primary: it supplies the entire preamble — a thermal ink jet printhead whose bubble-generating resistors and MOSFET drive circuitry are monolithic on the same substrate. That reference also motivates why on‑chip drivers exist: lead‑count reduction for high‑resolution arrays, the same rationale the '355 Background recites almost verbatim. Once the MOS drivers sit on the heater plate, they sit under the ink, and the passivation problem is created.

Why Re. 32,572: the same page (matching filing date 1985‑04‑03) renders obvious:

• a doped (phosphorus) silicon dioxide passivation layer on the order of 2 µm laid over both the heating elements and the addressing electrodes — squarely within claim 1's "200 Å to 2 µm … doped or undoped silicon dioxide directly over the MOS electronic circuitry and heating elements with protective layer";
• etching that layer off the electrode terminals, with the express alternatives of wet or dry etching;
• the alternative of plasma‑deposited Si₃N₄ for the same electrode passivation.

Why Haskell '559: it teaches the multi‑layer idea — a nitride seal (2000–6000 Å, overlapping the claimed 1000 Å–3 µm range) plus an oxide‑family protective layer over it — deposited by plasma at ~300 °C and never above 450 °C, and then patterned to open the contact areas through the composite. That is claim 1's two‑layer stack plus the contact‑opening etch, in the same technical context (protecting a completed metallized IC from a hostile environment).

Motivation to combine (MPEP 2143 / KSR):

1. Known technique, same problem. Both Re. 32,572 and Haskell address the identical problem — an aqueous, contaminant‑laden environment attacking aluminum metallization and active devices — and both teach the same solution class (inorganic thin‑film encapsulation).
2. Recognized need / art‑recognized problem. The '355 Background itself concedes the industry knew that (i) ink contains mobile ions as part of the dye species, (ii) MOS threshold voltage shifts under ion drift, and (iii) printhead temperatures rise to ~60 °C, accelerating drift. That is an admission of the problem and its source.
3. Design incentive from the reference itself. Haskell supplies the temperature ceiling rationale that dovetails with the '355's own statement that heater‑passivation thermal budgets are incompatible with aluminum metallization — which selects plasma nitride (Haskell, Hiraki, Nozaki) over the 650–1000 °C LPCVD nitride of Sakai '9825.
4. Combination of known elements with predictable results. Depositing a dielectric on a completed aluminum IC and photo‑opening the pads was routine; stacking a nitride ion barrier on an oxide adhesion/undercut layer was routine (Haskell claims 5 and 7; Hiraki's second insulating layer).

Anticipated rebuttal and my response: applicant will seize on Haskell's teaching that the oxide should be eliminated between the metal and the nitride (to avoid a lateral moisture path). That is a narrow, context‑bound criticism of the hermetic‑seal geometry at a contact opening, not a teaching away from an oxide‑under‑nitride dielectric stack generally; and it cuts the other way, because the '355's own etch sequence (dry nitride, then wet oxide) is what makes the direct‑to‑metal nitride seal unnecessary. Moreover, the reference literature overwhelmingly treats PSG‑then‑plasma‑nitride as the standard stack, and Re. 32,572 independently places doped SiO₂ directly on heaters and electrodes.

Ground 2 — Claim 1 obvious over Hawkins '530 in view of Hess '477 and Haskell '559 (or Hiraki '472)

Hawkins '530 already combines (i) a two‑part printhead, (ii) MOSFET‑capable active circuitry on the heater plate, (iii) a thick‑film passivation layer over that circuitry, and (iv) photopatterning of that layer over heaters and terminals. Substituting or supplementing the thick film with the thin‑film inorganic oxide/nitride stack of Haskell '559 for mobile‑ion resistance is a simple substitution of one known encapsulant for another, with predictable results (MPEP 2143(A)/(B)). Hiraki '472 supplies the plasma‑CVD, multi‑layer (protective film + additional insulating layer) architecture for a semiconductor device.

Ground 3 — Claim 1 obvious over Hess '477 + Hiraki '472 + Watanabe JPS 61‑135755 + Re. 32,572

The all‑foreign‑flavor variant: Watanabe teaches SiO₂ over heaters and electrodes in a liquid jet head built with a photopatterned resin flow‑passage layer; Hiraki teaches multi‑layer plasma‑deposited protective films; Re. 32,572 supplies the Ta cavitation layer and the plasma‑nitride passivation alternative; Hess supplies the monolithic MOS drivers. The motivation is the same as Ground 1: protecting the driving devices from the ink.

5. Dependent claims

Claim 2 — "thick film layer ≥ 8 µm on the nitride, patterned for heater pits and an ink flow passage"

Obvious over Grounds 1–3 in view of Hawkins '530 and/or Torpey '337.

• Hawkins '530: thick film organic structure deposited over the passivated heater plate; patterned to put each heater in a pit 26 and to form the recess 38 passage from manifold to channels; the layer is disclosed at 10–50 µm (20–40 µm preferred) — inherently ≥8 µm.
• Torpey '337: identical pit‑forming/bubble‑containment function with Riston®.
• Watanabe JPS 61‑135755: photosensitive resin layer photopatterned to define the passage walls.
  The claimed 8 µm floor is an arbitrary lower bound on an otherwise disclosed range with no demonstrated criticality — obvious under In re Aller / In re Woodruff and MPEP 2144.05. Any asserted "8 µm enables a photopatterned pit" advantage is a result‑effective optimization of a parameter the art already used for exactly that purpose.

Claim 3 — third layer of polyimide ≥1.5 µm etched from heaters and pads

Obvious over Grounds 1–3 in view of Hiraki '472 and/or Haskell '559.

• Hiraki '472: "additional insulating layer over the protective film" for improved withstand.
• Haskell '559: the nitride seal is covered by a further protective layer (silicon oxynitride/oxide/aluminum oxide) applied without intervening masking — establishing the general practice of capping the nitride barrier.
• US 4,899,181 (same page, "Similar Documents") lists polyimide and plasma nitride together as printhead ion barriers, "or any combinations thereof," with a broad 1000 Å–10 µm barrier thickness range — an express suggestion to combine.
  The stated advantages — additional ionic resistance, lower electric fields in a thick dielectric, and "excellent adhesion to plasma nitride" — are the ordinary, expected properties of polyimide and are exactly the kind of "predictable use of prior art elements according to their established functions" that KSR condemns.

Claim 4 — polyimide ≥8 µm so that it also provides the heater pit and the flow passage

Obvious over the claim‑3 combination in view of Hawkins '530. Hawkins '530 already teaches a single thick‑film layer that simultaneously (i) passivates the active circuitry and (ii) is photopatterned to provide the pit and the manifold‑to‑channel passage. Merging that dual function into the polyimide top layer is the duplication/relocation of a known function with predictable results. Again the 8 µm threshold is a range optimization.

Claim 5 — photopatternable thick film layer ≥8 µm over the polyimide third layer

Obvious for the same reasons as claim 2, applied to the three‑layer stack — a straightforward multiplication of a known layer for its known purpose.

Claim 6 — two polyimide layers: first (≥1.5 µm) intact, second (≥8 µm) patterned for pits/passage

The most specific claim, but still vulnerable. It is simply the combination of claims 3 and 4 executed as two discrete coats, and the stated advantage (retaining an intact barrier under the patterned layer so "maximum ionic passivation" is preserved) is the predictable consequence of not etching through a barrier layer. The use of multiple sequentially deposited and separately patterned thick‑film/polyimide layers in a printhead was squarely within the skill level — Hawkins '530 and Torpey '337 establish single‑layer practice, and the number of barrier layers was a known design variable. This is an "obvious to try" / "change in number of parts" situation under KSR and MPEP 2143(D).

6. Secondary considerations

None of the classic objective indicia appear on the face of the record:

• No unexpected results are demonstrated — the patent asserts more of the same (longer operating lifetime), not a new property.
• No teaching‑away is established by applicant; Haskell's oxide‑elimination teaching is context‑specific and does not disparage the claimed stack in the ink jet environment.
• Long‑felt need / commercial success: the '355 Background recites the need for longer printhead life and lower cost per page, but the record shows the solution was being pursued in parallel across the industry (Xerox's own Re. 32,572, '530 and US 4,899,181; HP's '477) — the "need" was being met by obvious routes, which weakens any nexus argument. No evidence of record links any commercial success to claims 1–6 as opposed to the printer/printhead generally.

§ 103(c) note: copending Ser. No. 354,941 and Ser. No. 336,624 (→ US 4,947,192) are commonly owned by Xerox. To the extent either qualifies only as § 102(e)/(f)/(g) art, pre‑AIA § 103(c)(1) would disqualify it as prior art for obviousness. They are therefore not proper § 103 combination references, although they corroborate the state of the art.

7. Bottom line

• Claim 1 is the strongest claim, but it is still, in my assessment, obvious. Its novelty rests on the ordered pair of dielectric layers and the two‑stage etch, and both the layers (Re. 32,572's 2 µm PSG passivation; Haskell '559's 2000–6000 Å plasma nitride plus oxide) and the etch (Re. 32,572's wet‑or‑dry removal of passivation from the terminals; Haskell's opening of contacts through a nitride/oxide composite) are separately disclosed. The articulated motivation is strong: mobile ions in the ink plus ~60 °C operating temperature plus 30–50 V fields, all expressly recognized in the art, with Haskell supplying the aluminum‑compatible ≤450 °C plasma deposition constraint.
• Claims 2, 4 and 5 are the weakest, because Hawkins '530 teaches a single thick film doing double duty (circuitry passivation + photopatterned pits + ink passage), and the "≥8 µm" limits are unexplained range selections.
• Claim 3 is moderately weak given the explicit "polyimide, plasma nitride, PSG or any combinations thereof" ion‑barrier teaching in the same corporate family of art.
• Claim 6 is the most defensible only in the sense that no single reference shows two discrete polyimide layers on the heater plate; but it is still an obvious two‑coat implementation of claims 3+4 with predictable benefit, so I would expect it to fall as well.
• Overall: I would rate the § 103 exposure as high for claims 1, 2, 4 and 5, moderate‑to‑high for claim 3, and moderate for claim 6, if the examiner combines Hess '477 + Re. 32,572 + Haskell '559 (+ Hawkins '530, + Nozaki '8629/Hiraki '472). A defensible narrow position for the patentee exists only if it argues the specific dry‑nitride‑then‑wet‑oxide sequence protecting the Ta cavitation layer produces an unexpected lifetime result — and the specification's own statement that "roughening the Ta surface leads to shortened heating element lifetime" would need corroborating data, which does not appear on this record.

Sources

• US 5,010,355 (subject patent): https://patents.google.com/patent/US5010355/en
• US 4,719,477 (Hess, HP): https://patents.google.com/patent/US4719477 and https://patents.google.com/patent/US5122812
• US 4,686,559 (Haskell, AMD): https://www.freepatentsonline.com/[4686559](/patent/4686559).html and https://patents.google.com/patent/US4686559
• JPS 61‑135755 (Watanabe, Canon): https://patents.google.com/patent/JPS61135755A/en
• US 4,774,530 (Hawkins, Xerox): https://patents.google.com/patent/US4774530 and http://patentimages.storage.googleapis.com/pdfs/US4774530.pdf
• Re. 32,572 pre‑reissue disclosure (Hawkins et al., filed 1985‑04‑03): https://uspto.report/patent/grant/[4,601,777](/patent/4601777)
• US 4,899,181 (Drake & Hawkins, filed 1989‑01‑30; "Similar Documents" section): https://uspto.report/patent/grant/[4,899,181](/patent/4899181)

Caveats: (1) the Re. 32,572 ↔ US 4,601,777 correspondence is inferred from identical filing date and text, not from an express reissue statement on the page; (2) US 4,899,181 and US 4,835,553 are not among the eleven references cited on the '355 face — they come from the related‑work portion of the page and are used here only as corroboration; (3) all stated statutory conclusions are analyst opinions, not USPTO or court determinations.