Invalidity dossier

US 4586168

Added 9/21/2026, 10:43:15 AM

At a glanceNo PTAB challengesNo litigation on file

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Patent summary

Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.

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Patent Overview — US 4,586,168

Title: Dual port memory sense amplifier isolation

Patent number: US 4,586,168 A

Application number: US06/560,628

Inventors: Richard H. Adlhoch; James Ward

Original assignee: Motorola, Inc. (current assignee listed as Motorola Solutions Inc)

Priority/filing date: 1983-12-12

Publication (grant) date: 1986-04-29

Legal status listed: Expired – Fee Related; anticipated expiration 2003-12-12

Purpose: The patent addresses dual port memory, in which a standard memory cell has multiplexed I/O so two different data processors can use the same memory. Typically such memory requires separate read and write cycles for each processor, preventing a read by one processor and a write by another during a single read cycle. An object is to permit almost simultaneous read and write of a memory storage cell.

Plain-language scope: A memory has a storage cell accessible by two data processors. The storage cell is controllably coupled to column lines, which are controllably coupled to a sense amplifier. Once data is latched in the sense amplifier, the column lines are disconnected from the sense amplifier, so a separate write circuit can write new data into the storage cell without interference from the latched sense amplifier. This is accomplished by shortening the column drive signal (the column select signal) to terminate the connection after the sense amplifier latches the read data, allowing write circuitry to be enabled during the same read cycle. In the described embodiment, a second write circuit is added and timing of the column select signal is modified; the shortened column drive signal must still be long enough for the sense amplifier to latch under worst-case conditions. The description notes it was simpler to shorten the column drive signal than the row drive signal, and the column line responds faster due to less capacitive loading.

Source: https://patents.google.com/patent/US4586168/en

What the excerpt does not establish: It does not provide the full text (the description is explicitly marked as excerpted), the complete claims, or all drawing details. It does not establish validity, enforceability, litigation history, ownership transfers beyond the listed assignee data, or prior-art analysis.

Generated 10/1/2026, 10:01:10 PM

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Litigation summary

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Proceedings on file (0)

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PTAB challenges

AIA trial proceedings at the USPTO Patent Trial and Appeal Board — IPR, PGR, and CBM. Petitioners, judge panels, claim-level invalidation outcomes from Final Written Decisions, and Federal Circuit appeals. The single most important defensive datapoint after litigation history.

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Assignment history

Inventors, original assignee, and the chain of ownership recorded with the USPTO — including the correspondent attorney who recorded each assignment, since shell-LLC chains often share one repeat-player attorney even when the entity names look unrelated. Surfaces NPE / patent-troll patterns: shell-entity transfers, known asserters in the chain, repeat correspondent fingerprints, pre-litigation assignments, and bankruptcy fire-sales.

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Prior art

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Obviousness

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Extensions

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Derivative works

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