US 4353060

I'll search for litigation/docket activity and corroborating records for this patent number.

Search results — US 4,353,060

Litigation / CAFC docket check: I ran targeted searches for 4353060 in connection with CAFC 2026 dockets and infringement litigation. No CAFC 2026 docket, PTAB proceeding, or district-court case was found naming US 4,353,060. This is consistent with the record: the patent is marked "Expired – Lifetime" with an anticipated expiration of 2000-07-01, so an active 2026 appeal involving this patent is very unlikely. I want to be explicit: absence of search hits is not proof of absence of a docket, and I cannot query PACER/CAFC docket systems directly — treat this as "no evidence located," not "confirmed none."

Caution on the identifier: A literal search for "4353060" also surfaces JP 4353060 B2 (Japanese Patent No. 4353060, Sumitomo Metal Industries / Ishikawa Gasket, issued 2009-10-28, "Stainless steel for gaskets" — a metallurgy patent). That is a different document entirely and is not to be conflated with US 4,353,060. Below I report only the US patent.

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Bibliographic data (from the authoritative full text)

Note on assignee: the record literally shows two names — "Tokyo Shibaura Electric Co Ltd" (original) and "TOYO SHIBAURA DENKI KABUSHIKI KAISHA" (reassignment). I am reporting both as recorded and flagging that the second appears to be a variant rendering of the same Toshiba entity rather than asserting that as fact.

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Abstract (as issued)

"The sum of an analog input signal and a positive feedback signal is applied to an A/D converter. A D/A converter device including a D/A converter and a delay device for delaying an analog feedback signal which is a signal formed by D/A converting the output of the A/D converter by one conversion operation period of the A/D converter. The positive feedback signal is formed by multiplying the analog feedback signal by a given feedback coefficient."

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Plain-language overview of the independent claims (1, 5, 7)

Claim 1 — the base "output stabilizing circuit" concept.
An A/D converter system built around a positive feedback loop:

• An adder sums the analog input with a positive feedback signal.
• An A/D converter digitizes the adder output.
• A D/A converter means (expressly including a D/A converter and a signal delay means) produces an analog feedback signal derived from the A/D output after at least one conversion period.
• A feedback coefficient multiplier (coefficient < 1) scales that analog feedback signal to form the positive feedback.
• An input coefficient multiplier scales the first analog input by an input coefficient to produce the signal fed to the adder.
• Key limitation: the input coefficient plus the feedback coefficient must sum to 1.

Practical effect (per the specification): this creates a hysteresis/dead zone so the LSB does not toggle when the input merely jitters around a threshold — suppressing granular noise and instability.

Claim 5 — the "inverse-filter" / response-corrected version (FIG. 13 embodiment).
Same stabilized loop, but with the coefficients hard-set to 0.5 and an added output-correction path:

• First adder (input + positive feedback) → A/D converter.
• Delay means delays the A/D output by one sampling period.
• D/A converter converts the delayed signal into the analog feedback.
• First coefficient multiplier × 0.5 forms the positive feedback.
• Second coefficient multiplier × 0.5 multiplies the delayed A/D output.
• Second adder sums the A/D output with the second multiplier's output to produce the system output.

Practical effect: this implements the inverse transfer function G(z) = (1 − 0.5Z⁻¹)/0.5 cascaded with the forward filter H(z) = 0.5/(1 − 0.5Z⁻¹), so H·G = 1 — improving the slow response to step inputs and the waveform distortion of the FIG. 3 design.

Claim 7 — the compensated version (FIG. 18A/19 embodiment).
Everything in claim 5, plus:

• A compensating circuit and a third adder that adds the compensation signal to the second adder's output.
• The compensating circuit comprises:
  • (i) a comparator taking the A/D output as a first input and the delay means output as a second input, producing POSITIVE (first > second), NEGATIVE (first < second), or ZERO (equal); and
  • (ii) a logic circuit with a flag register temporarily storing the POSITIVE or NEGATIVE state, which outputs "0" when POSITIVE, "1" when NEGATIVE, "1" when ZERO and the flag holds POSITIVE, and "0" when ZERO and the flag holds NEGATIVE — this signal is the addition input to the third adder.

Practical effect: injects a one-quantizing-step offset to cure the ±1 LSB fluctuation that remains in the claim-5 output (the Y₂ wobble described at command pulses 5, 6, 24, 25 in FIGS. 17A/17B), markedly reducing distortion.

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Dependent claims (context for the independents)

• Claim 2 — the delay means delays the A/D converter's output before the D/A converter (digital-side delay / latch).
• Claim 3 — the delay means delays the signal after D/A conversion (analog-side delay).
• Claim 4 — adds a multiplexer (selecting among plural analog inputs), an addressable memory storing the A/D output per channel and feeding the D/A converter after one conversion operation, and a timing control circuit interlocking mux and memory (time-division multi-channel conversion — FIG. 8).
• Claim 6 — adds a third coefficient multiplier applying an input coefficient of 0.5 to the first analog input.
• Claim 8 — details the logic: POSITIVE → set terminal, NEGATIVE → reset terminal of the flag register; AND gate receiving the flag output and the ZERO signal; OR gate receiving the AND output and the NEGATIVE signal, driving the third adder.

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Uncertainty flags

• CAFC 2026 docket: none located; the patent expired 2000-07-01, making 2026 appellate activity improbable. I cannot fully rule out an unindexed docket.
• Assignee naming: two distinct renderings appear in the record (Tokyo Shibaura Electric Co Ltd / TOYO SHIBAURA DENKI KABUSHIKI KAISHA). I have preserved both verbatim rather than normalizing.
• All technical/bibliographic content above is taken from the authoritative full patent text supplied for US 4,353,060; the web searches returned no conflicting ground truth for this specific number.

I'll search for litigation involving US patent 4353060.

Let me run more targeted searches.

Let me try a few more targeted searches on litigation databases.

Litigation Search: US Patent No. 4,353,060

Conclusion: I found no litigation — district court, CAFC, ITC, or PTAB — involving U.S. Patent No. 4,353,060.

What I searched and what came back

I ran targeted queries designed to surface litigation records (Unified Patents portal results, CourtListener/RECAP dockets, PTAB papers, and general "patent + lawsuit" queries for the literal number). None returned an assertion, complaint, IPR/PGR, or appeal naming US 4,353,060.

Critically, several results contained false-positive number matches that must not be conflated with this patent:

Relevant context on the patent itself

• Patent: US 4,353,060 — "Analog to digital converter system with an output stabilizing circuit"
• Inventors: Kenjiro Endoh, Yoshiyuki Ishizawa, Masanori Tanaka, Koji Iwasaki
• Original assignee: Tokyo Shibaura Electric Co., Ltd. (Toshiba); later recorded assignment to Toyo Shibaura Denki Kabushiki Kaisha (1982-07-20)
• Priority: 1979-07-13 (JP 54-88769); Filed: 1980-07-01; Granted: 1982-10-05
• Legal status (per Google Patents): Expired – Lifetime, with anticipated expiration 2000-07-01 (i.e., the 17-year term from the 1980 filing date under pre-URAA rules)
• Family: DE 3026230 A1/C2, GB 2060293 A/B, JP S5613830A / JPS5952576B2 — no family member shows an assertion in the records surfaced.

Caveats on confidence

• The patent's enforceable term ended ~2000, so any infringement action would have had to be filed in roughly 1982–2000. Older district court dockets (especially pre-PACER, pre-1990s) are not fully digitized or free-searchable, so I cannot rule out with certainty that an early-1980s/1990s suit existed and simply is not in the online corpora I can reach.
• I did not obtain a direct hit from the Unified Patents litigation caselist or from PACER itself for this number; the searches returned aggregator/PDF content rather than a docket entry for US 4,353,060.
• Within the limits of available records, the correct answer is: no known litigation.

Bottom line

No litigation is known involving US Patent No. 4,353,060. It appears to have lived out its term as an expired Toshiba (Tokyo Shibaura) analog-to-digital converter patent without any recorded enforcement action. If you need a definitive negative, the next step would be a paid docket search (LexisNexis/Docket Navigator) and a manual PACER/ITC sweep for the 1982–2000 window, since those older records are not reliably captured in free search.

I'll verify the structured "no proceedings" record against public sources before writing anything up.

PTAB Proceedings Report — U.S. Patent No. 4,353,060

"Analog to digital converter system with an output stabilizing circuit"
Patent Owner / original assignee: Tokyo Shibaura Electric Co., Ltd. (now Toshiba Corp.) · Inventors: Endoh, Ishizawa, Tanaka, Iwasaki
Priority: 1979-07-13 · Filed: 1980-07-01 · Granted: 1982-10-05 · Expired: 2000-07-01 (recorded as "Expired – Lifetime," anticipated expiration)

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Proceedings overview

Total AIA trial proceedings on file: 0. Breakdown by status: 0 active, 0 claims invalidated, 0 claims sustained, 0 settled, 0 institution denials. The USPTO Open Data Portal structured record for US4353060 returns no AIA trial proceedings, and web searching surfaced no IPR, PGR, or CBM involving this patent (and no Federal Circuit appeal of any PTAB decision on it). The bottom-line defensive posture is therefore neither "hardened by surviving IPRs" nor "claims canceled" — it is "the patent term ran out." US4353060 expired on 2000-07-01, more than a decade before the first IPR was filed at the PTAB (the AIA trial regime opened 2012-09-16). Any demand letter that cites US4353060 against current conduct is citing a patent that has been dead for over 25 years; the correct defense is the expiration date and 35 U.S.C. § 286's six-year damages lookback, not IPR estoppel. If the letter quotes canceled claims or a PTAB outcome, that representation is false.

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Per-proceeding detail

No proceedings exist to report. Rather than fabricate entries, here is why each AIA vehicle is unavailable or was never used:

(none) — IPR

• Type: Inter Partes Review (35 U.S.C. §§ 311–319)
• Availability analysis: IPR is legally available against an expired patent, but only prospectively from 2012-09-16. No petition was ever filed against US4353060. Practical disincentives are decisive: no pre-suit notice or service of an infringement complaint exists for this patent that would define the § 315(b) one-year window, and an IPR of an expired patent yields no injunction-avoidance or ongoing-royalty benefit.
• Institution decision: N/A
• Final Written Decision: N/A
• Appeal: N/A
• Defensive value: None needed — you do not have to invalidate a patent that expired on 2000-07-01.

(none) — PGR

• Type: Post-Grant Review (35 U.S.C. §§ 321–329)
• Availability analysis: PGR applies only to patents with an effective filing date on or after 2013-03-16. US4353060's effective filing date is 1980-07-01 (priority 1979-07-13). Statutorily ineligible. Do not accept any assertion that a PGR exists on this patent.
• Defensive value: N/A.

(none) — CBM

• Type: Covered Business Method Review (§ 18 of the AIA; sunset 2020-09-16)
• Availability analysis: CBM required a claim directed to a financial product or service (with the technological-invention exception). US4353060's claims 1–8 are directed to an analog feedback/adder circuit for stabilizing an A/D converter output — a converter technology, not a financial business method. Independently, the patent expired in 2000. Not CBM-eligible.
• Defensive value: N/A.

Related (non-PTAB) reference points you should have on the docket

• No FWD → no CAFC appeal. There is no PTAB Final Written Decision to appeal, so there is no Federal Circuit docket number to research. Queries to CourtListener and the Federal Circuit's docket should be expected to return nothing for this patent.
• No known district-court assertion. Targeted searches for litigation citing U.S. Patent 4,353,060 returned no case. I cannot rule out an old, unindexed 1980s–1990s suit with high confidence, but nothing public ties this patent to a case.
• Foreign family (parallel filings, not PTAB matters): JP 54-088769 → JPS5952576B2 (Japanese counterpart, "A/D converter stabilization circuit"); DE3026230A1 / DE3026230C2; GB2060293A / GB2060293B. These are the foreign counterparts of the same invention — not separate proceedings against the U.S. patent.
• Citation-of-record prior art (from the face of the patent, all pre-1980 U.S. patents): US2927962, US3745562, US3793513, US3872434, and US4107669 ("Apparatus for analog to digital conversion," Bell Telephone Laboratories). Foreign-family citation: DE2511594C3 (Siemens AG, "Arrangement for generating a hysteresis in the analog-digital conversion"). These are the references an examiner already considered — useful context, but irrelevant absent a live proceeding.
• Number-collision warning (practitioner trap): search engines surface unrelated documents at nearly identical numbers — JP4353060B2 is a 2009 Sumitomo Metal / Ishikawa Gasket stainless steel for gaskets patent, and EP4353060B1 is an unrelated European patent. Neither has anything to do with the Toshiba A/D converter patent. If a vendor or an AI summary hands you "PTAB activity on 4,353,060," verify it against the patent number and assignee before relying on it.

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Strategic summary

Claim status: UNTESTED (in the AIA sense) and EXPIRED (in fact). Claims 1–8 of US4353060 stand exactly as issued on 1982-10-05 — none was ever canceled by the PTAB, none was held unpatentable, and none was narrowed. That said, the distinction is academic for a modern defendant: the patent's term ended 2000-07-01, so claims 1–8 are unenforceable against any conduct on or after that date. Claim 1 (adder + A/D + D/A-with-delay + feedback-coefficient multiplier, with input coefficient α + feedback coefficient β = 1) and claims 5–8 (the 0.5/0.5 and output-compensation variants) are expired, not invalidated. The practical consequence is the same for infringement purposes, but a defense framed as "claims canceled" would be factually wrong and easily rebutted — frame it as expiration instead.

Estoppel landscape — none, and none needed. Because no petitioner ever filed an AIA trial, there is no § 325(e)(1) or § 315(e)(2) estoppel in either direction. Similarly, there is no IPR-driven narrowing to work around and no surviving-claim set to design around. Conversely, there is also no free ride from a prior petitioner's work product. Your path is statutory, not PTAB-based: (a) 35 U.S.C. § 154/URAA term computation — the recorded expiration of 2000-07-01 is the greater of the 17-years-from-issue date (1999-10-05) and the 20-years-from-filing date (2000-07-01) under the transitional URAA rule for patents in force on 1995-06-08; (b) § 286's six-year damages lookback, which as of today reaches back only to 2020-09-30 — two decades after the patent died; (c) § 271 requires an act of infringement during the term, and no such act can now occur. There is also no reexamination certificate or reissue visible in the record that could have extended or rewritten the claims.

Pattern signals — the null case. No repeat petitioners (there are no petitioners), no Patent Owner appeals (there is no FWD), no defensive aggregator involved (Unified Patents, RPX, and the like have no reason to spend on a patent that expired in 2000), and no litigation-driven IPR chain. The absence of PTAB activity here is not the "hardened patent" signal you'd see with a well-asserted modern patent — it is the signal of a 1980-vintage patent whose 20-year term simply closed before the AIA existed. For corroboration on the trial regime itself, see the USPTO's PTAB E2E / PTAB Decisions portal; a patent-number query there will return empty for this patent.

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Recommended next steps

• If you are a defendant and a demand letter cites US4353060: do not brief IPR. Lead with expiration. The patent's recorded term ended 2000-07-01 (Google Patents record; full text PDF at patentimages). Nobody can infringe an expired patent, and § 286 caps any recovery to acts within six years of filing suit — currently no earlier than 2020-09-30. If the letter asserts that a PTAB Final Written Decision canceled or sustained claims, quote the empty ODP proceeding record back and demand the proceeding number; there isn't one.
• If a counterparty or an AI tool tells you this patent was invalidated at the PTAB, or that JP4353060B2 / EP4353060B1 is a family member: correct it. JP4353060B2 is a Sumitomo Metal/Ishikawa Gasket stainless-steel patent; EP4353060B1 is unrelated. The real counterparts are JPS5952576B2, DE3026230, and GB2060293.
• If you were hoping for IPR estoppel leverage: there is none to inherit, and none is necessary. The only "proceeding" asset on this patent is its expiration date, and it is dispositive.
• Preserve the record: pull the Google Patents bibliographic page and the ODP "no proceedings" response into your file as the evidentiary basis for the expiration defense, in case an assertion persists.
• Caveat on completeness: my searches targeted PTAB/AIA trials, CAFC appeals, and litigation for US4353060 and returned nothing on point. I did not locate a pre-AIA district-court history for the patent, and cannot confirm with high confidence that none existed in the 1980s–1990s; if your matter turns on prior art decisions involving this patent, a LexisNexis/Westlaw "all courts" search by patent number is the appropriate next search, not the PTAB docket.

I'll search for assignment records and corroborating ownership data for this patent.

Let me probe for the assignment reel/frame and any correspondent-of-record data.

Ownership & Assignment Record — US 4,353,060

Source note / method. The authoritative full patent text supplied for US 4,353,060 includes the Google Patents Legal Events block, which mirrors the USPTO assignment index. That block records exactly one assignment event for this patent. I attempted to reach the USPTO Assignment Center / assignment.uspto.gov directly, but I could not extract the correspondent-of-record field or a second confirmation from the assignment index — the searches returned no hits for the reel/frame string 004014/0146 and no separate index page for this number. I therefore report the correspondent as not available in the records I can reach, rather than guessing it. Everything below is grounded in the supplied patent text plus the corroborating corporate-history searches noted inline.

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Inventors

• All four are named on the face of US 4,353,060 as inventors, and all four recur as assignors on the single recorded assignment (reel 004014/0146), executed 1980-06-16 to 1980-06-17 — i.e., roughly two weeks before the 1980-07-01 US filing date. That is the classic pre-filing employment "assignment of invention" signing, consistent with all four being Toshiba employees at the time of filing.
• Unusual patterns: none evident. There is no record in the available material of any inventor departing the original assignee within 12 months of filing, no inventor co-assignment to a third party, and no inventor-side retention of rights. The 1980-06 signing followed by a 1982 recording (delayed until grant) is normal prosecution-era practice, not a fire-sale precursor.
• The legal-event text names "ENDOH, KENJIRO; ISHIZAWA, YOSHIYUKI; TANAKA, MASANORI; AND OTHERS" — the "and others" is consistent with Iwasaki (and possibly a separate JP-side recording); the US patent names exactly four inventors.

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Original assignee

• As literally recorded on the issued patent: Tokyo Shibaura Electric Co Ltd (original assignee).
• As literally recorded on the 1982-07-20 assignment: "TOYO SHIBAURA DENKI KABUSHIKI KAISHA", address "72 HORIKAWA."
• Primary line of business: Toshiba was (and is) a diversified Japanese electronics/electrical manufacturer. Corroborating corporate-history sources confirm that Tokyo Shibaura Denki (Tokyo Shibaura Electric), formed 1939, was renamed Kabushiki Kaisha Toshiba / Toshiba Corporation in 1984 (Library of Congress name authority n 81128393; NDL authority 00263174, listing termination of the old name in 1984). The 72 Horikawa-cho, Saiwai-ku, Kawasaki address is the well-documented Toshiba headquarters address (it appears on numerous Toshiba EP filings surfaced in search, e.g. EP 0 501 338 and EP 0 399 812, both "Kabushiki Kaisha Toshiba, 72, Horikawa-cho, Saiwai-ku, Kawasaki-shi").
• Notation on the "TOYO" spelling (flag, consistent with the earlier sections): The record renders the 1982 assignee as "TOYO Shibaura Denki," whereas the operating company's documented name is TOKYO Shibaura Denki. Given the identical "72 Horikawa" address and the documented 1939–1984 corporate name, the "TOYO" form appears to be a recording/transcription variant of the same Toshiba entity. I preserve both renderings verbatim and do not assert they are two distinct parties.
• Did they ship a product embodying the claims? The specification itself describes a Toshiba application — a digital level adjuster in which the stabilized A/D output (8-bit control signal) drives a digital multiplier for a 12–16-bit coded audio signal (FIG. 10). Toshiba was a major producer of audio/consumer and industrial electronics in this era. I have not located a specific commercial part number tied to this patent, so I state only that the assignee is a large operating manufacturer and that the spec discloses a concrete product application — not that a specific shipping product is documented.
• Current status: Toshiba Corporation remains an operating company. (Publicly reported: Toshiba was taken private in 2023 by a consortium led by Japan Industrial Partners and delisted from the Tokyo Stock Exchange — general knowledge, moderate confidence; it does not affect this expired patent.)

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Assignment timeline

The Assignment Center index as reflected in the patent's Legal Events shows one recorded assignment (plus the grant event, which is not a conveyance):

• 1980-06-16 / 1980-06-17 (executed) / recorded 1982-07-20 — Reel 004014/0146

  • Conveyance: Assignment
  • Assignor: Endoh, Kenjiro; Ishizawa, Yoshiyuki; Tanaka, Masanori; and others
  • Assignee: "TOYO SHIBAURA DENKI KABUSHIKI KAISHA" (recorded literally; address 72 Horikawa) — i.e., the Tokyo Shibaura Denki / Toshiba entity, per the company history cited above
  • Correspondent: not available in the records I can reach (the Legal Events block does not expose the correspondent field, and I could not retrieve the Assignment Center entry directly). I will not invent a name here.
  • Context: inventor-to-employer assignment (initial vesting of title) executed just before the 1980-07-01 filing; recorded after grant. Not an acquisition, fire-sale, securitization, or transfer-to-asserter.

• Supplementary (non-conveyance) events in the same block: 1980-07-01 application filed (applicant Tokyo Shibaura Electric Co Ltd); 1982-10-05 patent granted. Neither is an assignment.

No post-issuance transfer is recorded. There is no company→LLC transfer, no security interest, no change-of-name recording, and no release in the available record. If there is any additional entry, it is not visible in the material I can reach — I say plainly that no post-1982 assignment of US 4,353,060 appears in the records consulted.

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Timeline diagram

timeline
    title Ownership of US 4353060
    1979 : JP priority application filed
    1980 : Inventors assign rights to Tokyo Shibaura
         : US application filed
    1982 : Assignment recorded reel 004014 0146
         : Patent issued to Tokyo Shibaura Electric
    1984 : Company renamed Toshiba Corporation
    2000 : Patent expired by term

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NPE / troll-pattern signals

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Verdict

Insufficient data — specifically, only the original assignment exists.

Justification: the sole recorded conveyance is reel 004014/0146, executed 1980-06-16/17 and recorded 1982-07-20, an inventor-to-employer assignment from Endoh, Ishizawa, Tanaka, and others to the Tokyo Shibaura Denki (Toshiba) operating entity. There is no post-issuance transfer, no LLC or NPE assignee, no known asserter, no litigation, and no evidence of any correspondent recurrence — so no NPE or troll-pattern signal is supported by evidence. The patent lived out its term with the original operating-company assignee (renamed Toshiba Corporation in 1984) and expired 2000-07-01.

Verification link: search the number at the USPTO Assignment Center — https://assignmentcenter.uspto.gov/ (and the mirrored index at https://assignment.uspto.gov/patent/index.html) — entering patent number 4353060, and confirm reel/frame 004014/0146.

Limitations. (a) I could not directly load the Assignment Center's per-record view, so the correspondent of record is unavailable and any additional micro-entries (e.g., a later change-of-name of the assignee to Toshiba) may exist but were not visible to me. (b) Pre-2000 USPTO assignment records are only partially digitized; a manual reel check could surface entries not in the electronic index. (c) The "TOYO" vs "TOKYO" Shibaura spelling is preserved as recorded and flagged, not resolved.

I'll research each cited prior-art reference for US 4,353,060 to build accurate citations and assess § 102 relevance.

Let me get details on the German family citation (the closest-subject-matter reference) and confirm the adversarial context.

Prior-Art Analysis — US 4,353,060 (literal identifier, not normalized)

Document under analysis (per authoritative full text): US 4,353,060 A — "Analog to digital converter system with an output stabilizing circuit"; App. No. US 06/165,037; filed 1980-07-01; granted 1982-10-05; priority JP 54-88769 (1979-07-13); original assignee Tokyo Shibaura Electric Co. Ltd. → recorded reassignment to TOYO SHIBAURA DENKI KABUSHIKI KAISHA.

Legal framework I'm applying. The application was filed 1980-07-01, so pre-AIA 35 U.S.C. §§ 102/103 apply. Because all five cited US references published more than one year before the US filing date, they are § 102(b) prior art (printed publications). Anticipation under § 102 requires a single reference disclosing every element of a claim as arranged; where a reference discloses only some elements, it is § 103 material. I flag both, since the record groups these as examiner citations rather than as anticipation rejections.

Scope note: the strict rule says interpret IDs literally — so I confirm this analysis is confined to US 4,353,060. It is not JP 4353060 B2 (Japan, 2009, gasket stainless steel), which the identifier search also surfaces and which is a wholly unrelated document (already flagged in the earlier sections).

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Summary table of cited references

Reference details verified against FreePatentsOnline (US 2,927,962), Google Patents (US 3,745,562; US 3,793,513; US 3,872,434; US 4,107,669), and the patentimages PDFs.

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1. US 2,927,962 — "Transmission systems employing quantization"

• Full citation: US 2,927,962 A, Bell Telephone Laboratories, Inc.; App. No. 425,485; filed 1954-04-26; patent granted 1960-03-08.
• Description: Foundational PCM error-compensation scheme. A sampler feeds an adder (23) that adds the quantizing error of the immediately preceding sample to the present sample before quantizer (24); the quantized output is locally decoded and subtracted to derive the error that is fed back. A "vernier"-type variant feeds a stabilizing-grid signal back to the coder's beam-deflecting elements.
• § 102 assessment: Not an anticipation of any claim. It discloses an adder-before-quantizer plus a feedback path, which touches the generic architecture of claim 1, but it feeds back a difference/error signal (net corrective, i.e., effectively negative feedback), not the **positive feedback of the output level scaled by β<1, and it has no α + β = 1 input-coefficient constraint. Best characterized as § 103 background art for claim 1's loop topology.

2. US 3,745,562 — "Digital transmission system with frequency weighted noise reduction"

• Full citation: US 3,745,562 A, Bell Telephone Laboratories, Inc. (inventor Rosenbaum); App. No. 214,051; filed 1971-12-30; granted 1973-07-10. (DE counterpart DE 2,263,757 A1/C2.)
• Description: Modifies a delta modulator to use present + future samples and past error terms. Delay lines (141–143) and multiplier circuits (144–149) with b-coefficients weight past errors; combining circuit generates first and second feedback signals applied to first and second summing means to alter the quantizer input; supports block encoding.
• § 102 assessment: Not a complete anticipation. It explicitly discloses the feedback coefficient multiplier + delay building blocks that appear in claim 1, and delay-before-quantization relevant to claim 2. However, the b-coefficients are chosen as Fourier coefficients of a noise-penalty function (frequency-weighting), not a single β<1 positive-feedback coefficient, and there is no α+β=1 constraint. Primary role: § 103 combinable art.

3. US 3,793,513 — "Circuits and methods for processing delta-modulated signals"

• Full citation: US 3,793,513 A, Nippon Electric Co. (inventor Kaneko); App. No. 253,592; filed 1972-05-15; granted 1974-02-19. (JP counterpart JPS5120148B1.)
• Description: Digital processing of one-bit delta-modulated codes without PCM conversion. Coefficient circuits 30/31/32 multiply codes by coefficients a, b, c; adder means 41 sums them; integrator 42 is an accumulator comprising adder 421, delay 422 of one clock period, and a feedback path; sign-bit extractor 43 acts as the polarity quantizer; output code W is multiplied by coefficient c and fed back to adder 41.
• § 102 assessment: Closest structural precursor to claims 1–2 among the US references. It discloses a quantizer with a feedback loop containing a one-clock-period delay (Z⁻¹) and a coefficient multiplier — mapping onto claim 1's D/A-converter + delay + coefficient-multiplier combination and to claim 2 (delay ahead of the reconstruction/integrator stage). But coefficient c is applied with a sign opposite the forward coefficients (delta-modulator negative feedback), so it does not disclose the positive (regenerative) feedback of the output level scaled by β<1, nor the α+β=1 relation. ⇒ § 103 art; possible § 102 support only for isolated limitations, not the claims as a whole.

4. US 3,872,434 — "Dynamic sample-by-sample automatic gain control"

• Full citation: US 3,872,434 A, Recognition Equipment Inc. (inventors Marion W. Neff, Dale R. Duvall, Paul D. Lawson); App. No. 421,814; filed 1973-12-05; granted 1975-03-18.
• Description: OCR/optical-reader AGC. A photocell array produces a multiplexed analog stream; a memory stores digital coded gain words per channel; a multibit D/A converter converts each word to an analog gain-control voltage in synchronism with multiplexing, applied to the A/D converter's reference. Uses a background monitor that counts output words per scan and adjusts the conversion scale.
• § 102 assessment: Most relevant to claim 4 (multiplexer selecting among plural analog signals + addressable memory storing per-channel digital values + timing/interlock of mux and memory). It is the only cited reference teaching a multiplexed multi-channel A/D with per-channel digital memory read timing. But the D/A output drives a reference/gain input, not an adder input combined with a positive feedback signal, and it lacks the α+β=1 stabilizing loop. ⇒ § 103 art for claim 4; not a standalone anticipation because claim 4 depends from claim 1.

5. US 4,107,669 — "Apparatus for analog to digital conversion"

• Full citation: US 4,107,669 A, Bell Telephone Laboratories, Incorporated; filed 1975-08-28; granted 1978-08-15.
• Description: Oversampled predictive/error-feedback coders. A quantizer (401/501/701) in the forward loop and a feedback loop containing a D/A converter and a serial chain of integrators (or feedback filter 702) whose summed output is subtracted from the input. Derives the noise-shaping result X(Z)=S(Z)+[1−H(Z)]·q(Z) and optimizes filter coefficients a_i to push quantizing noise out of band.
• § 102 assessment: Background architecture for claim 1. It is a genuine feedback-loop A/D converter with a filtering network (coefficient-set) in the feedback path and expressly gives the Z-transform treatment of noise shaping — the analytical machinery the '060 patent later applies (H(z)=0.5/(1−0.5Z⁻¹)). But the loop is subtractive (error feedback) and the coefficients minimize out-of-band noise, not a β<1 positive-feedback dead-zone. ⇒ § 103 art; not an anticipation.

6. DE 2,511,594 C3 (family citation — the most on-point reference)

• Full citation: DE 2,511,594 C3, Siemens AG (Berlin/München), "Anordnung zur Erzeugung einer Hysterese bei der Analog-Digital-Umsetzung" (Arrangement for generating a hysteresis in A/D conversion); priority/filed 1975-03-17; 1978-04-20.
• Description: As its title states, generates hysteresis in A/D conversion — i.e., a deliberate input dead-band around each threshold, which is exactly the stabilizing effect the '060 patent attributes to its positive-feedback loop (the spec computes a system dead-zone of (β/α)·ΔX, and ΔX dead-band even at the converter, illustrating the same object).
• § 102 assessment: Conceptually the closest reference to the claimed purpose and likely the most dangerous § 103 reference. Because it is the DE-family citation, I treat it as evidence of the general state of the art rather than a US face citation. Caveat: it appears in the "Family Cites Families" group, not the US "Citations (5)" examiner list, and I could not retrieve its full text within this session — so I cannot assert an element-by-element match. It should be prioritized for a full-text review because it targets the same hysteresis/dead-zone function as claim 1.

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Claim-mapping matrix (feature → reference)

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Bottom line

1. No single cited reference anticipates any claim of US 4,353,060 under § 102 in the strict all-elements sense. The five US references are best understood as § 102(b) prior art directed to individual limitations, functioning collectively as § 103 obviousness art (adder-before-quantizer feedback, delayed feedback with coefficient multipliers, and multiplexed multi-channel memory control).
2. The two references warranting the deepest scrutiny are:
   • US 3,793,513 — closest structural precursor: quantizer + one-clock delay + coefficient multiplier in the feedback path (touches claims 1–2).
   • DE 2,511,594 C3 (Siemens) — closest functional precursor: explicitly generates hysteresis in A/D conversion, matching the patent's stated object (claim 1). Its status here is a family citation and I could not verify its full text, so treat this as a lead, not a conclusion.
3. US 3,872,434 is the reference most directly implicated by claim 4 (multiplexed A/D with per-channel digital memory + timing control), even though it uses the D/A output for gain control rather than positive feedback.
4. Distinguishing feature of the '060 claims: the combination of a positive (regenerative) feedback loop with β<1 producing a deliberate threshold dead-zone, together with the α + β = 1 gain constraint. None of the cited US references discloses that combination — they feed back errors (subtractive) rather than stabilizing the output level with a sub-unity positive coefficient.

Caveats / confidence. (a) This is a citation-level analysis built on the patent's own characterizations plus retrieved abstracts/claims and PDFs; I did not perform a full element-by-element parse of every reference's complete specification, so the § 102 "no anticipation" conclusion is my best assessment, not a formal invalidity opinion. (b) DE 2,511,594 C3 details come from the patent record's family-citation listing; I could not open its full text here. (c) All ID interpretations are literal; no identifiers were auto-corrected.

I'll ground this obviousness analysis by pulling details on the cited prior-art references.

Obviousness Analysis — US 4,353,060 under 35 U.S.C. § 103

0. Method and evidentiary caveat (read this first)

The instruction is to "use the results from the Prior Art section of this page." That section is limited to the record Google Patents exposes:

• Cited by the examiner (5 US references): US 2,927,962 (Bell Telephone, 1960); US 3,743,562 (Bell Telephone, 1973); US 3,793,513 (Nippon Electric, 1974); US 3,872,434 (Recognition Equipment, 1975); US 4,107,669 (Bell Telephone Labs, 1978).
• Family-cited (1 foreign reference): DE 2,511,594 C3 (Siemens, priority 1975-03-17, published 1978-04-20) — "Arrangement for generating a hysteresis in the analog-digital conversion."

Critical limitation on this analysis: I have the titles, dates and partial text of these references, not their full specifications. US 3,872,434 and US 4,107,669 returned usable abstract/description text in my searches; US 2,927,962, US 3,743,562 and US 3,793,513 did not, and DE 2,511,594 C3 returned nothing but its title. Any § 103 conclusion about what a reference discloses is therefore an inference from title/abstract, and must be re-verified against the actual documents before being relied on. I flag this explicitly rather than overstate confidence.

One more structural caveat: this patent was examined in 1980–82, i.e., pre-KSR. The obviousness case below is built on both the pre-KSR "teaching, suggestion, motivation" framework and the post-KSR "predictable variation / known technique" framework, and I note where the two diverge.

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1. Level of ordinary skill in the art

A PHOSITA as of the 1979-07-13 priority date would be a graduate engineer with ~2–3 years in data-conversion design, familiar with: successive-approximation and flash A/D architectures; quantizer feedback loops (delta modulation, delta-sigma); the "hysteresis to suppress LSB chatter" problem in threshold comparators; and elementary Z-transform analysis of recursive (IIR) loops, including the idea that a feedback structure has a transfer function H(z) that can be compensated by an inverse filter. All of the techniques the patent uses — D/A-in-feedback, one-sample delay, sub-unity feedback coefficients, inverse filtering, hysteresis logic — are 1960s–70s building blocks (confirmed by the 1960 Bell, 1973 Bell, 1974 NEC and 1975 Siemens references).

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2. The decisive reference: DE 2,511,594 C3

This is the reference with the largest § 103 leverage, and it is also the one I can say least about with certainty.

• What its title asserts: an arrangement for generating a hysteresis in the analog-digital conversion. That is literally the stated object of US 4,353,060 (the "non-sensitive band of 0.5ΔX," col.-equivalent discussion in the spec).
• Why this matters: if DE 2,511,594 C3 discloses implementing A/D hysteresis by feeding a fraction of the D/A-converted digital output back to the input summing node, then claim 1 is at serious risk on that single reference, or at minimum on that reference in view of any delay-teaching secondary reference.
• Why it did not kill the patent: DE 2,511,594 C3 is cited in the family (almost certainly in the German prosecution of DE 3,026,230, which nonetheless granted and later issued as C2/C3). Two plausible readings: (a) the German examiner found it distinguishable because the Siemens arrangement lacked the α + β = 1 normalization and/or the explicit "delay of at least one converting operation period" recited in claim 1; or (b) it was overcome by amendment. I cannot resolve which without the documents.

Action item: pull DE 2,511,594 C3 (and its published drawing sheets) before finalizing any validity opinion. Everything downstream is contingent on it.

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3. What the confirmed references teach (from retrieved text)

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4. Claim-by-claim obviousness assessment

Claim 1 — the base loop

(adder + A/D + D/A converter means including a delay + feedback multiplier β<1 + input multiplier α, with α + β = 1)

Primary combination: DE 2,511,594 C3 in view of US 4,107,669, further in view of US 3,793,513 and US 3,743,562.

• Adder, A/D, D/A-in-feedback: US 4,107,669 (converter 402 feeding adding circuit 430 and differencing circuit 440).
• Delay of ≥1 conversion period: US 3,793,513 (delta-modulation feedback delay); also US 4,107,669's integrator chain.
• Sub-unity feedback coefficient: US 3,743,562 (weighted feedback) and US 4,107,669 (coefficients aᵢ).
• Input coefficient α with α + β = 1: this is the only element with a genuine mapping gap. But the patent's own specification concedes it is a gain-normalization design choice ("if α and β are so selected to have a relation α=1−β, the gain between the input and output of the A/D converter system may be made equal to that of the single A/D converter 13"), and it elsewhere states α "may take any value." A constraint that the applicant characterizes as an optional, result-effective scaling choice is, under KSR, exactly the kind of predictable variation a PHOSITA would adopt — particularly since US 4,107,669 already performs unity-gain / transfer-function normalization analysis.

Motivation: the art uniformly addresses quantization-noise and threshold-instability in coder feedback loops; the Siemens reference supplies the express purpose (hysteresis in A/D conversion), and Bell/NEC supply the architecture and the delay. Combining them yields claim 1.

Assessment: claim 1 is the most vulnerable claim — moderate-to-high obviousness risk, contingent entirely on what DE 2,511,594 C3 actually discloses.

Claims 2 and 3 — delay on the digital side vs. the analog side

Pure placement choices for the same delay element. US 3,872,434 delays in the digital domain (stored words → D/A), satisfying claim 2; US 4,107,669's D/A-then-integrator ordering supports the analog-side variant of claim 3. Choosing which side of the D/A converter to insert a required delay is a routine engineering option with no unexpected result.

Assessment: obvious. These claims add essentially nothing beyond claim 1.

Claim 4 — multiplexer + per-channel memory + timing control

This is the strongest documented obviousness finding in the set, because US 3,872,434 explicitly discloses every element: a multiplexed analog stream, a memory holding one digital word per channel addressed in synchronism with the multiplexer, a D/A converter, and timing logic. The patent's FIG. 8 embodiment (mux 17 → multiplier 11 → adder 12 → A/D 13 → memory 18 → D/A 15 → multiplier 16, interlocks via timing control 19) is a straightforward time-division adaptation of that teaching, and US 4,107,669 supplies the reason to place a D/A-plus-feedback loop around the shared converter.

Assessment: claim 4 obvious over US 3,872,434 in view of US 4,107,669. Note the irony: this is the claim whose features are best evidenced in the record, yet it depends from claim 1, so it survives or falls with claim 1's α + β = 1 limitation.

Claim 5 — the α = β = 0.5 inverse-filter (FIG. 13)

(A/D output → one-sample delay → D/A → ×0.5 feedback; separate ×0.5 of the delayed A/D output → second adder with the A/D output)

• The loop half is squarely disclosed by US 4,107,669 + US 3,793,513 (0.5 is one ordinary choice among the coefficients aᵢ of US 4,107,669; the patent's FIG. 6/7 data confirm 0.5 is not critical).
• The distinguishing half is the digital tap that reconstructs G(z) = (1 − 0.5Z⁻¹)/0.5 so that H(z)·G(z) = 1. None of the five cited US references, and (on its face) not DE 2,511,594 C3 either, discloses cascading an inverse digital filter with the feedback loop's forward response to cancel the hysteresis-induced response delay and waveform distortion.

The § 103 argument that a defendant/examiner would make: inverse filtering is a classical, well-known technique; US 4,107,669 performs exactly the Z-domain H(z) analysis that makes the required inverse apparent; and once you recognize that the positive-feedback quantizer imposes a known first-order response, building its inverse from an already-available tapped delay line (the latch 14 that claim 1 already requires) is a predictable use of a known technique. Under KSR, that is a respectable case.

Why it is nonetheless a real weakness in the obviousness case: the claim recites a specific circuit topology (a second coefficient multiplier at 0.5 tapping the delay output into a second adder with the un-delayed A/D output), not a functional result. None of the six references discloses or suggests a second, parallel digital output path. Pre-KSR — and the examiner in 1982 was applying pre-KSR law — the absence of any teaching or suggestion of an inverse-filter tap would likely have supported allowance. The patent's own prosecution history presumably rests here.

Assessment: claim 5 is the hardest claim to invalidate on this record. Genuine but incomplete obviousness case; I would not call it clear-and-convincing.

Claim 6 — the third multiplier applying input coefficient 0.5

A numeric narrowing of claim 1's α, with α = 1 − β ⇒ 0.5 when β = 0.5. Assessment: obvious — the specification itself presents 0.5 as the illustrative example throughout.

Claims 7 and 8 — the output compensation circuit

(comparator Y₁ vs. Y₁Z⁻¹ producing POSITIVE/ZERO/NEGATIVE; flag register set/reset; AND of flag with ZERO; OR with NEGATIVE; third adder injecting 0 or 1 step)

Combination: claim 5's subject matter in view of US 3,872,434.

The key insight available in the record is that US 3,872,434's "Mode Latch" does exactly the flag-register job — it "stores the mode for the previous scan for comparison to the mode of the present scan." Substituting that prior-state latch for the claim-7 flag register, adding a three-state comparator (POSITIVE/ZERO/NEGATIVE — a comparator with an equality output, ubiquitous), and gating with an AND/OR pair is a combination of admittedly known circuit elements performing their known functions, producing the predictable result of ±1-step hysteresis direction tracking. The claim's own truth table (W = NEG + ZER·F) is ordinary combinational logic.

Counter-consideration: the purpose here is unusual — not background tracking (US 3,872,434's use) but correcting a ±1 LSB wobble in an inverse-filtered A/D output. A motivation to reach for US 3,872,434's mode latch to fix that specific artifact is not directly taught and must be supplied by the PHOSITA's general knowledge. That is a KSR-style "known element, predictable result" argument; it is stronger than nothing but weaker than an express teaching.

Assessment: claims 7–8 are moderately vulnerable, but depend from claim 5 and inherit its gap for the inverse-filter structure; if claim 5 stands, claims 7 and 8 stand with it.

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5. Secondary considerations

• No litigation was located (per the earlier litigation section), so there is no adjudicated validity determination, no Finding of Fact, and no jury verdict to cite. There is likewise no evidence of commercial success, copying, industry praise, or long-felt-but-unmet need in the record for this patent.
• The ~19-year delay between issuance (1982) and the 1979 priority is not a secondary consideration, but the absence of any enforcement action over the patent's full life is at least consistent with the technology being a design technique rather than a product differentiator.
• Foreign prosecution cuts against the patentee: DE 3,026,230 was granted and then re-issued as C2 (1987-11-26) after further examination, and GB 2,060,293 B and JP S59-52576 B2 also issued. That the German Office had DE 2,511,594 C3 (its own national prior art) before it and still granted is a modest, non-binding indication of at least one distinguishing feature — worth understanding, but it proves nothing about US § 103.

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6. Bottom line

The overall § 103 case against US 4,353,060 lives or dies on two documents I could not retrieve. First, whether DE 2,511,594 C3 actually teaches hysteresis in A/D conversion by feeding the quantized output back to the input through a D/A converter and a sub-unity coefficient — if it does, claim 1 is in serious jeopardy and everything dependent on it follows. Second, whether any reference in the 1975–79 window teaches the inverse-transfer-function digital tap of claim 5; on the present record, none does, and that tap is the reason this patent is not obviously invalid.

Two honest limitations on the above: (i) I analyzed what the references say in their titles and partial text, not their full specifications, so each mapping line needs document-level verification; and (ii) I did not locate the file wrapper (USPTO PatentCenter/Global Dossier for US 06/165,037), which would show precisely which limitation the examiner relied on for allowance and which references were applied under § 103 versus merely listed under § 102 — that wrapper is the single highest-value next document to pull.