US 11402425

I'll verify the details with searches, including any 2026 CAFC docket activity.

US 11,402,425 B2 — Verified Summary

Scope note on the docket search: I searched for the specific number "11402425" / "11,402,425" together with CAFC/2026 docket terms. I found no Federal Circuit 2026 docket entry, appeal, IPR, or district-court case involving US 11,402,425. The Toshiba-related litigation that surfaced (MR Technologies GmbH v. Toshiba/Resonac HDD patents; Encryptawave Technologies v. Toshiba, E.D. Tex. 4:25-cv-00171, asserting US 7,233,664) concerns entirely different patents and is not related to this patent. I did not auto-correct any identifiers.

Bibliographic data

Abstract (as issued)

"A failure detector circuit of one embodiment acquires a first signal while transmitted from a first circuit to a second circuit and acquires a second signal while transmitted from the second circuit to a third circuit. The second circuit is located between the first circuit and the third circuit and transmits, to the third circuit, as the second signal, the first signal or a third signal having a given fixed state. The failure detector circuit outputs a fourth signal indicating detection or non-detection of a failure in the second circuit, in accordance with the first signal and the second signal."

Plain-language overview of the independent claims

Claim 1 (failure detector circuit). The claim covers a detector circuit that taps both sides of an intervening "second circuit" (an isolation/gating block): it reads the first signal on the wire into the second circuit and the second signal on the wire out of it. The second circuit, sitting between the first and third circuits, passes through either the first signal itself or a fixed-state substitute ("third signal"). Based on those two observed signals, the detector emits a fourth signal that says whether the second circuit has failed or not. Notably, the claim is functional/structural at a high level and does not itself require parity or any specific logic.

Claim 9 (failure detection system). The system claim puts the three circuits together: a first circuit that produces the first signal; a second circuit that outputs, as the second signal, either the first signal or a fixed-state third signal; a third circuit that operates on the second signal; and the failure detector circuit that watches both the first and second signals and emits the fourth signal indicating detection/non-detection of a failure in the second circuit.

Claim 17 (method). The method counterpart: acquiring/tapping the first signal (first→second circuit) and the second signal (second→third circuit), where the second circuit is interposed and passes either the first signal or a fixed-state third signal, then outputting the fourth signal indicating detection or non-detection of a failure in the second circuit based on the two acquired signals.

Dependent-claim architecture (for context)

• Parity-based comparison — claims 2, 10, 18 (calculate parity of the first signal, parity of the second signal, compare).
• Fifth signal (isolation control) states — claims 3, 11, 19: the second circuit passes the first signal in a first state and the fixed third signal in a second state, and the detector still outputs the fourth signal in both states.
• Fourth/fifth/sixth circuit implementations — claims 4, 12, 20: a fourth circuit computes a sixth signal (parity of the first signal); a fifth circuit passes that sixth signal as a seventh signal in the first state and a fixed-state signal in the second state; a sixth circuit outputs, as the fourth signal, a parity between the seventh signal and the second signal.
• Seventh circuit variants — claims 5/7/13/15 (seventh circuit runs a test/in-system self-test of the first circuit, driving the fifth signal to its second state during the test) and claims 6/8/14/16 (seventh circuit controls power supply to the first circuit, driving the fifth signal to its second state while power is interrupted).

Embodiment context

The specification presents two embodiments: (1) an in-system self-test (ISST) scenario in which the second circuit (isolation circuit module 3, comprising first isolation circuits 31 and a second isolation circuit 32) blanks the ISST target module's output during test, and (2) a power-gating scenario in which the isolation block blanks the output while power to the target module is interrupted. In both, a parity encoder 5 computes parity of the pre-isolation signal, the parity is carried through the second isolation circuit 32, and a parity decoder 6 XORs the post-isolation signal group against it to produce the failure alarm. The stated advantage is detecting isolation-block failures continuously, regardless of whether the self-test is running or power is gated.

Uncertainty flags

• All bibliographic and claim content above is taken from the full patent text you supplied (Google Patents rendering, fetched 2026-09-24), which I treated as authoritative; it aligns with the independent Justia and FreePatentsOnline postings of the same family.
• I could not confirm or refute any 2026 litigation/post-grant proceeding specifically involving US 11,402,425 — absence of search hits is not proof that none exists (PTAB/CAFC dockets are not fully indexed by the search tools available here). If you need a definitive litigation check, that should be run against PACER/Docket Navigator and the CAFC docket by patent number and by party (Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corp.).
• The "Active / expires 2041-01-29" status and the 2026-03-23 fee-reminder entry are third-party (Google Patents) indications, not an official USPTO legal conclusion; patent term was evidently adjusted, and the expiration date should be verified in Patent Center.

I'll search for litigation involving US patent 11402425.

Let me try more targeted searches on litigation databases.

Litigation Search: US Patent No. 11,402,425

Bottom line

No litigation, ITC investigation, or post-grant challenge involving US Patent No. 11,402,425 was found in my searches. I searched for the exact number (11,402,425 / "11402425") and the kind of sources you identified (Unified Patents litigation portal, Docket Alarm, CAFC opinions, PTAB filings, and general docket text). I did not find any district court complaint, ITC Section 337 action, PTAB petition (IPR/PGR), reexamination, or Federal Circuit appeal in which this patent was asserted or challenged.

Required fields

What I can confirm about the patent (grounding)

• Patent: US 11,402,425 B2, "Failure detector circuit, failure detection system, and method"
• Inventor: Naoei Terasawa
• Assignee: Kabushiki Kaisha Toshiba / Toshiba Electronic Devices & Storage Corporation
• Application: US 17/005,750, filed 2020-08-28; priority to JP 2020-030088 (2020-02-26); granted 2022-08-02; active, adjusted expiration 2041-01-29.
• Family members: US 2021/0263095 A1 (pre-grant publication), JP 2021135121 A, CN 113311310 A.
• Citations of record (5): JP 3349991 B2; US 2006/0242483 A1 (Rambus, Built-in self-testing of multilevel signal interfaces); JP 2003-098223 A; JP 2011-146903 A; and US 2021/0286005 A1 (Kabushiki Kaisha Toshiba, Failure detection circuit and semiconductor device) — the last being a later-filed Toshiba application cited as art, not a litigation reference.
• The Google Patents record for this patent shows no litigation events (no "Litigation" section and no district court docket links), which is consistent with my search results.

Important caveats

1. I cannot certify the absence of litigation. District court complaints are not always indexed in the free sources I can reach, and complaints asserting a patent can be filed without immediate public indexing. The authoritative checks would be:
   • Unified Patents litigation portal: https://portal.unifiedpatents.com/litigation/caselist (search the patent number directly)
   • PACER / CourtListener RECAP for docket-level confirmation
   • USPTO Patent Center "Litigation" / assignment records for this patent
   • ITC EDIS (https://edis.usitc.gov) for Section 337 investigations
   • PTAB (https://ptacts.uspto.gov) for any IPR/PGR on this patent
2. Per your strict rule, I did not auto-correct any number. Every result above corresponds to the literal string 11,402,425 / 11402425; I excluded near-miss numbers (e.g., the Toshiba-related US 11,639,961 B2, US 2021/0286005 A1, and unrelated Toshiba matters such as the MRT Technologies/Resonac media dispute that appeared in results).
3. Practically, this is not surprising: US 11,402,425 is a recently granted (2022) Toshiba circuit-testing patent, and Toshiba is not a frequent patent plaintiff in the U.S.; there is no indication in the record that it has been monetized or asserted.

If you want, I can run targeted queries against any specific database you have access to (or a Docket Navigator/Unified Patents export), but on the basis of the searches available to me, the answer is: no known litigation.

Proceedings overview

Total AIA trial proceedings on file for US 11402425: 0. There are no IPRs, PGRs, or CBM reviews — no active proceedings, no claims invalidated, no claims sustained, no settlements, no institution denials. The structured "PTAB proceedings on file" block (USPTO Open Data Portal) is the canonical source and returns an empty set, and my independent web checks surfaced nothing that the ODP has missed.

The bottom line for a defendant: this patent has never been tested at the PTAB. It is not "hardened by surviving IPRs," and it is not "gutted by cancellation." Both of those framings would be fabrications here. What you actually face is a virgin patent — claims 1–20 are all live and untested, and no petitioner has ever had to put art on the table, so you have no roadmap of what works and no § 315(e)(2) estoppel constraining you.

No proceedings to report

There are no proceeding-numbered subsections to populate. Per the operating rule against inventing proceeding numbers, I am not supplying placeholder IPR numbers, hypothetical petitioner names, or fabricated claim-level dispositions. Any such content would be sanction-bait in the truest sense.

What I searched (negative results, 2026-09-29):

• ODP / structured PTAB data for US 11402425 — empty (per prompt block).
• Web: US 11402425 PTAB inter partes review — no hits; results returned unrelated '024-family patents (a Bio-Rad/10X nucleic-acid patent, a CIG USA optical-module IPR) that merely share the number string "024."
• Web: "11402425" patent IPR petition Toshiba — no relevant hits (Australian Official Journal listings, unrelated Toshiba filings).
• Web: PTAB "IPR" "Failure detector circuit, failure detection system, and method" Toshiba — returned only the patent's own family/publication pages (FreePatentsOnline, Patents-Review, Baidu Xueshu), no Board documents.
• Web: patents.google.com/patent/US11402425B2 PTAB proceedings — no PTAB docket entries; results were unrelated '814/'025/'251 patent IPRs filed by Google, Amazon, Apple, and CIG USA.

Caveat on completeness: the ODP ingest can lag newly filed petitions by days-to-weeks, and my searches are not a substitute for docket-level verification. If a petition was filed in the last ~60 days, it may exist but not yet be indexed. Verify directly at PTAB E2E and by patent number at Docket Alarm / CourtListener before relying on the null result in a litigation posture.

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Strategic summary

Claim status of US 11402425: claims 1–20 are all UNTESTED. Nothing is canceled and nothing is sustained, because no tribunal has adjudicated any claim. Claim 1 is the broadest claim — a functionally recited failure-detector circuit that "acquires a first signal while transmitted from a first circuit to a second circuit," "acquires a second signal while transmitted from the second circuit to a third circuit," where the second circuit passes through the first signal or a fixed-state third signal, and that "outputs a fourth signal indicating detection or non-detection of a failure in the second circuit, in accordance with the first signal and the second signal." Independent claim 9 is the system counterpart; independent claim 17 is the method counterpart. Dependent claims 2–8 and 10–16 and 18–20 layer in parity comparison (claims 2, 10, 18), the fifth/isolation-control-signal two-state logic (claims 3, 11, 19), and the fourth/fifth/sixth-circuit architecture with the seventh circuit as either an ISST controller (claims 5, 7, 13, 15) or a power controller (claims 6, 8, 14, 16). Note the drafting: the "circuits" in claim 1 are defined by function and position in a signal path, not by structure — that is a live § 112(a)/(b) and § 101 pressure point for anyone drafting a petition, but I want to be clear that this is my own observation as a practitioner, not a finding by any panel, because no panel has looked at it.

Estoppel landscape: there is none, in either direction. § 315(e)(2) estoppel only attaches to a petitioner that has been through an instituted IPR to FWD, and no petitioner exists here. That is good news for you: every prior-art ground is still available — you can raise art in district court that a prior petitioner would have been estopped from raising, and you are not boxed into "reasonably could have raised" analysis. The corollary risk: because the patent has never been through the Office's post-grant machinery, its claims have not been narrowed by amendment or disclaimer, so the full original scope of every one of claims 1–20 is what you must design around or invalidate.

Pattern signals: no petitioner serial filings, no PTAB appeals by the patent owner (there is no FWD to appeal), and no evidence of a defensive aggregator such as Unified Patents in the chain — no Unified-style IPR appears in the ODP set or in search results. The patent is held by Kabushiki Kaisha Toshiba and Toshiba Electronic Devices & Storage Corporation (assignment recorded 2020-10-22, REEL/FRAME 054133/0864, inventor Naoei Terasawa). A large-entity operating company of Toshiba's profile is a defensive-assertion non-event in most scenarios — Toshiba is far more often a petitioner (see, e.g., Toshiba TEC Corp. et al. v. K.Mizra, IPR2022-01426, challenging U.S. 7,570,400) than a patent owner being IPR'd. That materially lowers the odds this patent ever attracted a third-party IPR in the first place, and explains the null result without implying the claims are strong.

One lead worth running down: the patent's own citation list includes US 20210286005A1 (Kabushiki Kaisha Toshiba, priority 2020-03-11, published 2021-09-16), titled "Failure detection circuit and semiconductor device." The "similar documents" list separately shows US 11,639,961 B2, same title and assignee. I infer — and flag as an unverified inference — that '005 is the pre-grant publication of the '961 patent, making it a close Toshiba sibling in the same failure-detection family. If you are mapping Toshiba's failure-detection portfolio, check '961 for PTAB activity separately; do not assume the null result for '425 carries over.

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Recommended next steps

Because there are zero proceedings, the usual "link to the FWD and quote the disposition" step does not apply. There is no FWD to link, and I will not link to one that does not exist. Concretely:

1. Say it plainly in your invalidity narrative. No PTAB activity is itself a signal: well-asserted, commercially significant patents eventually attract IPRs, often within 12–18 months of a first infringement suit. If this patent is now being asserted against you and it had a long prior life without a single petition, ask why — it may indicate the claims are narrow in practice, that practicing entities have already designed around them, or that the art is thin. It does not indicate the claims are valid.

2. You can still file first, and you should think about it early. With no prior petitioner, you face no § 325(d) "same art previously presented" estoppel and no General Plastic serial-petition risk. But watch two clocks: the § 315(b) one-year bar from service of a complaint alleging infringement of this patent (or a real party in interest / privy), and the § 315(a)(1) bar if you filed a DJ action first. If you want the Board as your forum, the petition must be on file within 12 months of service.

3. If you do file, the timetable is fixed by statute. Institution decision within 6 months of the petition's filing date (§ 314(b)); if instituted, the FWD is due within 12 months of the institution decision (§ 316(a)(11)), extendable up to 6 months only for good cause. Track oral hearing (typically ~2–3 months pre-FWD) and the patent owner's § 316(a)(9) preliminary response and, post-institution, any § 316(d) motion to amend — amendments are the principal way a never-IPR'd patent narrows.

4. Deprioritize PTAB until you verify the null result. Re-run the check against PTAB E2E by patent number and against the CAFC docket for any appeal naming Toshiba as appellant and this patent. Absent a hit, your validity fight is a district-court (or ITC) fight, and your best near-term lever is the claim-drafting generality in independent claims 1, 9, and 17 rather than an Office record that does not yet exist.

Verification trail for the null result: US11402425B2 on Google Patents (no PTAB proceedings section populated); PTAB E2E public search; US20210263095A1 pre-grant publication.

I'll research the assignment record for US 11,402,425, starting with the assignment data I can extract from the patent record and verifying against public sources.

Let me search for the assignment correspondent and any additional recorded assignments.

Let me try to retrieve the recorded assignment correspondent and check for any later assignments.

Ownership & Assignment Analysis: US Patent No. 11,402,425

Patent: US 11,402,425 B2 — "Failure detector circuit, failure detection system, and method"
App: 17/005,750 · filed 2020-08-28 · granted 2022-08-02 · adjusted expiration 2041-01-29
Family: US 2021/0263095 A1 · JP 2021135121 A · CN 113311310 A · priority JP 2020-030088 (2020-02-26)

A note on scope before the fields: I could retrieve the one recorded assignment's reel/frame and parties from the Google Patents legal-events record, but the correspondent of record (the attorney/agent who filed the recording) is not exposed in any free source I could reach — it is not shown in the Google Patents legal-events table, and my searches of assignment indexes returned only unrelated near-miss hits (e.g., a UK company numbered 11402425). I therefore report the correspondent as not determinable from available sources rather than guessing.

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Inventors

• Single-inventor patent. No co-inventors, which simplifies the chain — there is only one assignor to trace.
• Unusual-pattern check: There is no evidence of inventor departure, and no basis to infer one. This is a standard employee-inventor situation: the patent's prosecution was handled as a corporate Toshiba filing and the inventor's rights were assigned to his employer (see timeline). Nothing here resembles the "all inventors leave within 12 months" precursor to a portfolio fire-sale.

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Original assignee

Two co-assignees are named on the face of the issued patent:

1. Kabushiki Kaisha Toshiba (Toshiba Corp.), 1-1, Shibaura 1-chome, Minato-ku, Tokyo 105-0023, Japan
2. Toshiba Electronic Devices & Storage Corporation, Kawasaki, Kanagawa, Japan

• Primary line of business: Toshiba Corporation is a diversified global electronics/energy/infrastructure conglomerate. Toshiba Electronic Devices & Storage Corporation (established 2017-07-01 via Toshiba's company-split of its Storage & Device Solutions business) is Toshiba's semiconductor and HDD operating company — power devices, MCUs, analog ICs, HDDs (per its own product literature and JPX LEI record 353800H52ZXK0JZ9IR13, parent LEI 549300LBHTST91VKHO68 = Toshiba).
• Does it ship a product embodying the claims? The claims cover a failure-detection / isolation-circuit architecture for use inside an LSI or MCU. Toshiba Electronic Devices & Storage sells MCUs and automotive/industrial ICs and is the natural embodied-product owner of an internal circuit-testing feature; it is the assignee that holds ~2,900 patents in Japan per company registries. This is a product company technology, not a licensing vehicle.
• Current status: Operating, solvent, parent-owned. Toshiba Corp. was taken private in 2023 by Japan Industrial Partners (JIP), but Toshiba Electronic Devices & Storage remains an active subsidiary (LEI status 有効 / "valid"). No bankruptcy, no dissolution, no receivership. (Checked against JPX LEI and corporate registry data.)

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Assignment timeline

There is exactly one recorded assignment in the chain, and it is the inventor's original conveyance to the employer — not a post-issuance transfer.

• 2020-10-07 (executed) / recorded 2020-10-22 — Reel 054133 / 0864
  • Conveyance: Assignment (original inventor-to-employer conveyance; "ASSIGNMENT OF ASSIGNOR'S INTEREST")
  • Assignor: Naoei Terasawa (sole inventor)
  • Assignee (joint): Kabushiki Kaisha Toshiba and Toshiba Electronic Devices & Storage Corporation — both recorded under the same reel/frame 054133/0864
  • Correspondent: Not determinable from the sources I could reach. Google Patents' legal-events table reproduces the assignment's parties, effective date, and reel/frame but omits the correspondent. I did not locate this recording in a public index that exposes the attorney/agent of record. To capture it you must query USPTO Assignment Center directly by the reel/frame (054133/0864) or by the patent number. (I am flagging this as a genuine gap, not a "not present" finding.)
  • Context: Internal/employment assignment — the inventor assigning his rights to his Toshiba employers. Executed ~5.5 months after the 2020-08-28 US filing and after the 2020-02-26 JP priority filing; routine formalization of a corporate filing, not an arm's-length or distress transaction.

No further assignments were recorded after issuance. Google Patents' legal-events record for this patent lists only: the 2020 assignment; docketing (2021-08-08); notice of allowance (2022-03-29); patent grant (2022-07-13); and a routine maintenance-fee reminder (2026-03-23). There is no change-of-name, merger, security agreement, license-recordal, release, or second assignment. Recorded custody has therefore never left the Toshiba group.

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Timeline diagram

timeline
    title Ownership of US 11402425
    2020 : Priority JP filing Feb 26
         : US application filed Aug 28
         : Terasawa assigns to Toshiba Oct 22
    2022 : Patent granted Aug 2
    2026 : Maintenance fee reminder Mar 23

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NPE / troll-pattern signals

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Verdict

Insufficient data (only the original assignment).

The recorded chain consists of a single inventor→employer conveyance on reel 054133/0864 (executed 2020-10-07, recorded 2020-10-22), assigning Naoei Terasawa's rights jointly to Kabushiki Kaisha Toshiba and Toshiba Electronic Devices & Storage Corporation. There are no post-issuance assignments, no shell-entity transfers, no known asserter, and no litigation (consistent with the earlier litigation summary), so every NPE/troll signal above is either "not present" or, for the correspondent-based signals, unevaluable because the correspondent was not retrievable and the chain contains only one link. This maps to the defined "Insufficient data — only the original assignment" verdict rather than "operating-company assertion," because Toshiba has not asserted the patent and there is no litigation record to characterize. Practically, the patent simply sits with the original operating-company owner.

Two explicit caveats:

1. The correspondent of record is a genuine gap in this analysis — it is not exposed by the free sources I can reach. Confirm it at USPTO Assignment Center (query reel 054133/0864): https://assignmentcenter.uspto.gov/
2. My findings rest on the Google Patents legal-events table for US 11,402,425 — verify the absence of any second assignment directly against the Assignment Center and Patent Center records before relying on this for a standing/ownership opinion.

Verification link: USPTO Assignment Center — https://assignmentcenter.uspto.gov/ (search patent number 11402425 or reel/frame 054133/0864).

I'll research each cited reference to build the prior-art analysis. Let me run targeted searches.

Let me gather additional detail on the closest reference and the family publication.

Prior-Art Analysis — US Patent No. 11,402,425

Note on scope/method: The five references below are the citations of record listed on the face of US 11,402,425 ("Patent Citations (5)") in the Google Patents rendering of the USPTO record (https://patents.google.com/patent/US11402425/en). I searched and report only on the literal number 11402425; near-numbers (e.g., US 11,639,961, US 2021/0286005, US 2021/0263095) are addressed only where they are the same document under a different identifier, and I say so explicitly.

Critical framing (must not be skipped): These are references the examiner considered, and the patent issued over all of them. Under 35 U.S.C. § 102, anticipation requires a single reference disclosing every limitation of a claim. As shown below, none of the five cited references appears to fully anticipate any independent claim, because none discloses the core limitation of claim 1 — comparing the signal acquired before an isolating "second circuit" against the signal acquired after it, where that second circuit passes either the first signal or a fixed-state third signal, to output a failure signal for the second circuit itself. The references are better characterized as § 103 obviousness-type art than as § 102 anticipatory art. I flag this rather than force a § 102 match.

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1. Citations of record (summary table)

All five are flagged as examiner-cited in the record. References 1–4 predate the present patent's earliest priority date (2020-02-26) and are facially available as prior art. Reference 5 is not — see the flag in §3.5.

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2. The claim ladder being tested

So the § 102 analysis is checkable, the operative claim elements are:

• Claim 1 (independent, failure detector circuit): (a) acquire a first signal transmitted first-circuit → second-circuit; (b) acquire a second signal transmitted second-circuit → third-circuit; (c) the second circuit sits between first and third circuits and passes, as the second signal, either the first signal or a third signal having a given fixed state; (d) output a fourth signal indicating detection/non-detection of a failure in the second circuit, as a function of the first and second signals.
• Claim 2: compute parity of the first signal and parity of the second signal; output the fourth signal from the comparison.
• Claim 3: second circuit passes the first signal when a fifth signal is in a first state, passes the third signal in a second state; failure detector operates in both states.
• Claim 4: fourth circuit outputs a sixth signal = parity of the first signal; fifth circuit passes sixth signal as a seventh signal in the first state / fixed state in the second state; sixth circuit outputs the fourth signal = parity between seventh and second signals.
• Claims 5–8: the fifth signal comes from a seventh circuit that either runs a test (ISST) of the first circuit (5, 7) or controls power supply to it (6, 8).
• Claim 9 / 17 (independent): system / method counterparts of claim 1; claims 10–16 / 18–20 mirror 2–8.

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3. Reference-by-reference § 102 assessment

3.1 JP 3349991 B2 — "IC test system" (NEC Micro Systems)

• Full citation: JP 3349991 B2; JP application 11-188541 (filed 1999-07-02); granted/published 2002-11-25; assignee エヌイーシーマイクロシステム株式会社. https://patents.google.com/patent/JP3349991B2/en
• Brief description: IC-test technique for detecting failures in the wiring/connection portions between functional macroblocks (e.g., IP blocks) that a conventional "separation test" (which isolates a block's terminals and drives them directly from the tester) cannot reach. It uses selector groups (分離テスト用セレクタ) to isolate the macroblocks and then tests the inter-block nets (nets 1–3) with real-operation or scan-path patterns.
• § 102 relevance / potential claims: None anticipatory. Elements (a)/(b)/(d) are absent. The selectors arguably resemble the "second circuit that substitutes a fixed state," and the goal (finding a failure at the block boundary) superficially aligns with claim 1(c), but the reference detects failures in the interconnect between blocks, not a failure in the isolating circuit itself, and it does not compare a pre-isolation first signal against a post-isolation second signal to produce a failure signal. It is at most weakly relevant to the preamble of claim 1 / claim 9 / claim 17 as background, and is stronger as § 103 art.

3.2 US 2006/0242483 A1 — "Built-in self-testing of multilevel signal interfaces" (Rambus Inc.)

• Full citation: US 2006/0242483 A1; continuation of US 09/953,514 (priority 2001-09-14); filed 2006-05-12; published 2006-10-26; Rambus Inc. https://patents.google.com/patent/US20060242483A1/en
• Brief description: BIST mechanisms for multilevel (multi-PAM) signal interfaces. A test-signal generator (e.g., PRBS) drives an interface; the received/decoded signal is compared against a binary reference signal; a mismatch produces an error signal. Testing can be single-interface, grouped, or master/slave (master device tests slave interfaces and compares a signal derived from the returned signal to a locally generated reference).
• § 102 relevance / potential claims: Closest of the five on the "compare a transmitted signal to detect a failure" idea, but not anticipatory. It does not disclose a "second circuit" that selectively substitutes a third signal having a given fixed state in place of the first signal (element (c) of claim 1), nor a failure signal for that circuit (element (d)). Its comparison is decoded-test-signal vs. reference signal in a memory channel, not parity of a signal captured before vs. after an isolation circuit. Best characterized as relevant to the general concept of claim 1 / claim 2 (comparison-based error detection) as § 103 art; it does not meet claim 2's parity limitation (Rambus uses PRBS/bit comparison, not a parity XOR).

3.3 JP 2003-098223 A — "Scan test circuit and method" (Matsushita Electric Industrial)

• Full citation: JP 2003-098223 A; priority 2001-09-25; published 2003-04-03; Matsushita Electric Industrial Co., Ltd. https://patents.google.com/patent/JP2003098223A/en
• Brief description: Scan test for an LSI having power-cutoff function blocks. Observation flip-flops (9, 10) are inserted before the input and after the output of the power-down block B. A power-cutoff transition signal (16) resets the input-side FF, fixing the block's input level and the output level during power-down; the FFs are chained into a scan chain (14/15) and, after release of the transition signal, a scan-shift verifies whether the power-down state-fixing control was correct.
• § 102 relevance / potential claims: Strong background for the second embodiment (isolation during power interruption) and relevant to the environment of claims 6/8/14/16 ("controls power supply… maintains the second state while interrupting the power supply"). However, it is not anticipatory: verification is by scan-shift observation, not by comparing a pre-isolation first signal with a post-isolation second signal, and no "fourth signal indicating detection/non-detection of a failure in the isolating circuit" is generated. No independent claim (1, 9, 17) is met.

3.4 JP 2011-146903 A — "Semiconductor device and method for controlling semiconductor device" (Renesas Electronics)

• Full citation: JP 2011-146903 A; priority 2010-01-14; published 2011-07-28; Renesas Electronics Corporation. (It appears in the citation networks of, e.g., US 2004/0027173 and US 9,411,390 — https://patents.google.com/patent/US20040027173 .)
• Brief description: A semiconductor device and control method relating to power-gating / isolating a power line to an internal circuit and the associated test/control signaling (as reflected by the title, assignee, and its citation context among power-gating and inter-block-control patents).
• § 102 relevance / potential claims: No anticipation. Relevant at most as background to the power-supply-control clause of claims 6/8/14/16. Caveat: my searches did not retrieve the full JP 2011-146903 A text (tool budget was exhausted), so I am characterizing this reference by its bibliographic record and its citation family context, not by a claim-chart reading. I explicitly flag this rather than assert a limitation-by-limitation comparison. Its face date (2010) does place it in the prior-art window.

3.5 US 2021/0286005 A1 — "Failure detection circuit and semiconductor device" (Kabushiki Kaisha Toshiba) ⚠️

• Full citation: US 2021/0286005 A1; priority 2020-03-11; published 2021-09-16; Kabushiki Kaisha Toshiba. (Granted as US 11,639,961 B2, which appears in the "Similar Documents" list of US 11,402,425.) https://www.patents-review.com/a/20210286005-failure-detection-circuit-semiconductor-device.html

• Brief description: A Toshiba failure-detection circuit in a semiconductor device (e.g., in a vehicle-control communication module). A third circuit outputs a sixth signal whose level (third level vs. fourth level) depends on whether a second signal and a fifth signal have the same or different levels, and the device distinguishes a "normal state" from a "failure state." This is the most technically cognate citation — same field, same assignee, same "detect a failure by comparing signals" architecture.

• § 102 relevance / potential claims — TWO problems:

  1. It is not prior art on its face as to US 11,402,425. US 11,402,425's earliest effective filing date is 2020-02-26 (JP 2020-030088). US 2021/0286005 A1's earliest effective filing/priority date is 2020-03-11 — after 2020-02-26. Under both pre-AIA § 102 and AIA § 102(a)(1)–(a)(2), a US application publication with a later effective filing date than the challenged patent's priority date is not available as § 102 prior art. (In AIA § 102(a)(2) terms it fails the "effectively filed before the effective filing date of the claimed invention" test, notwithstanding the different-inventor requirement.)
  2. Even ignoring dates, its disclosure (comparing a second signal and a fifth signal to generate a sixth failure-indicating signal) is a different architecture from the claimed "compare pre-isolation first signal to post-isolation second signal, where the middle circuit substitutes a fixed-state third signal." No independent claim is anticipated.

  Conclusion: This is a same-assignee, same-field later document. If it is genuinely flagged as examiner-cited, that is worth verifying against the USPTO file wrapper — as a matter of § 102 it cannot legally be prior art to US 11,402,425.

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4. Secondary references (family-cited, not in the "Patent Citations (5)" list)

The record also lists three documents cited by family members ("Family Cites Families (3)"), which are not the five citations of record for this US patent but are sometimes relevant in foreign prosecution:

None of these discloses parity comparison of a signal captured across an isolating circuit, and none anticipates any claim of US 11,402,425.

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5. Bottom line on § 102

• No cited reference anticipates any independent claim (1, 9, or 17), because none discloses all of: capturing the first signal and the second signal across a middle circuit that substitutes a fixed-state third signal; and outputting a failure signal for that middle circuit based on the first and second signals.
• Most technically relevant citation: US 2021/0286005 A1 (Toshiba) — but it is later-dated (2020-03-11) than the patent's 2020-02-26 priority and therefore is not § 102 prior art; treat it as a related/cognate document, not a novelty reference.
• Most relevant genuine prior art for the "compare-to-detect-error" idea: US 2006/0242483 A1 (Rambus) — § 103-type art against the comparison concept of claims 1/2, but not a § 102 anticipation (no fixed-state isolation circuit; no parity).
• Most relevant for the power-isolation embodiment: JP 2003-098223 A (Matsushita) and, secondarily, JP 2011-146903 A (Renesas) — background/§ 103 art for claims 6/8/14/16.
• JP 3349991 B2 (NEC) — background on inter-block failure detection via isolating selectors; not anticipatory.

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6. Caveats and consistency check

1. Consistency with the prior litigation section: Nothing here contradicts it. That section found no litigation/PTAB/ITC activity for US 11,402,425; the grant over these five references is consistent with a clean, unasserted patent.
2. § 102 vs. § 103: Your instruction asked specifically about § 102. I have not overstated the references into anticipations. In practice these five are best deployed as § 103 art (individually or in combination), with Rambus + Matsushita being the most plausible combination against the two embodiments.
3. Retrieval limitation (disclosed, not hidden): I could not retrieve full text for JP 2011-146903 A; my § 3.4 assessment rests on its bibliographic record and citation context, not a limitation-by-limitation reading. For a filing-grade chart, pull the JP machine translation and JP 3349991 B2's figures from J-PlatPat/Espacenet.
4. Verify the US 2021/0286005 A1 citation basis: Given its post-priority date, confirm in USPTO Patent Center / the file wrapper whether it was truly cited as prior art or merely cross-referenced as a co-pending same-assignee case. This is the one item most likely to be mislabeled in third-party records.
5. No patent numbers or identifiers were auto-corrected; every identifier above is reproduced literally as it appears in the record.

I'll gather details on the prior-art references of record before building the §103 analysis.

Let me pull the two Japanese references I haven't confirmed yet, plus the closely-related Toshiba family member.

Obviousness Analysis — US 11,402,425 B2 under 35 U.S.C. § 103

Note on inputs. The "Prior Art section of this page" gives five references of record plus three "Family Cites Families" (JP H10-149377 A; JP 4067945 B2; JP 4450279 B2). I retrieved substantive text for JP 2003-098223 A, JP 3349991 B2, and US 2006/0242483 A1. I could not retrieve the substance of JP 2011-146903 A or the three family cites, so those are treated as supporting/atmospheric art only, not as load-bearing references, and are flagged below. No identifiers have been auto-corrected.

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1. Framework and assumptions

• Effective filing date: 2020-02-26 (JP 2020-030088 priority). AIA §§ 102/103 apply; priority date is well after the publication dates of all four printed publications relied on below, so each is § 102(a)(1) prior art.
• Governing standard: Graham v. John Deere, 383 U.S. 1 (1966) (scope/content of art; differences; PHOSITA level; secondary considerations), as modified by KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007). Under KSR, a teaching-suggestion-motivation test is not the exclusive route; any articulated reasoning with a rational underpinning suffices. I apply the MPEP 2143 rationales (A)–(G) expressly.
• Evidentiary posture: These references were before the examiner (they appear as citations of record), which means any § 103 case built on them is a prima facie case on the same record, not a new-art case. Critically, the examiner nevertheless allowed 20 claims — so I also analyze where the applicant's rebuttal must have landed.

1.1 A flag on one "cited" reference

The earlier-generated summary lists US 2021/0286005 A1 among "Cited prior art." It is cited of record, but its listed priority date (2020-03-11) is after this patent's 2020-02-26 effective filing date, so it cannot be § 102(a)(1) or § 102(a)(2) prior art against these claims. It is a Toshiba application (same assignee family as the patent-in-suit; the closely related US 11,639,961 B2, "Failure detection circuit and semiconductor device," is a different patent and must not be conflated with the patent at issue). I treat it as context/admissions only — if it were used in a rejection, that would be legal error. Flagging because the earlier section's phrasing ("Cited prior art") could be misread.

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2. Level of ordinary skill in the art (PHOSITA)

A bachelor's degree in electrical engineering (or equivalent) plus roughly 2–3 years of experience in digital IC design/design-for-test, including logic built-in self-test (BIST), scan-based test, and power-gating/isolation-cell design — or a master's with less experience. This is a mature, incremental arts area; the ordinary artisan is comfortable with XOR parity trees, signature analysis, boundary isolation cells, and power domain controllers. The Office's own classification of this patent in G01R 31/31703 — "Comparison aspects, e.g. signature analysis, comparators" is corroborative: the examiner placed the invention squarely within the comparison-monitoring arts.

3. Claim construction of the load-bearing terms

Claim-drafting note (relevant to obviousness breadth): Independent claim 1 is phrased "A failure detector circuit that: acquires… and outputs…" — a structural preamble with method-style steps. It is functionally broad: it recites comparing what goes into a gating block with what comes out. The narrow, structurally specific material (parity encoder → dedicated isolation cell for the check bit → parity decoder) appears only in claim 4/12/20. This matters: the broad independent claims are the easiest to invalidate and carry little weight beyond the abstract comparison idea.

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4. The prior art and what each reference actually teaches

4.1 JP 2003-098223 A — Matsushita, "Scan test circuit and method" (pub. 2003-04-03; priority 2001-09-25) — the primary reference

Source: https://patents.google.com/patent/JP2003098223A/en

This reference is strikingly close, and it is the power-gating scenario of the patent's own second embodiment:

• A system LSI (1) has functional block A (2) and functional block C (4) on always-on power, and functional block B (3) whose power is cut off depending on circuit usage.
• Observation flip-flop groups 9 and 10 are inserted before the input signal of block B and after the output signal of block B — i.e., taps on both sides of the interposed block.
• A power cutoff transition signal (16), with AND element 21, OR element 20 and NOR element group 24 in block B's I/O modules 12/13, fixes the input signal level to block B and fixes the output signal level at power-off ("状態固定信号") — i.e., substituting a fixed-state signal for the normal signal.
• The stated problem is exactly the patent's problem: "to ensure testability of a circuit existing in an input/output unit of a functional block to be powered down, and to facilitate verification of a control state at the time of power shutdown," and its claim 1 recites an "input/output-section failure detection means" (入出力部故障検出手段) for the power-cutoff target block.
• Verification is performed by chaining observation FFs 9, 10 into one scan chain, releasing the power-cutoff transition signal, shifting out, and checking whether the power-off-time control was normal.

Gap: the failure determination is latched and shifted to an external tester; there is no on-chip comparator that autonomously emits an alarm, and no parity/signature comparison on-chip.

4.2 US 2006/0242483 A1 — Rambus, "Built-in self-testing of multilevel signal interfaces" (pub. 2006-10-26; priority 2001-09-14) — the secondary reference supplying the on-chip comparator/alarm

Sources: https://www.freepatentsonline.com/y2006/0242483.html ; family WO 2003/025599 A1 / US 2003/0070126 A1

• Discloses "error detection mechanisms for signal interfaces … including built-in self-test (BIST) mechanisms," implemented on the IC.
• Discloses a device (FIG. 6) with a signal interface coupled to a signal generator and an error detector, and (FIG. 7/8) interface units connectable in series for testing with pseudo-random bit sequence generators — i.e., a signature-generation/testing architecture.
• Expressly: a generator provides a test sequence; a memory receives and synchronizes the test sequence and the received signal; "a logic circuit … is to compare the test sequence and the signal" and "if there is a difference, the logic circuit is to assert an error condition." That is a comparison of the signal before vs. after the circuit under test, producing a binary failure/error output — functionally the "fourth signal."
• Also discloses control logic that decouples/disable normal interface paths and disables additional transmitters/receivers during the test mode — i.e., a form of isolation of the circuit under test, reinforcing combinability.

Gap: the compared entity is a channel/interface, not an isolation/power-gating block; and while Rambus teaches on-chip comparison and error assertion, it is discussed in an offline/BIST context rather than as a continuous monitor.

4.3 JP 3349991 B2 — NEC Microsystems, "IC test system" (pub. 2002-11-25; prior art date 1999-07-02)

Source: https://patents.google.com/patent/JP3349991B2/en

• Addresses IC testing where isolation (separation) test selectors (4–8) are placed at functional macroblock (BLK1/BLK3) boundaries to directly drive/observe macroblock terminals from outside the test system.
• Its stated purpose is to detect faults in the interconnect/wiring between functional macroblocks (nets 1–3) — i.e., the very structures that the isolation logic sits within — because "separation test alone" cannot check them.
• Supplies the motivation and mechanism for monitoring a boundary between blocks and for a control signal that switches the boundary between a normal path and a test/fixed path.

4.4 JP 2011-146903 A — Renesas, "Semiconductor device and method for controlling semiconductor device" (pub. 2011-07-28; priority 2010-01-14) — NOT VERIFIED

I could not retrieve its substance. Based on title/assignee it is likely directed to power/isolation control in a semiconductor device, but I will not assume its disclosure. It is therefore excluded from every combination below and only noted as a probable third-order reference an examiner could also have cited.

4.5 Family cites (JP H10-149377 A; JP 4067945 B2; JP 4450279 B2) — NOT VERIFIED

Titles suggest logic verification, semiconductor IC/memory control, and semiconductor IC device, respectively. Not used as load-bearing art.

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5. Combination 1 (primary): JP 2003-098223 A in view of US 2006/0242483 A1

References combined: JP 2003-098223 A (primary) + US 2006/0242483 A1. Optionally further in view of JP 3349991 B2.

5.1 Why a PHOSITA would combine them (articulated reasoning)

1. Same field, same problem, same sub-system. Both references are IC test/fault-detection arts; both concern observing a signal as it crosses a functional boundary inside an integrated circuit (JP 2003-098223 at a power-gated block's I/O; Rambus at a signal interface). KSR: combination of familiar elements according to known methods, yielding no more than predictable results (MPEP 2143(A)).
2. Simple substitution. JP 2003-098223 already taps both sides of the block — it just routes the taps away via scan chain to a tester. Rambus supplies a known, off-the-shelf alternative way to evaluate two signals on-chip: compare them, and if they differ, assert an error. Substituting Rambus's comparator/error-assert for the external scan-based evaluation is substitution of one known element for another to obtain the predictable result of an on-chip failure indication (MPEP 2143(B)). The substitution also yields the patent's own stated desideratum — detection that works without invoking a test mode — which is precisely the point of an always-available on-chip monitor.
3. Improving a similar device in the same way. Comparison/signature-based fault detection was a known technique for improving observability of digital blocks; applying it to the isolation boundary is improvement of a similar device in the same manner (MPEP 2143(C)).
4. The device was "ready for improvement," and the art identified the defect. JP 3349991 B2 teaches that isolation/boundary structures and inter-block wiring are a recognized fault location that "separation test" misses. That is an express design incentive to instrument exactly that boundary (MPEP 2143(D), (F)).
5. Obvious to try / finite predictable solutions. For monitoring a gated boundary there are only a handful of known options — duplicate-path comparison, parity/signature check bit, scan-based observation, DMR. Enumeration and selection is routine (MPEP 2143(E)).
6. No teaching away. Nothing in either reference disparages on-chip comparison or continuous monitoring. Rambus's own test mode decouples the normal path — the same isolation behavior the patent relies on.

5.2 Claim chart — claims 1, 2, 3, 9, 10, 11, 17, 18, 19

Conclusion for Combination 1: Claims 1, 3, 9, 11, 17, and 19 are prima facie obvious with a strong rational underpinning. Claims 2, 10 and 18 are obvious over the same combination further in view of the elementary, well-known parity/signature-comparison technique (corroborated by the examiner's own classification in G01R 31/31703).

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6. Combination 2: adding JP 3349991 B2 — claims 5, 7, 13, 15 (test-of-first-circuit variant)

• JP 3349991 B2 discloses a test system with isolation-test selectors at macroblock boundaries and a test controller that drives the boundary into a test configuration; JP 2003-098223 A supplies a scan test mode signal (17) and a mode-transition control. Together they teach a seventh circuit that conducts a test of the first circuit, holds the fifth signal at state one while not testing and state two during test.
• Motivation: instrumentation of a block under test by isolation of its outputs is the raison d'être of both references; adding continuous comparison monitoring to a test-isolated boundary merely secures the same boundary against faults the test itself cannot see (JP 3349991 B2 says as much about separation test's blind spots).
• Claims 5 and 7 are near-duplicates of each other (both recite the seventh circuit performing a test), and both fall together. Once the core concept is obvious, redundant permutations add nothing patentable — this redundancy is a claim-drafting artifact, not a source of separate inventive weight.

7. Combination 3: claims 6, 8, 14, 16 (power-control variant)

• This is the closest fit of all. JP 2003-098223 A alone discloses the power-control variant: a power control that maintains an isolation/state-fix control signal at a first state while power is normal and at a second state while power is cut, with the boundary observation circuitry verifying the resulting behavior. With Rambus for the on-chip alarm output, claims 6/8/14/16 are prima facie obvious on the same reasoning as § 5 — arguably with the highest confidence of the set, because the primary reference is a power-gating reference.

8. Combination 4: claims 4, 12, 20 — parity encoder / dedicated isolation cell for the check signal / parity decoder

This is the only family of claims where the obviousness case needs an extra step, because the specific topology — an XOR parity encoder (fourth circuit), a separate isolation circuit (32) that carries the parity bit through the isolation boundary on the same control signal, and an XOR parity decoder (sixth circuit) that compares — is not squarely taught by any single reference of record.

Why it is nonetheless obvious:

1. The topology is dictated by the goal. To keep the equality comparison valid in both states, the check bit must be subjected to the same isolation as the data bits. If the check bit bypassed the isolation cell while the data bits were forced to the fixed state, the comparison would flag a false failure every time the block was isolated — which would defeat the whole purpose. A PHOSITA seeking "constant detection in both states" (the patent's self-stated advantage) would inevitably put the check path through its own isolation cell. That is a predictable design consequence, not an inventive leap (MPEP 2143(A), (C)).
2. The parity/check-bit idea itself is elementary (XOR tree encoder + XOR tree decoder). Corroborated by the Office's G01R 31/31703 classification ("comparison aspects, e.g. signature analysis, comparators") and by Rambus's signature-analysis disclosure.
3. The specification concedes arbitrariness. The patent states that the encoder "can be optionally configured," that the L-state values are "as an example," that the isolation circuits' fixed state "is not limited to such an example," and even sets out the alternative (an odd number of isolation circuits outputting H). Where the patentee's own disclosure labels the parameters arbitrary and modifiable, the variation cannot supply non-obviousness.
4. The patent's own explanation of why it works is a mathematical truism: "the parity of the signal group output from the first isolation circuits is to be low and logically equivalent to the signal having the L-state output from the second isolation circuit." Parity of an all-zeros group is zero — a known property, not a discovery.

Assessment: Claims 4, 12 and 20 are obvious, but with moderate rather than high confidence, because no single reference of record shows the duplicated check path through its own isolation element. A well-crafted rejection would pair JP 2003-098223 A + Rambus + JP 3349991 B2 + a parity-check-bit reference (or an official-notice-style reliance on the admitted state of the art and the specification's own admissions).

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9. Non-obviousness arguments the patent owner would raise — and my evaluation

Weakest point in my prima facie case: as noted, no reference of record squarely discloses the check-signal-through-its-own-isolation-cell architecture of claims 4/12/20, and none frames the comparison as a continuously operating monitor (as opposed to a BIST/test-mode function). Those are the two genuine points of daylight, and they are narrow.

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10. Ancillary observation (outside §103, but material to overall validity posture)

Because claim 1 recites essentially "observe the input of a gating block, observe its output, and emit a signal saying whether the block failed," it is also exposed to a §101 Alice challenge as a comparison of two signals implemented with generic logic (the encoder/decoder/shift-out are all conventional). This is a parallel vulnerability, not a §103 point, and I flag it only because it affects how much weight the broad independent claims can realistically bear.

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11. Overall conclusion

Bottom line: The overwhelming majority of the 20 claims — in particular the broad independent claims 1, 9 and 17 and the parity claims 2, 10, 18 — would, in my view, be rendered obvious by JP 2003-098223 A in view of US 2006/0242483 A1, with JP 3349991 B2 as a reinforcing reference. The combination is supported by at least five independent KSR/MPEP 2143 rationales, and there is no objective-indicia record to rebut it. Only the specific topology of claim 4/12/20 (a parity check signal routed through its own isolation cell on the same isolation control) presents a real, though narrow, non-obviousness question — and even that is arguably a predictable design consequence of the patent's own stated goal of valid detection in both states.

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12. Uncertainty flags and what to verify

1. JP 2011-146903 A (Renesas) — text not retrieved. It is excluded from all combinations. If it discloses power/isolation control with boundary monitoring, it could strengthen (or independently supply) the § 103 case against claims 6/8/14/16 and 3/11/19.
2. Family cites JP H10-149377 A, JP 4067945 B2, JP 4450279 B2 — contents not verified; not relied upon.
3. US 2006/0242483 A1 — I retrieved its abstract/summary/detailed-description text, but search results interleaved content from its Rambus siblings (US 2003/0070126 A1, WO 2003/025599 A1, US 7,168,672, US 8,378,699). The "compare and assert an error condition" teaching is common to the family; if a rejection is built on it, cite the specific paragraphs of US 2006/0242483 A1 itself.
4. No comparison of the pre-grant publication (US 2021/0263095 A1) claims against the issued claims was possible here. If the issued claims were narrowed during prosecution (e.g., to add the duplicated check path), that amendment is the best evidence of where the applicant believed the art stopped — and it should be read in the file wrapper before finalizing any invalidity position.
5. US 2021/0286005 A1 / US 11,639,961 B2 are same-assignee, later-in-time Toshiba filings and are not prior art; do not conflate their subject matter with US 11,402,425.
6. Weak, non-dispositive signal: the CN family member CN 113311310 A is recorded as withdrawn (Google Patents status "not_active Withdrawn"). That is occasionally consistent with a crowded prior-art field in the CN/JP prosecution, but it is a heuristic only and I would not rely on it as evidence of obviousness.
7. A definitive § 103 opinion requires the file wrappers (USPTO Patent Center for US 17/005,750 and JP 2021135121 A) to see which references were actually applied and what arguments the applicant made.