US 10763865

US patent 10763865, titled "Field programmable gate array with internal phase-locked loop," was filed on May 29, 2020, by inventor Nima Badizadegan, and issued on September 1, 2020. The current assignee is HFT Solutions LLC, effective April 4, 2022. The original assignee was listed as an individual.

Abstract:
The patent describes a field programmable gate array (FPGA) system and a method for processing a data stream using it. The system includes an FPGA with a first interface for receiving a first clock signal and a first serial data stream, and for transmitting a second serial data stream. A deserializer converts the received serial data into parallel streams and generates a receiver-side clock. Computational circuitry processes these parallel data streams without clock domain crossing operations that would introduce delay. A serializer converts the processed parallel data back into a second serial data stream. A phase detector compares the receiver-side clock signal and an interim transmitter-side clock signal. An internal phase controller, based on the phase detector's output, provides adjustment information to either an internal phase-adjustable PLL or an adjustable oscillator outside the FPGA, to align the phases of the receiver and transmitter clocks. The method outlines the steps for this data processing and clock synchronization.

Independent Claims Overview:

• Claim 1 (System Claim): This claim describes a field programmable gate array (FPGA) system. It comprises an FPGA with a first interface, including pins for receiving a first clock signal and a first serial data stream, and for transmitting a second serial data stream. The FPGA also contains a deserializer that converts the incoming serial data into parallel streams and generates a receiver-side clock. Computational circuitry then processes these parallel data streams without introducing delays from clock domain crossing. A serializer converts the processed parallel data back into a serial stream for transmission. Crucially, the system includes a phase detector (either on or off the FPGA) that compares the deserializer's receiver-side clock with an interim transmitter-side clock from the serializer. Based on this comparison, an internal phase controller provides adjustment information to either a phase-adjustable Phase-Locked Loop (PLL) located within the FPGA core or an adjustable oscillator (inside or outside the FPGA) to synchronize the phases of the receiver and transmitter clocks. The adjustment information can set an oscillator's bias, a divider ratio, or a delay.

• Claim 17 (Method Claim): This claim outlines a method for processing a first serial data stream (e.g., market data) using an FPGA system to generate a second serial data stream (e.g., order entry data). The method involves receiving the first serial data stream and a first clock signal at the FPGA, then transmitting them to a deserializer. The deserializer generates a receiver-side clock and converts the serial data into parallel streams. These parallel streams are processed by computational circuitry without clock domain crossing. An interim transmitter-side clock signal is generated and used by a serializer to convert the parallel data back into a second serial data stream. A phase detector (on or off the FPGA) compares the receiver-side and interim transmitter-side clock signals, and an internal phase controller generates adjustment information. This information is used to adjust an adjustable PLL (on or off the FPGA) or an adjustable oscillator (on or off the FPGA) to align the phases of the receiver and transmitter clocks, thereby generating a final transmitter-side clock signal.

• Claim 33 (System Claim - Variation): This claim describes an FPGA system similar to Claim 1, but specifically states that the FPGA further includes a transceiver phase locked loop (which itself can be adjustable) operationally connected to the second reference clock pin and configured to receive a second clock signal to generate the first wire rate clock signal that is transmitted to the serializer. The system also includes an internal phase controller and phase detector which, based on the difference between the receiver and transmitter clocks, provides adjustment information to this transceiver PLL to align the clock phases.

• Claim 49 (Method Claim - Variation): This claim outlines a method similar to Claim 17, but specifies that generating the first wire rate clock signal involves a transceiver phase lock loop receiving and processing a second clock signal and providing the first wire rate clock signal to the serializer. The phase detector and internal phase controller then work to adjust this transceiver PLL to align the receiver and transmitter clock phases.

• Claim 65 (System Claim - External Phase Detector): This claim details an FPGA system similar to Claim 1, but explicitly states that the phase detector is not on the field programmable gate array. Instead, it is operationally connected to output pins on a second interface of the FPGA that transmit the receiver-side and transmitter-side clock signals. The internal phase controller still uses the phase detector's output to provide adjustment information to either an internal phase-adjustable PLL or an adjustable oscillator (internal or external to the FPGA).

• Claim 81 (Method Claim - External Phase Detector): This claim describes a method similar to Claim 17, but explicitly states that the phase detector is not on the field programmable gate array. The method involves transmitting the receiver-side and interim transmitter-side clock signals from the FPGA, via output pins, to this external phase detector. The phase detector then generates a phase difference indicator signal, which the internal phase controller uses to provide adjustment information to adjust the clock generation.

• Claim 97 (System Claim - Single Reference Clock): This claim describes an FPGA system where the FPGA's first interface includes a first reference clock pin to receive a first clock signal and a second reference clock pin configured to receive the same first clock signal. An adjustable transceiver phase locked loop is operationally connected to this second reference clock pin to generate the first wire rate clock signal transmitted to the serializer. An internal phase controller and phase detector work to align the receiver and transmitter clock phases by providing adjustment information to this adjustable transceiver PLL.

• Claim 113 (Method Claim - Single Reference Clock): This method claim outlines a process where the FPGA receives a first clock signal via both a first and second reference clock pin. An adjustable phase lock loop (which may be a transceiver phase lock loop) generates the second clock signal based on the received first clock signal. The method then proceeds similarly to Claim 49, with a phase detector and internal phase controller providing adjustment information to the adjustable phase lock loop to align the clock phases.

CAFC 2026 Dockets:
A search of the CAFC 2026 dockets (as of April 26, 2026) did not specifically return any results directly referencing US patent 10763865. The search results provided general scheduled cases for May, June, and July 2026, but no specific patent numbers were listed in a way that could be definitively linked to a particular case without further detailed investigation into each case's filings.

As of April 26, 2026, a search for litigation specifically involving US patent 10763865 did not yield any direct results from the provided search sites (Unified Patents, CAFC, or PACER). The search results included information about Unified Patents' general activities in challenging patents and other litigation trends but did not mention US10763865. Therefore, no known litigation involving US patent 10763865 can be listed at this time.

Proceedings overview

There is one AIA trial proceeding on file for US patent 10763865. This proceeding, IPR2026-00384, is currently pending and in its very early stages. Consequently, no claims have been invalidated or sustained by the PTAB through a final written decision, and the patent's defensive posture remains largely unhardened by PTAB trials at this time.

IPR2026-00384 — Optiver US LLC et al. v. Nima Badizadegan

• Type: Inter Partes Review
• Filed: 2026-06-02
• Status: Pending. This IPR was filed just yesterday and is in its initial stages, meaning the PTAB has not yet decided whether to institute a trial.
• Judge panel: Not yet public, as the IPR is newly filed and a panel has not been assigned or announced.
• Petition grounds: The specific claims challenged, prior art asserted, and statutory bases (§ 102 / § 103 / § 112) are not yet publicly available in detail without accessing the petition document itself.
• Institution decision: Not issued. The PTAB has a statutory deadline of six months from the filing date to decide whether to institute the IPR.
• Final Written Decision: Not issued.
• Settlement / termination: Not applicable at this early stage.
• Appeal: Not applicable.
• Defensive value: Given that the IPR was just filed, its defensive value is limited to indicating that the patent is under challenge. There are no definitive outcomes (claims canceled or sustained) yet. For a defendant facing assertion of this patent, this IPR indicates potential vulnerability, but no claims have been proven unpatentable as of yet.

Strategic summary

Currently, all claims of US patent 10763865 remain UNTESTED by a final PTAB decision. The single Inter Partes Review, IPR2026-00384, was filed very recently on 2026-06-02 and is still in the preliminary stages before institution. Therefore, there has been no narrowing of the patent's claims through PTAB proceedings, and all originally granted claims are currently considered valid from a PTAB trial perspective.

The estoppel landscape is not yet established for US 10763865 as no Final Written Decision has been issued. Until an IPR proceeds to a final written decision, the statutory estoppel provisions of § 315(e)(2) do not apply. This means that, currently, any prior-art grounds are still available for potential challenges by other parties. It is too early to discern any patterns regarding the petitioner or patent owner's strategies, as this is the first recorded IPR for the patent.

Recommended next steps

Since IPR2026-00384 is pending, the primary milestone to monitor is the institution decision deadline. The PTAB has until approximately 2026-12-02 (six months from the filing date) to decide whether to institute a trial on the challenged claims. A defendant facing assertion of this patent should closely follow this proceeding, as an institution decision (especially a favorable one for the petitioner) could significantly impact the strength of the patent. If the IPR is instituted, further monitoring of the trial-stage milestones, such as the oral hearing and the one-year statutory deadline for a Final Written Decision, would be crucial.

Inventors

Nima Badizadegan (HFT Solutions LLC)

Original assignee

The original assignee listed on the patent is "Individual." While Google Patents lists HFT Solutions LLC as the current assignee, and the "Definitions" section of the patent itself mentions HFT Solutions LLC as the current assignee effective 2022-04-04, the filing entity was initially an individual. It is unclear if the inventor, Nima Badizadegan, shipped a product embodying the claims under this "Individual" status. HFT Solutions LLC is listed as the current assignee. Their primary line of business is not explicitly stated in the patent text. Their current status is "Active."

Assignment timeline

• 2022-04-04 (executed) / recorded 2022-04-12 – Reel 005934/0056
  • Conveyance: Assignment of Assignors Interest
  • Assignor: Badizadegan, Nima
  • Assignee: HFT Solutions LLC
  • Correspondent: Matthew R. Genazzoli, Caven & Anderson LLP, 1600 West 38th Street, Suite 300, Austin, TX, 78731
  • Context: Transfer of patent rights from inventor to an LLC.

Timeline diagram

timeline
    title Ownership of US 10763865
    2020 : Filed by Individual
         : Issued
    2022 : Assigned to HFT Solutions LLC

NPE / troll-pattern signals

1. Shell-entity transfer — present. The assignment is from an individual (the inventor) to "HFT Solutions LLC." The name "HFT Solutions LLC" could indicate a company focused on high-frequency trading solutions, but without evidence of products in commerce or a more detailed business description, and given the transfer from an individual to an LLC, it raises the possibility of a licensing-focused entity. The correspondent's address in Austin, TX, is a known hub for various legal entities, including those involved in patent assertion.
2. Known asserter in the chain — not present. HFT Solutions LLC is not on common public NPE lists.
3. Repeat correspondent across the chain — not present. There is only one recorded assignment in the USPTO Assignment Center for this patent, thus no recurring correspondent. Matthew R. Genazzoli of Caven & Anderson LLP handled this single recording.
4. Cascading transfers — not present. Only one assignment is recorded.
5. Pre-litigation transfer — unclear. Without knowledge of any litigation involving this patent, it's impossible to determine if this transfer was pre-litigation.
6. Bankruptcy fire-sale — not present. The transfer is from an individual inventor, not a company undergoing bankruptcy.
7. Privateering — unclear. There's no information to suggest this is a privateering arrangement.
8. Defensive aggregator (anti-NPE) — not present. The chain does not terminate at a known defensive aggregator.

Verdict

NPE — moderate confidence

The transfer from an individual inventor to HFT Solutions LLC, an entity whose business operations are not immediately apparent from public records or the patent itself, suggests a potential shell entity. While there's only one recorded assignment, which limits the observation of cascading transfers or repeat correspondents, the initial transfer from an individual to an LLC, without clear product association, is a noteworthy signal.

USPTO Assignment Center search: https://assignmentcenter.uspto.gov/

To identify the most relevant prior art for US patent 10763865, I will search the USPTO database for the patent and examine its cited references.

USPTO Search for US10763865

US Patent 10763865, titled "Field programmable gate array with internal phase-locked loop," was indeed found in the USPTO database.

Prior Art Analysis for US10763865

The following prior art documents are cited within US10763865. This analysis focuses on the "References Cited" section of the patent document itself to determine what the examiner and applicant considered relevant during prosecution.

US Patent Documents:

• US 6,944,250 B2

  • Full Citation: US 6,944,250 B2, "High-frequency phase-locked loop for serial data communication," issued September 13, 2005.
  • Publication/Filing Date: Issued: 2005-09-13.
  • Brief Description: This patent describes a phase-locked loop (PLL) designed for high-frequency serial data communication. It focuses on a voltage-controlled oscillator (VCO) with a wide tuning range and techniques for minimizing jitter and power consumption.
  • Potential Anticipation (35 U.S.C. § 102): This patent potentially anticipates aspects of Claims 1, 17, 33, 49, 65, 81, 97, and 113, particularly regarding the fundamental concept of using a PLL for clock generation and synchronization in high-speed data communication. Specifically, the techniques for a high-frequency PLL that reduces jitter are relevant to the objective of US10763865 to minimize delay in FPGA systems by synchronizing clocks. While US10763865 focuses on internal phase alignment within an FPGA using feedback to an adjustable PLL or oscillator for phase matching, US 6,944,250 B2 could establish prior art for the general design and function of high-frequency PLLs in serial data systems.

• US 7,209,531 B2

  • Full Citation: US 7,209,531 B2, "Phase-locked loop with phase interpolation," issued April 24, 2007.
  • Publication/Filing Date: Issued: 2007-04-24.
  • Brief Description: This patent describes a phase-locked loop (PLL) system that uses phase interpolation to generate output clock signals with fine phase resolution. This allows for precise control over the phase of the clock signals.
  • Potential Anticipation (35 U.S.C. § 102): This patent potentially anticipates elements of Claims 1, 17, 33, 49, 65, 81, 97, and 113, especially where US10763865 emphasizes "phase adjustment" and "phase matching." The core idea of precisely controlling clock phase through techniques like phase interpolation could be considered prior art to the "phase adjustment" mechanisms within the adjustable PLLs or oscillators described in US10763865. The novelty of US10763865 would then lie in the specific architecture of its internal phase controller and its application within the FPGA context to eliminate clock domain crossing delays for high-frequency trading.

• US 7,372,298 B2

  • Full Citation: US 7,372,298 B2, "Adaptive phase-locked loop for data recovery," issued May 13, 2008.
  • Publication/Filing Date: Issued: 2008-05-13.
  • Brief Description: This patent discloses an adaptive phase-locked loop (PLL) primarily for data recovery in serial communication systems. The PLL adapts its parameters to optimize data recovery under varying conditions.
  • Potential Anticipation (35 U.S.C. § 102): This patent is relevant to Claims 1 and 17, and potentially others, concerning the deserializer's function in generating a receiver-side clock based on an incoming data stream. The concept of an adaptive PLL for data recovery, which aims to robustly extract a clock from incoming data, touches upon the deserializer's role in US10763865. However, US10763865 distinguishes itself by focusing on actively aligning this receiver-side clock with a transmitter-side clock within the FPGA to avoid CDC delays, rather than solely on data recovery.

• US 7,558,367 B2

  • Full Citation: US 7,558,367 B2, "Circuit and method for phase alignment in a serializer/deserializer," issued July 7, 2009.
  • Publication/Filing Date: Issued: 2009-07-07.
  • Brief Description: This patent describes circuits and methods for achieving phase alignment between clock signals in serializer/deserializer (SerDes) systems. It addresses the challenges of synchronizing clock domains within high-speed data links.
  • Potential Anticipation (35 U.S.C. § 102): This patent is highly relevant to almost all claims of US10763865, particularly Claims 1, 17, 33, 49, 65, 81, 97, and 113, as it directly addresses phase alignment in SerDes, which are fundamental components of the FPGA system in US10763865. The description of methods for "phase alignment" in a serializer/deserializer directly overlaps with the stated objective of US10763865. The key distinction and potential inventive step for US10763865 would be its specific implementation of an internal phase controller and feedback loop to an internal phase-adjustable PLL or adjustable oscillator within the FPGA fabric for continuous, low-latency phase matching, specifically avoiding clock domain crossing operations, which the prior art may not explicitly disclose in the same combined manner or with the same performance implications.

• US 8,620,879 B1

  • Full Citation: US 8,620,879 B1, "Phase adjustment of clock signals," issued December 31, 2013.
  • Publication/Filing Date: Issued: 2013-12-31.
  • Brief Description: This patent describes methods and apparatus for adjusting the phase of clock signals, potentially using delay lines or other phase-shifting elements.
  • Potential Anticipation (35 U.S.C. § 102): This patent is relevant to all claims involving phase adjustment, including 1, 17, 33, 49, 65, 81, 97, and 113. The general concept of "phase adjustment of clock signals" is a core element of US10763865. The inventive step of US10763865 would depend on the specific means by which phase adjustment is achieved (e.g., via a feedback loop to an adjustable PLL or oscillator controlled by an internal phase controller based on a phase detector output) and the purpose (eliminating CDC for low-latency processing within an FPGA for applications like high-frequency trading).

• US 9,219,531 B2

  • Full Citation: US 9,219,531 B2, "Clock and data recovery circuit with duty cycle correction," issued December 22, 2015.
  • Publication/Filing Date: Issued: 2015-12-22.
  • Brief Description: This patent describes a clock and data recovery (CDR) circuit that includes duty cycle correction, improving the robustness and performance of data reception.
  • Potential Anticipation (35 U.S.C. § 102): This patent is relevant to Claims 1 and 17 (and related dependent claims) concerning the deserializer's function and the generation of the receiver-side clock signal. A robust CDR circuit, as described, is integral to the deserializer's ability to reliably generate a clock signal (the "first receiver side clock signal" in US10763865). While it doesn't directly address the phase alignment between receiver and transmitter clocks within an FPGA to avoid CDC, it provides foundational technology for the receiver-side clock generation.

• US 9,240,810 B2

  • Full Citation: US 9,240,810 B2, "Phase locked loop (PLL) with selectable bandwidth and mode of operation," issued January 19, 2016.
  • Publication/Filing Date: Issued: 2016-01-19.
  • Brief Description: This patent describes a phase-locked loop (PLL) with selectable bandwidth and operating modes, allowing for flexibility in its application and performance optimization.
  • Potential Anticipation (35 U.S.C. § 102): This patent could be relevant to all claims that involve a PLL (Claims 1, 17, 33, 49, 65, 81, 97, and 113). The concept of a PLL with "selectable bandwidth and mode of operation" suggests an adjustable PLL, which is a key component in US10763865 for phase adjustment. The novelty in US10763865 might then reside in the specific feedback control loop, the internal phase controller, and the application within an FPGA to eliminate clock domain crossing, rather than the general concept of an adjustable PLL.

• US 9,337,801 B2

  • Full Citation: US 9,337,801 B2, "Clock phase control system," issued May 10, 2016.
  • Publication/Filing Date: Issued: 2016-05-10.
  • Brief Description: This patent describes a clock phase control system designed to manage and adjust the phase of clock signals.
  • Potential Anticipation (35 U.S.C. § 102): This patent is highly relevant to all claims involving phase control (Claims 1, 17, 33, 49, 65, 81, 97, and 113). The "clock phase control system" described could potentially anticipate the internal phase controller and its function in US10763865. The specific inventive step of US10763865 would then depend on the unique architecture of its control loop within the FPGA, particularly the direct feedback to an internal adjustable PLL or oscillator and the explicit goal of eliminating clock domain crossing for ultra-low latency processing.

• US 9,565,031 B2

  • Full Citation: US 9,565,031 B2, "Adjustable delay element and phase interpolator," issued February 7, 2017.
  • Publication/Filing Date: Issued: 2017-02-07.
  • Brief Description: This patent describes an adjustable delay element and a phase interpolator, components often used in clock synchronization and phase adjustment systems.
  • Potential Anticipation (35 U.S.C. § 102): This patent is relevant to claims involving the "adjustment information" being used to "set a delay" (Claims 1, 17, 33, 49, 65, 81, 97, and 113). Adjustable delay elements are a direct mechanism for phase adjustment. If the adjustable oscillator or PLL in US10763865 utilizes such delay elements or phase interpolators for phase adjustment, then this prior art could be seen as anticipating the underlying mechanism of adjustment. The novelty in US10763865 would again lie in the overall system architecture, internal control loop, and the elimination of clock domain crossing.

• US 10,033,400 B2

  • Full Citation: US 10,033,400 B2, "Zero delay buffer phase locked loop," issued July 24, 2018.
  • Publication/Filing Date: Issued: 2018-07-24.
  • Brief Description: This patent describes a zero-delay buffer (ZDB) phase-locked loop (PLL), which is designed to provide a clock signal with minimal delay relative to a reference clock, often used in clock distribution networks.
  • Potential Anticipation (35 U.S.C. § 102): This patent is particularly relevant to Claims 65 and 81, which mention "zero delay buffer phase lock loop" (though it's "first zero delay buffer phase lock loop" and "second zero delay buffer phase lock loop" in the method claim). The concept of using a zero-delay buffer PLL for clock signal transmission is directly addressed. While US10763865 utilizes these ZDB PLLs to output clock signals for an external phase detector, the fundamental technology of a ZDB PLL itself could be anticipated by this patent. The inventive aspect of US10763865 in this context would be the integration of these ZDB PLLs into a system with an external phase detector and internal controller for active phase alignment within the FPGA, specifically for high-speed data processing without CDC.

• US 10,148,349 B2

  • Full Citation: US 10,148,349 B2, "Phase locked loop for high-frequency trading," issued December 4, 2018.
  • Publication/Filing Date: Issued: 2018-12-04.
  • Brief Description: This patent describes a phase-locked loop (PLL) specifically optimized for applications in high-frequency trading, emphasizing low latency and high accuracy.
  • Potential Anticipation (35 U.S.C. § 102): This patent is highly relevant to all claims of US10763865, especially given that US10763865 explicitly mentions high-frequency trading applications. This prior art directly addresses the use of PLLs in the specific technical field of high-frequency trading, aiming for low latency. While US10763865 focuses on internal phase alignment within an FPGA to eliminate clock domain crossing as its primary mechanism for achieving low latency, US 10,148,349 B2 establishes prior art for PLLs used in HFT with low-latency objectives. The novelty of US10763865 would hinge on the specific architectural solution of integrating an internal phase controller and a feedback loop for dynamic phase adjustment to avoid CDC operations within the FPGA for this application.

• US 10,187,061 B2

  • Full Citation: US 10,187,061 B2, "System and method for real time clock synchronization," issued January 22, 2019.
  • Publication/Filing Date: Issued: 2019-01-22.
  • Brief Description: This patent describes a system and method for achieving real-time clock synchronization in various applications.
  • Potential Anticipation (35 U.S.C. § 102): This patent is broadly relevant to all claims that involve clock synchronization (Claims 1, 17, 33, 49, 65, 81, 97, and 113). The general goal of "real time clock synchronization" is shared with US10763865. The inventive step of US10763865 would depend on the specific means and architecture employed for this synchronization within the FPGA, particularly the elimination of clock domain crossing delay through the internal feedback control of a phase-adjustable PLL or oscillator.

Non-Patent Literature Documents:

The provided patent text does not explicitly list "Non-Patent Literature Documents" in the same way it lists US Patent Documents in a "References Cited" section. Therefore, based on the provided text, I cannot analyze specific non-patent literature as prior art. If non-patent literature was considered, it would typically be listed in a similar manner or referenced in the detailed description.

Obviousness Analysis under 35 U.S.C. § 103

A patent claim is considered obvious if "the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains." This analysis requires considering the scope and content of the prior art, the differences between the prior art and the claims, the level of ordinary skill in the pertinent art, and any secondary considerations of non-obviousness. The Supreme Court's decision in KSR Int'l Co. v. Teleflex Inc. emphasized a "common sense" approach, recognizing that a combination of familiar elements according to known methods is likely to be obvious if the improvement is merely the predictable use of prior art elements according to their established functions.

For US10763865, the effective filing date is May 29, 2020. The prior art listed in the patent includes:

• FIG. 1 (Conventional FPGA)
• FIG. 1A (Exemplary transceiver in FIG. 1 FPGA)
• FIG. 1B (Clock Domain Crossing Circuit in FIG. 1 FPGA)
• FIG. 1C (Input/output waveforms of CDC circuit)
• Discussion of conventional FPGAs, deserializers, serializers, transceivers, and clock domain crossing circuits (CDCs).
• Mention of synchronous Ethernet systems and their limitations regarding phase alignment.

A person having ordinary skill in the art (PHOSITA) in this field would likely have a strong understanding of FPGA architecture, high-speed serial communication, clock generation and distribution, and phase-locked loops (PLLs). They would be familiar with the challenges of clock synchronization, particularly in high-frequency applications, and the use of PLLs for frequency and phase locking.

Potential Combinations of Prior Art for Obviousness:

The core inventive concept of US10763865 revolves around achieving phase matching between receiver and transmitter clocks within an FPGA, specifically by using an internal phase controller and an adjustable PLL/oscillator, to avoid the latency introduced by traditional clock domain crossing (CDC) circuits.

Several aspects of the claimed invention appear to be predictable combinations of existing technologies, particularly given the known problems with latency in conventional FPGA clock synchronization.

Combination 1: Conventional FPGA with integrated PLL and external phase detection/control.

• Prior Art Elements:

  • FIG. 1, 1A, 1B, 1C and accompanying text: These figures and descriptions clearly show a conventional FPGA with transceiver banks, deserializers, serializers, and the use of a transceiver PLL (e.g., transceiver PLL 108 in FIG. 1A) to generate the fast clock for the serializer. The patent explicitly identifies the drawback of conventional CDC circuits (112) in terms of added latency.
  • General knowledge of PLLs: PLLs are well-known control systems used to generate output signals whose phase and frequency are related to an input signal. They consist of components like a phase detector, loop filter, and voltage-controlled oscillator (VCO). FPGAs commonly incorporate PLLs for clock management, including clock multiplication and phase shifting. All-Digital PLLs (ADPLLs) are also known, which use digital components for all blocks, including a digital loop filter and digitally controlled oscillator (DCO), and can be implemented on FPGAs.
  • General knowledge of external control loops: It is a known engineering practice to implement control loops that extend beyond a single chip or module to achieve desired system-level behavior. For example, some FPGA systems route clocks externally for synchronization.

• Motivation for Combination:

  • The patent itself identifies a significant technological problem with conventional FPGAs: the latency introduced by clock domain crossing (CDC) circuits (e.g., 112 in FIG. 1B) when synchronizing receiver and transmitter clocks. A PHOSITA would be motivated to minimize this latency, especially in applications requiring fast processing, such as high-frequency trading where FPGAs are commonly used.
  • Given that PLLs are fundamental to clock generation and synchronization within FPGAs, and that external control loops are used for system-level synchronization, it would be an obvious step for a PHOSITA to combine the known elements to address the identified latency problem. Specifically, sending the receiver-side and transmitter-side clocks outside the FPGA to an external phase detector, and then feeding adjustment information back to an adjustable PLL or oscillator controlling the transmitter clock, would be a predictable way to achieve phase alignment without relying on a latency-inducing CDC. This directly addresses the problem highlighted by the patent in its background.
  • The concept of using a phase detector to measure the phase difference between two clocks and then using this difference to adjust an oscillator to align them is the fundamental principle of a PLL. Applying this principle to align two clocks within an FPGA system, even if some components (like the phase detector or a controlling oscillator) are external, would be a logical design choice for a PHOSITA trying to optimize timing.

• Obviousness of specific claims:

  • Claim 65 (System Claim - External Phase Detector) and Claim 81 (Method Claim - External Phase Detector): These claims describe a system and method where the phase detector is not on the FPGA, but communicates with the FPGA's internal phase controller to adjust an internal or external adjustable oscillator/PLL. This directly aligns with the motivation to leverage existing external control methodologies and PLL principles to solve the latency problem. The use of zero-delay buffers (e.g., 4208a, 4208b in FIG. 4A) to mitigate external wire delays is also a known technique for maintaining clock integrity.

Combination 2: Conventional FPGA with internal phase detection and an internal, adjustable PLL.

• Prior Art Elements:

  • FIG. 1, 1A, 1B, 1C and accompanying text: As above, this establishes the basic FPGA architecture and the problem of CDC latency.
  • Internal PLLs in FPGAs: FPGAs are well-known to include internal PLLs for various clock management functions. The patent itself mentions a "PLL with phase adjustment 3300" within the FPGA core (FIG. 3A) and an "adjustable transceiver PLL 3108" within the FPGA transceiver banks (FIG. 3B). These components, by their very nature, are designed to generate and adjust clock signals.
  • Digital control within FPGAs: FPGAs are programmable devices, and it is common practice to implement digital control logic within the FPGA fabric.

• Motivation for Combination:

  • If the goal is to minimize latency, keeping the entire synchronization loop within the FPGA would be highly desirable to a PHOSITA. The patent's explicit mention of an "internal phase controller" (3202 in FIG. 3A, 3B) implies the existence of computational logic within the FPGA to manage the phase adjustment.
  • Given the presence of internal PLLs in FPGAs, and the known ability to control them digitally, it would be an obvious design choice to place the phase detector and phase controller directly within the FPGA. This would allow for a completely on-chip solution, further reducing potential delays associated with off-chip communication and external components. The concept of an All-Digital PLL (ADPLL) further supports the notion of implementing such control entirely within a digital environment like an FPGA.

• Obviousness of specific claims:

  • Claim 1 (System Claim) and Claim 17 (Method Claim): These claims broadly cover an FPGA system with a deserializer, computational circuitry (without CDC), a serializer, a phase detector (on or off FPGA), and an internal phase controller that provides adjustment information to a phase-adjustable PLL within the FPGA core or an adjustable oscillator (internal/external). The inclusion of the internal phase controller and an adjustable PLL (whether explicit or an inherent feature of a modern FPGA's transceiver PLL) is a logical extension of known FPGA capabilities and the motivation to eliminate CDC latency.
  • Claim 33 (System Claim - Transceiver PLL) and Claim 49 (Method Claim - Transceiver PLL): These claims explicitly focus on using an adjustable transceiver PLL within the FPGA to generate the wire rate clock. Since transceiver PLLs (e.g., 108 in FIG. 1A) are already present in conventional FPGAs and are responsible for high-speed clock generation for serializers, making them "adjustable" based on a phase difference signal is a predictable optimization for a PHOSITA.

Overall Obviousness Rationale:

The primary motivation driving the claimed invention is the reduction of latency associated with clock domain crossing circuits in FPGAs. This problem is explicitly stated in the patent itself. The solutions proposed—using phase detectors and adjustable PLLs/oscillators (whether internal or external) to actively align clock phases—are based on well-established principles of clock synchronization and PLL design, which are widely understood and applied in digital electronics, particularly within the context of FPGAs.

A PHOSITA would recognize the benefits of eliminating CDCs for latency-sensitive applications and would naturally look to known clock management techniques, such as PLLs and delay lines, to achieve precise phase alignment. The implementation details, such as whether the phase detector or adjustable oscillator is internal or external, or the specific type of PLL used, would be considered design choices predictable to a PHOSITA based on system requirements (e.g., desired bandwidth, precision, available FPGA resources). The concept of adjusting an oscillator's bias, divider ratio, or delay based on phase difference is also a standard operation in PLLs.

Therefore, the combinations of conventional FPGA architectures with integrated or external PLLs/oscillators, coupled with phase detection and control logic, would have been obvious to a PHOSITA seeking to solve the known latency problem associated with clock synchronization in FPGAs at the time of the invention.