US 10755750

I'll search for information on this specific patent number, including any CAFC 2026 docket activity.

Let me run a couple more targeted searches to confirm the CAFC docket status and any assignment changes.

US Patent 10,755,750 — Summary

Note on methodology: I searched for the specific number 10755750 and for related CAFC/Micron 2026 docket activity. I found the patent's full text via Google Patents and Justia, both of which corroborate the details below. I did not find any 2026 CAFC docket, appeal, or IPR involving US 10,755,750 specifically. The 2026 Federal Circuit Micron cases that exist (e.g., Netlist, Inc. v. Micron Technology, Inc., Micron Technology Inc. v. Longhorn IP, LLC, and the YMTC–Micron disputes) concern other patent numbers, not the '750 patent. I am flagging that explicitly rather than implying a case exists.

Bibliographic data

Abstract (verbatim)

"Disclosed is an improved load switch driver for Power Management Integrated Circuit (PMIC) devices. In one embodiment, a PMIC is disclosed comprising a gate driver, the gate driver connected to the gate of a switch; an operation frequency generator connected to the gate driver and configured to supply a periodic voltage to the gate driver; and a voltage sensor, the voltage sensor connected to the operation frequency generator and the source of the switch, the voltage sensor configured to monitor a drain-source voltage of the switch and lower the frequency of the operation frequency generator to a second frequency in response to detecting a collapse of the drain-source voltage."

Plain-language overview of the independent claims

• Claim 1 (circuit). A circuit containing a switch plus a voltage sensor. The sensor watches the switch's drain-to-source voltage (V_DS) and, when it detects that V_DS has collapsed, lowers the operation frequency of the gate voltage to a second (lower) frequency. In the disclosed embodiment, the "collapse" of V_DS signals that the FET is fully saturated/turned on, so the driver can drop from a fast-charging frequency to a low "trickle" frequency. Ranges disclosed elsewhere in the claims: ~200–400 kHz before, ~8.5–12 kHz after.

• Claim 9 (system). A system comprising a load switch driver and one or more memory devices coupled to that driver through at least one switch. The load switch driver is configured to monitor the switch's V_DS and lower the frequency of an operation frequency generator to a second frequency in response to detecting a collapse of V_DS. (Dependent claims 10–12 add second/third load switch drivers tied to a DRAM device and an ASIC device; claim 13 recites the internal gate driver / operation frequency generator / voltage sensor architecture.)

• Claim 16 (method). A method with three steps: (1) monitor the drain-source voltage of a switch; (2) determine that V_DS has collapsed; and (3) supply a gate voltage to the gate of the switch at a second frequency in response to that determination. (Dependent claims 17–20 add the ~200–400 kHz turn-on frequency prior to monitoring, the ~8.5–12 kHz second frequency, and two alternative collapse-detection techniques — comparing V_DS to a known breakdown voltage, or monitoring instantaneous changes in V_DS.)

Technical gist

The patent addresses power consumed by PMIC load-switch drivers in memory systems (e.g., SSDs). Conventional drivers continuously charge the FET gate at a high frequency, which wastes power — especially in sleep/low-power states. The invention runs the gate driver at a high frequency (200–400 kHz) only long enough to turn the FET on quickly, uses a voltage sensor to detect V_DS collapse (indicating full saturation), then drops the operation-frequency-generator frequency to a low maintenance frequency (8.5–12 kHz) to hold the gate charge. Claim 6 also recites the broader PMIC context (voltage regulator(s) and sequencer(s)).

A note on internal inconsistencies (uncertainty)

The specification's narrative description of V_DS behavior during turn-on is non-standard and somewhat internally inconsistent — it states that "V_DS increase[s] during charging of the gate (i.e., the ohmic region)" and that "once saturated, V_DS continues to increase until reaching the switch's breakdown voltage (i.e., when V_DS collapses)." That phrasing does not neatly match textbook MOSFET turn-on where V_DS decreases as the device enters the ohmic region. I am reporting the text as written; the claims themselves do not depend on this description, and I have no authoritative extrinsic evidence resolving it.

Sources

• Google Patents, US10755750B2: https://patents.google.com/patent/US10755750/en
• Justia Patents (claims text): https://patents.justia.com/patent/10755750
• Related family: US10504562B2 (parent), US11024345B2 (child); pre-grant publication US20200058331A1

If a CAFC appeal or IPR for this specific patent number does exist, I could not locate it in the sources searched — that finding should be treated as "not found," not as confirmation that no such proceeding exists.

I'll research litigation involving US patent 10755750 across patent litigation databases and court records.

Let me search more targeted sources for litigation involving this specific patent.

Let me verify with additional targeted searches, including CourtListener and the patent's litigation/assignment records.

Summary of Findings

Based on my searches, I found no known litigation — district court, ITC, or PTAB — involving U.S. Patent No. 10,755,750 (the "'750 patent").

What I searched

• General web/patent-litigation searches for "10755750" combined with litigation, lawsuit, infringement, complaint (Unified Patents litigation portal references, CourtListener/PACER-adjacent results, Docket Alarm, Justia, and the USPTO/PTAB sources).
• Searches tying the patent's title ("Power management integrated circuit load switch driver with dynamic biasing") to litigation.
• Searches for the patent owner (Micron Technology) asserting the '750 patent.

What the results show (and don't show)

• Every litigation hit returned was for different patents — e.g., Netlist v. Micron (asserting Netlist's '366, '912, '417, '215, '506, '339, '918, '054, '060, '160 patents), Optis v. Apple ('332, '284, '557, '774, '833), ContentGuard v. Google, etc. None of these involve the '750 patent.
• The '750 patent is owned by Micron Technology, Inc. (original assignee; inventor Matthew David Rowley). Micron is an operating company that is predominantly a defendant in patent suits, not a serial assertor of its own PMIC patents. I found no record of Micron asserting the '750 patent against anyone.
• The '750 patent is part of a three-member family with US 10,504,562 (parent) and US 11,024,345 (child continuation). I also found no litigation records for the '750 patent in the sources reviewed.

Important caveats

• I could not complete a final round of verification searches (search-step limit was reached), so this is not an exhaustive negative. Litigation databases (Unified Patents portal, Docket Navigator, RPX Insight, Lex Machina) should be checked directly for a definitive result.
• Patent citations and cited-by records (e.g., the '750 patent being cited by Samsung and YMTC patents) are not litigation; I treated them as such.
• No ITC Section 337 investigation, no IPR/PGR, and no CAFC appeal referencing the '750 patent number appeared in my results.

Bottom line

If any litigation exists involving U.S. 10,755,750, I did not find it, and I cannot confirm any case (plaintiff, defendant, jurisdiction, case number, filing date, or status) on the basis of the sources reviewed. I recommend a direct query of the Unified Patents litigation portal (portal.unifiedpatents.com/litigation/caselist), Docket Navigator, and PACER/RECAP using the exact number 10,755,750 before treating the absence as conclusive. I am explicitly flagging that I do not know with high confidence that zero cases exist — only that none surfaced in this search.

I'll verify the structured "no proceedings" signal against live sources before writing anything up.

Those queries returned nothing relevant. Let me try more targeted searching against PTAB-specific sources.

Let me run a few final checks against PTAB-focused aggregators and Federal Circuit dockets.

Proceedings overview

Total AIA trial proceedings on file: 0 (zero active, zero claims invalidated, zero claims sustained, zero settled, zero institution denials). The USPTO Open Data Portal structured block returns no AIA trial proceedings for US 10755750 as of the most recent ingest, and my independent web checks of PTAB-facing sources surfaced no IPR, PGR, or CBM naming this patent, its parent US 10504562, or its continuation US 11024345. Bottom line for a defendant: there is no PTAB-based shortcut and no PTAB-based dead claim here. All 20 claims of US 10755750 are live, intact, unadjudicated, and carry no estoppel baggage — but that cuts both ways, because it also means nobody has ever stress-tested this patent, and a first-filed IPR is still available to you on a clean slate.

Because there is no proceeding to analyze claim-by-claim, the usual per-proceeding entries are replaced below by the negative findings and the evidentiary record that would have fed a proceeding.

No AIA trial proceedings on file (verified negative)

• Type: N/A — no IPR, PGR, or CBM identified.
• Filed: N/A.
• Status: Active (this is the patent's legal status from the structured data, not a proceeding status). Plain-English gloss: the patent is in force, maintenance fees current, with no post-grant challenge ever filed.
• Judge panel: N/A — no panel has ever been assigned.
• Petition grounds: N/A.
• Institution decision: N/A — no § 314/§ 324 decision on this patent exists.
• Final Written Decision: N/A — no FWD has issued, so no claim of this patent has ever been canceled or confirmed by the Board.
• Settlement / termination: N/A.
• Appeal: No Federal Circuit appeal exists regarding this patent's validity, because there is no Board decision to appeal. Note that I found no CAFC docket tying US 10755750 or its family to an appeal.
• Defensive value: A defendant cannot rely on a canceled-claim argument, and the patent owner cannot rely on a PTAB win to argue "hardened claims" either. This is an unlitigated, un-adjudicated patent. Your leverage is entirely in district court and in a de novo first IPR.

Important non-proceeding signals I did find (do not mistake these for challenges):

• The Google Patents "Cited By" list includes US 11,211,955 B2 and US 11,843,398 B2 (Samsung Electronics) and TWI 808420 B / US 11,901,034 B2 (Yangtze Memory). These are later patents that cite US 10755750 as background — they are not validity challenges. US 11,024,345 B2 in the same list is a Micron family member (continuation), not a third-party citation.
• US 10,504,562 B2 appears in the citation list; it is the parent application of this continuation, i.e., same family, same assignee (Micron Technology, Inc.), same priority date 2018-03-12. Not prior art against the patent owner by a petitioner.
• Prosecution-cited art worth mining for a future petition: US 2018/0159520 A1 and US 10,224,918 B2 (Infineon, "Active gate bias driver"), US 2018/0286465 A1 and US 10,121,519 B2 (Toshiba Memory, "Semiconductor device and control method thereof"), US 2017/0063223 A1 (Vidatronic, "Voltage regulator with dynamic charge pump control"), and US 2015/0365006 A1 (Fairchild Korea). These are the examiner's own references — a § 103 petition built on dynamic-bias/charge-pump-driver art is at least perceptible on this record.
• Legal status timeline, for docket hygiene: application filed 2019-10-23 (continuation); assignment to Micron recorded 2019-10-31; patent granted 2020-08-25; anticipated expiration 2038-03-12 (priority date 2018-03-12); 4th-year maintenance fee paid 2024-02-22. A separate continuation, US 17/001,548, issued as US 11,024,345 B2 on 2021-06-01 and was also granted.

Strategic summary

Claim status: all 20 claims UNTESTED. There is no PTAB record to narrow this patent. Independent claims 1 (circuit), 9 (system), and 16 (method) stand as issued, along with their dependents. Nothing about claim 1 has been construed by the Board; nothing in claims 2-8, 10-15, or 17-20 has been canceled or confirmed. That is materially different from the typical "hardened by two IPRs" or "gutted by IPR" posture — this patent has never been through the process at all. A defendant should treat the full claim set — including the frequency-corridor claims 4, 5, 14, 15, 17, and 18 (200-400 kHz before, 8.5-12 kHz after) — as fair game for challenge.

Estoppel landscape: essentially nil. Because no petitioner has ever filed an IPR or PGR against US 10755750, § 315(e)(2) estoppel has never attached to anyone. No party is barred from raising any prior-art ground, whether patent or printed publication, in district court or before the Board. The only estoppel-adjacent constraints on a new defendant are practical rather than statutory: (a) the 1-year § 315(b) bar runs from your service of a complaint alleging infringement, not from anyone else's activity; and (b) the Director's Fintiv-era discretionary-denial practice and the current § 325(d)/§ 314(a) framework will govern whether your petition gets instituted if you file it alongside live litigation. Because the examiner already considered the Infineon, Toshiba, Vidatronic, and Fairchild references, a petition that merely recycles them invites a § 325(d) discretionary denial — you'd want either materially new art or a strong "the examiner never actually grappled with this combination" showing.

Pattern signals. There is no pattern, because there is no proceeding. Specifically: no serial petitioner, no Unified Patents or other defensive aggregator in the chain, and no PTAB appeal history for this family. Two contextual points matter for pricing the risk. First, the patent owner is Micron Technology, Inc. — a large-entity operating company that is itself an aggressive and sophisticated PTAB participant in its own disputes (e.g., Micron's IPR filings in the Netlist and Palisade matters, including Micron Technology Inc. v. Palisade Technologies, LLP, IPR2025-01009). Expect competent, well-funded defense of this patent, not a troll's default. Second, PMIC/load-switch IP is generally held defensively by memory and controller makers; the absence of assertions against this family is consistent with a defensive portfolio rather than an assertion campaign. If you are holding a demand letter citing US 10755750, the most likely explanation is a licensing or cross-licensing maneuver rather than an established offensive track record — which changes negotiation posture more than it changes invalidity posture.

Recommended next steps

• Do not expect to find a pre-existing FWD to cite. There isn't one. If you are a defendant, do not represent to a court or an adversary that any claim of US 10755750 has been invalidated — it has not. Conversely, if you are the patent owner, do not represent that the claims are "PTAB-confirmed"; they have never been tested.
• If you want a PTAB track, you are the first mover. Verify the negative directly on the Board's own systems before filing, and docket your § 315(b) clock from the date you were served. Confirm current status via USPTO PTAB E2E / Patent Trial and Appeal Board End-to-End and the USPTO Patent Center record for application 16/661,904.
• Prior-art starting set: mine the prosecution citations listed above — US 2018/0159520 A1 and US 10,224,918 B2 (Infineon active gate bias driver), US 2018/0286465 A1 and US 10,121,519 B2 (Toshiba Memory), US 2017/0063223 A1 (Vidatronic dynamic charge pump control), US 2015/0365006 A1 (Fairchild Korea). Pair them with § 103 motivation evidence and be ready for a § 325(d) argument that these were already before the examiner.
• Link targets for diligence: Google Patents US10755750B2, the PTAB E2E portal, and CourtListener for any CAFC or district-court record. As of 2026-09-29 I found no CAFC opinion, no PTAB decision, and no litigation involving this patent.
• Caveat on scope of search. The ODP structured block is the canonical list and it reports zero proceedings. My web verification found nothing contradicting that, but public PTAB aggregators do not always index discretionary denials, pre-institution settlements, or very recently filed petitions promptly. If a proceeding was filed within the last few months, it may not yet be reflected anywhere I can reach. Treat "zero" as well-supported but confirm against PTAB E2E before relying on it in a filing.

I'll start by verifying the recorded assignment data against the primary sources before writing up.

Let me check for any litigation, NPE assertion activity, or additional recorded transfers involving this patent or its family.

Let me try to pull the actual assignment cover sheet for reel 050883/0494 to capture the correspondent of record.

I attempted to pull the recorded cover sheet for reel 050883/0494 directly, but the live searches returned no usable USPTO Assignment Center hit for this specific reel. The write-up below is grounded in the Google Patents legal-events record included with the authoritative patent text, and I flag explicitly where the record is silent.

Inventors

• Sole named inventor. No co-inventors on US 10,755,750 or on the parent US 10,504,562 / child US 11,024,345.
• Employer determination: The assignment instrument recorded at reel 050883/0494 names Rowley as assignor and Micron Technology, Inc. as assignee, with an execution/effective date of 2018-03-16 — four days after the parent application (US 15/919,020) was filed on 2018-03-12. An inventor-to-employer assignment executed concurrently with filing, plus a first-named-inventor address in Boise (Micron's HQ city), is the standard signature of an in-house employee invention. This is corroboration, not direct proof of employment status.
• Departure pattern: No data. I could not locate any record (USPTO, LinkedIn, SEC) confirming whether Rowley remained at Micron or departed within 12 months of filing. Per the operating rules I will not speculate; this signal is unclear / not determinable from available sources. No portfolio fire-sale followed, which reduces the diagnostic value of the question here.

Original assignee

Micron Technology, Inc. — a Delaware corporation, principal place of business 8000 South Federal Way, Boise, ID 83707-0006. Named as both original and current assignee on the face of US 10,755,750.

• Primary line of business: Operating semiconductor manufacturer — DRAM, NAND flash, and related memory subsystems. Micron is a publicly traded operating company (NASDAQ: MU), not a holding or licensing vehicle.
• Product embodying the claims: The patent is directed to a load-switch driver with dynamic biasing inside a PMIC used to manage power domains in a memory system (e.g., SSD). Micron ships PMIC-governed SSD and memory-module products in which such load-switch/power-domain isolation circuitry is a practical component. The claims (see claim 9: "a load switch driver … one or more memory devices coupled to the load switch driver via at least one switch") are drafted to a memory-system implementation, i.e., Micron's own product domain.
• Current status: Operating. Maintenance fee for the 4th year paid 2024-02-22 (large entity, event code M1551). Patent status "Active"; anticipated expiration 2038-03-12 (20 years from the 2018-03-12 priority date).

Assignment timeline

Recorded assignments for US 10,755,750 (application 16/661,904):

• 2018-03-16 (executed) / recorded 2019-10-31 — Reel 050883/0494
  • Conveyance: Assignment
  • Assignor: Rowley, Matthew David (sole inventor)
  • Assignee: Micron Technology, Inc. (Idaho)
  • Correspondent: Not exposed in the indexed Google Patents legal-events entry. The USPTO Assignment Center record (and the underlying cover-sheet PDF for reel 050883/0494) would name the recording agent; I could not retrieve it within this session, so I decline to name a correspondent. For context only, Micron's contemporaneous assignments in this era (e.g., reel 050718/0581, dated 2019-10-15) were recorded through Wells St. John P.S., Spokane, WA — but that is a different reel and I cannot attribute it to 050883/0494. Flagged as unverified.
  • Context: Standard employee invention assignment — inventor conveys title to his employer concurrent with the parent filing; recorded roughly 8 days after the continuation (16/661,904) was filed on 2019-10-23.

That is the only recorded assignment. There are no recorded security agreements, mergers, changes of name, licenses, releases, or corrections for this patent, and no post-issuance transfer of any kind. The only other PTO legal events are routine prosecution and maintenance entries:

• 2020-01-14 — Non-final action mailed
• 2020-04-27 — Notice of allowance mailed
• 2020-07-23 — Issue fee payment verified
• 2020-08-05 — Patent grant (STCF)
• 2024-02-22 — Maintenance fee paid, 4th year, large entity

Family context (same ownership chain, no separate assignments recorded): US 15/919,020 → US 10,504,562 B2 (parent, filed 2018-03-12); US 10,755,750 B2 (the instant continuation, filed 2019-10-23); US 17/001,548 → US 11,024,345 B2 (child continuation, filed 2020-08-24). All three are Active and carry Micron as assignee. No divisional or continuation was spun out to a separate entity.

Timeline diagram

timeline
    title Ownership of US 10755750
    2018 : Parent application filed by Micron
         : Rowley assigns to Micron 2018-03-16
    2019 : Continuation 16 661 904 filed
         : Assignment recorded Reel 050883 Frame 0494
    2020 : Patent US 10755750 grants
    2024 : 4th year maintenance fee paid

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. The patent never left Micron. There is no assignment to any "IP / Patents / Licensing / Holdings / Ventures" entity; the sole recorded conveyance (reel 050883/0494) runs to an operating manufacturer. No single-purpose LLC appears anywhere in the chain.

2. Known asserter in the chain — Not present. Neither current nor any prior assignee matches a public NPE list (Acacia, Marathon, IV, IPNav, Wi-LAN, Conversant/Mosaid, Vringo, Pendrell, Innovatio, Round Rock, etc.). Assignees of record are Rowley (individual inventor) and Micron Technology, Inc. only.

3. Repeat correspondent across the chain — Not determinable. With only one recorded assignment, recurrence cannot be assessed, and the correspondent of record for that single entry was not retrievable. No finding.

4. Cascading transfers — Not present. One assignment in the entire chain, executed 2018-03-16 and recorded 2019-10-31. There is no series of sub-24-month transfers and no shared-correspondent cluster of LLCs.

5. Pre-litigation transfer — Not present. No infringement suit naming US 10,755,750 (or its parent/child) was located in the searches performed, and there is no transfer within 6 months preceding any suit. The only transfer predates the patent's grant (2020-08-25) by 30 months.

6. Bankruptcy fire-sale — Not present. Micron has not filed Chapter 7/11; it remains an operating, publicly traded large entity paying maintenance fees (large-entity fee event 2024-02-22).

7. Privateering — Not present. No assignment to an NPE asserting on Micron's behalf; no SEC-filing or Patent Progress/EFF coverage of such a transfer surfaced.

8. Defensive aggregator (anti-NPE) — Not present. The chain does not terminate at RPX, AST, LOT, Unified, or OIN. Ownership rests with the original operating assignee.

Verdict

Insufficient data (no records beyond the original assignment).

The entire recorded chain is a single inventor-to-employer conveyance — executed 2018-03-16, recorded 2019-10-31 at reel 050883/0494, assignor Matthew David Rowley, assignee Micron Technology, Inc. There is no post-issuance transfer, no security interest, no merger, and no change of name. Every NPE/troll signal above is therefore not present or not determinable. This is the normal, benign pattern: the original operating assignee still owns the patent, consistent with the Google Patents face record listing Micron as both original and current assignee and with Micron's payment of the 4th-year maintenance fee (2024-02-22).

Caveat on completeness: I could not load the USPTO Assignment Center / legacy-assignment cover sheet for reel 050883/0494 in this session, so the correspondent of record for that one entry is unverified, and I cannot rule out an unindexed assignment that Google Patents' legal-events feed did not capture. Verify directly at the USPTO Assignment Center search (https://assignmentcenter.uspto.gov/) by entering patent number 10755750; the two-record family check (patents 10,504,562 and 11,024,345) should be run on the same query to confirm no sibling was separately encumbered.

I'll research the prior-art citations listed on US 10,755,750 via searching each reference.

Let me gather details on the remaining cited references.

Prior-Art Analysis — US 10,755,750 B2

Patent under review: US 10,755,750 B2, "Power management integrated circuit load switch driver with dynamic biasing"

• Inventor: Matthew David Rowley; Assignee: Micron Technology, Inc.
• Filing: 2019-10-23 (App. 16/661,904); Priority: 2018-03-12; Granted: 2020-08-25
• Because priority is 2018-03-12, the AIA (§ 102 as amended) governs novelty.

Methodology / scope caveat. I attempted direct searches on every listed citation. I obtained full documents for US7852125B2, US20170063223A1, US20180159520A1/US10224918B2, US20150365006A1, and the family members; for four references (US8199545B2, US20120170335A1, US20160156259A1, US20180046390A1) my searches returned no usable primary document before I exhausted my search budget. For those four I describe them from their titles/assignees and general knowledge and flag lower confidence. I did not fabricate disclosures I could not verify.

Key legal framing. Anticipation under § 102 requires a single reference to disclose each and every limitation of a claim, arranged as in the claim. The point of novelty in the '750 patent is the combination of (a) a voltage sensor monitoring the drain-source voltage (V_DS) of a switch and (b) lowering the operation frequency of the gate drive to a second frequency in response to detecting a collapse of V_DS (claims 1, 9, 16; ranges 200–400 kHz → 8.5–12 kHz per claims 5/14/17 and 4/15/18). None of the cited references discloses this combination, so none of the cited references anticipates the independent claims 1, 9, or 16, and therefore none anticipates the dependent claims either (a dependent claim incorporates all limitations of its parent). The references are, however, relevant as § 103 art against individual elements. This is consistent with the examiner having allowed the '750 claims over these references.

The 13 cited references (backward "Patent Citations")

Timing note. References 8–11 published after the 2018-03-12 priority date but were effectively filed before it, so they are available only as § 102(a)(2) art (US patent/application publications "effectively filed" before the critical date). References 1–7 published before the priority date and are § 102(a)(1) art. References 12–13 are the applicant's own earlier disclosure of the same invention (parent application US 15/919,020 / its pre-grant publication) and are not prior art against the '750 patent.

Per-reference detail

1. US7852125B2 — "Switching circuit arrangement"

• Citation/date: Koninklijke Philips Electronics N.V.; priority 2006-05-29, PCT filing 2007-05-14, granted 2010-12-14. Inventors Toni Lopez, Reinhold Elferich. (https://patents.google.com/patent/US7852125B2/en)
• Description: A synchronous-rectifier FET with gate-biasing circuitry (a series biasing diode plus an anti-parallel turn-on diode) that forces the gate voltage below threshold to mitigate reverse recovery and "gate bounce." A clamping switch connected between gate and source is controlled by the drain voltage; the gate path "becomes active as soon as the drain-to-source voltage ... starts rising," and the clamp turns on when V_DS rises above a threshold. The spec discusses V_DS rise during dv/dt transitions and avalanche breakdown levels. It is a dynamic gate-biasing reference, but its control variable is the rise of V_DS to hold the device OFF, not a collapse of V_DS to signal turn-ON.
• § 102 assessment (claims 1, 9, 16): Not anticipatory. It monitors V_DS (arguably the "voltage sensor ... monitor a drain-source voltage of the switch," relevant to claim 1's sensor element and to the claim 7/19 "compare to a known breakdown voltage" concept), but it discloses no operation frequency generator, no second frequency, and no lowering of a gate-drive frequency in response to V_DS collapse. The control action (clamping gate down) is the opposite of the patent's (hold gate charge / reduce frequency). Best characterized as § 103 background on V_DS-sensed gate biasing.

2. US8199545B2 — "Power-conversion control system including sliding mode controller and cycloconverter"

• Citation/date: Hamilton Sundstrand Corporation; filed 2009-05-05, granted 2012-06-12.
• Description (lower confidence): A power-conversion control system using a sliding-mode controller with a cycloconverter. This is a converter-control topology reference.
• § 102 assessment (claims 1, 9, 16): Not anticipatory. No teaching of a load switch, V_DS-collapse sensing, or reduction of a gate-drive operating frequency to a maintenance frequency. Relevant at most as generic power-conversion context.

3. US20120170335A1 — "Switch control circuit, converter using the same, and switch controlling method"

• Citation/date: Inventor Jae-Yong Lee; priority 2011-01-05; published 2012-07-05.
• Description (medium confidence): A switch-control circuit for a converter that senses switch conditions (V_DS/current) to time synchronous-rectification or switching. I could not retrieve the primary document; treat specifics as unverified.
• § 102 assessment (claims 1, 9, 16): Not anticipatory on the information available. No disclosed V_DS-collapse-triggered frequency reduction of a gate driver to a second (maintenance) frequency. Possibly relevant to the "monitor a drain-source voltage" element of claims 1/16.

4. US20150365006A1 — "Conduction detecting circuit, rectifying switch controlling circuit ... and power supply ..."

• Citation/date: Fairchild Korea Semiconductor Ltd. (inventor Hang-Seok Choi); filed 2014-06-13, published 2015-12-17; granted as US9350258B2 (2016-05-24). (https://patents.google.com/patent/US20150365006)
• Description: Detects body-diode conduction of synchronous-rectification MOSFETs by sensing a drain voltage of the SR transistor, low-pass filtering it into a "filtered voltage," and comparing (via first/second comparators) to determine conduction-interval end points. It explicitly deals with instantaneous changes in the drain voltage and with V_DS being high/low relative to a reference in order to make on/off timing decisions.
• § 102 assessment (claims 1, 9, 16; esp. claims 7–8/19–20): Not anticipatory of the independent claims (no gate-driver frequency reduction; the response is an ON/OFF timing decision, not a change to a second operating frequency). It is the most relevant reference to the collapse-detection dependent claims: its drain-voltage comparison and instantaneous-change detection map conceptually onto claim 7 ("comparing the drain-source voltage to a known ... voltage") and claim 8/20 ("monitoring instantaneous voltage changes of the drain-source voltage"). Strong § 103 combinable art on the sensing sub-feature only.

5. US20160156259A1 — "Controller and controlling method of switching power supply"

• Citation/date: Silergy Semiconductor Technology (Hangzhou) Ltd.; filed 2014-11-28, published 2016-06-02.
• Description (lower confidence): A switching-power-supply controller (Silergy is a power-management IC vendor); likely a PWM/valley or detection-based controller. Primary document not retrieved; specifics unverified.
• § 102 assessment (claims 1, 9, 16): Not anticipatory on the information available. No verified disclosure of V_DS-collapse-triggered reduction of a gate-drive operating frequency.

6. US20170063223A1 — "Voltage regulator with dynamic charge pump control"

• Citation/date: Vidatronic Inc.; filed 2015-08-28 (provisional 62/211,356, 2015-08-28), published 2017-03-02; granted as US9899912B2 (2018-02-20). (https://patents.google.com/patent/US20170063223A1/en)
• Description: A charge-pump-driven linear voltage regulator in which the charge pump is dynamically switched ON only when required and OFF otherwise, by sensing the charge pump voltage and comparing it against a reference to reduce time-averaged quiescent current. This is conceptually the nearest reference to the patent's motivating goal — reducing power consumed by a charge pump/gate driver after the critical event has passed.
• § 102 assessment (claims 1, 9, 16): Not anticipatory. The sensed quantity is the charge-pump output voltage, and the control action is ON/OFF gating, not sensing a load-switch V_DS collapse and not lowering a drive frequency to a second frequency. This is the reference an examiner/opponent would most plausibly combine under § 103 to argue the "dynamic biasing to save power" concept was known — worth flagging as the strongest obviousness-type art.

7. US20180046390A1 — "Semiconductor device and method of controlling semiconductor device"

• Citation/date: Toshiba Memory Corporation; filed 2016-08-09, published 2018-02-15.
• Description (lower confidence): A Toshiba Memory semiconductor/memory device with control circuitry (likely voltage-generation/power control of a memory device). Primary document not retrieved; specifics unverified.
• § 102 assessment (claims 1, 9, 16): Not anticipatory on the information available. No verified V_DS-collapse/frequency-reduction teaching. Relevant at most to the memory-device system context of claim 9.

8. US20180159520A1 — "Active gate bias driver"

• Citation/date: Infineon Technologies Americas Corp.; filed 2016-12-07, published 2018-06-07. (Published after the '750 priority date → § 102(a)(2) art.)
• Description: A gate driver that, upon receiving an indication to deactivate a switch, actively drives the gate to a bias voltage to reduce reverse-recovery charge — for motor-drive/IPM applications (e.g., 6–20 kHz PWM, high-voltage switches). It concerns gate biasing and switching-loss reduction, but around turn-OFF, not turn-on saturation.
• § 102 assessment (claims 1, 9, 16): Not anticipatory. No V_DS-collapse sensor, no operation-frequency generator, no second maintenance frequency upon collapse. Relevant only as general "active gate bias driver" art.

9. US10224918B2 — "Active gate bias driver"

• Citation/date: Infineon Technologies Americas Corp.; filed 2016-12-07, granted 2019-03-05 (§ 102(a)(2) art). Same disclosure as ref. 8 (a further family member, US10680598B2, also issued 2020-06-09).
• § 102 assessment (claims 1, 9, 16): Not anticipatory, for the same reasons as ref. 8.

10. US20180286465A1 — "Semiconductor device and control method thereof"

• Citation/date: Toshiba Memory Corporation; filed 2017-03-29, published 2018-10-04 (§ 102(a)(2) art); granted as US10121519B2.
• Description: A memory system (e.g., SSD) including NAND memory, a controller, a DRAM, an oscillator (OSC), a power circuit, and a temperature sensor, mounted on a substrate. This is the closest cited reference to the system architecture of claim 9 (memory device coupled to power/control circuitry, with an oscillator present) and to claim 6's PMIC context (power circuit/regulator).
• § 102 assessment (claims 9, 6): Not anticipatory. It discloses a memory-system-with-power-circuit environment and an oscillator, but there is no disclosure of a load-switch driver that monitors V_DS and lowers the operation frequency generator's frequency to a second frequency upon V_DS collapse. It does not disclose the load-switch/voltage-sensor/frequency-generator combination of claim 9 (or claim 13). Relevant § 103 art only for the memory-system claim setting.

11. US10121519B2 — "Semiconductor device and control method thereof"

• Citation/date: Toshiba Memory Corporation; filed 2017-03-29, granted 2018-11-06 (§ 102(a)(2) art). Granted version of ref. 10.
• § 102 assessment (claims 9, 6): Not anticipatory, same analysis as ref. 10.

12. US20190279688A1 — "Power Management Integrated Circuit Load Switch Driver with Dynamic Biasing"

• Citation/date: Micron Technology, Inc.; priority 2018-03-12, published 2019-09-12. This is the applicant's own pre-grant publication of the parent application US 15/919,020, i.e., the same invention and same inventor.
• § 102 assessment: Not prior art. Common-ownership / same-inventive-entity material (§ 102(b)(2)(C) exception); it cannot anticipate the '750 claims. It appears in the citation list as a family/self-reference, not as an independent anticipatory reference.
• (Note: the prompt's earlier section lists a "US20200058331A1" as the '750 pre-grant publication; the citation list here also shows a US20200388307A1 and US20190279688A1 in the "Also Published As" set. Identifier strings are reproduced literally; the two Micron publications correspond to the same '750 family.)

13. US10504562B2 — "Power management integrated circuit load switch driver with dynamic biasing"

• Citation/date: Micron Technology, Inc.; priority 2018-03-12, granted 2019-12-10. The parent patent (App. 15/919,020) of which the '750 patent is a continuation.
• § 102 assessment: Not prior art against the '750 patent — same family, same invention, same owner. Not anticipatory.

Overall conclusion on § 102

• No cited reference anticipates claims 1, 9, or 16, because none discloses the claimed combination of (i) a voltage sensor monitoring the drain-source voltage of a switch and (ii) lowering the operation frequency of the gate voltage / operation frequency generator to a second frequency in response to detecting a collapse of V_DS. Consequently no dependent claim (2–8, 10–15, 17–20) is anticipated by these references either.
• Closest references, and the claim elements they touch:
  • US7852125B2 (Philips) — V_DS-sensed gate biasing/clamping; touches the "monitor the drain-source voltage" element and the breakdown-voltage-adjacent concepts of claims 7/19. Wrong control direction and no frequency change.
  • US20170063223A1 / US9899912B2 (Vidatronic) — dynamically gating a charge pump to save power based on a sensed voltage; the most plausible § 103 anchor for the "reduce power after the transient" motivation. Sensed variable and control action differ.
  • US20150365006A1 / US9350258B2 (Fairchild Korea) — drain-voltage comparison and instantaneous-change detection; the most relevant art to the collapse-detection dependent claims (7–8 / 19–20).
  • US20180286465A1 / US10121519B2 (Toshiba Memory) — memory-system-with-power-circuit/oscillator environment; relevant to claim 9's system setting and claim 6's PMIC context only.
• References 12 and 13 are the applicant's own family (parent/pre-grant publication) and are not prior art.

Caveats. For references 2, 3, 5, 7 (US8199545B2, US20120170335A1, US20160156259A1, US20180046390A1) I could not verify the full disclosure against the claims; my "not anticipatory" conclusions for those four rest on the titles/assignees and general knowledge and should be treated as lower-confidence and re-verified against the primary documents. All conclusions here are technical/analytical, not legal opinions.

Forward citations (not prior art, listed for completeness). The '750 patent is cited by, among others, US11024345B2 (Micron family), US11211955B2 / US11843398B2 (Samsung), TWI808420B and US11901034B2 (Yangtze Memory), and several subsequent Micron power-management patents (e.g., US12125517B2 "Multi-rail power transition," US12334141B2 "Write timing compensation"). These post-date the '750 patent and are irrelevant to its novelty.

Sources: Google Patents full text for US 10,755,750 B2 (https://patents.google.com/patent/US10755750/en); Google Patents documents for US7852125B2, US20170063223A1, US20150365006A1/US9350258B2, US20180159520A1/US10224918B2, and the Toshiba Memory family; Justia Patents claims text for US 10,755,750.

I'll research the key prior-art references cited on the patent record, focusing on those most likely to map onto the claim elements (frequency-variable gate drive, V_DS/condition sensing, gate-charge maintenance).

Let me characterize the remaining cited references so the combination analysis is accurate.

I've reached my search-step limit, so I'll now synthesize the § 103 analysis using the patent's own prior-art record (the "Patent Citations (13)," "Family Cites Families," and "Cited By" lists on the Google Patents page) plus the reference characterizations I was able to retrieve.

Obviousness Analysis — U.S. Patent 10,755,750 B2 under 35 U.S.C. § 103

Note on scope. Per the task instruction, I am analyzing obviousness using the references listed in the Prior Art section of the patent page — i.e., the 13 "Patent Citations," the 2 "Family Cites Families," and the "Cited By" documents. Several of these references were listed by the applicant in an IDS or surfaced in the examiner's search; their mere presence on the face of the patent does not mean the examiner combined them. Notably, the prosecution history on the page shows the application went from a single Non-Final Action (2020-01-14) straight to a Notice of Allowance (2020-04-27) — no final rejection — which strongly suggests the examiner did not assemble the combination(s) discussed below. That context matters: my analysis is a hypothetical § 103 attack, not a record of what the Office actually did.

Caveat on reference content. I confirmed the substance of Vidatronic, Infineon, Fairchild, Silergy, Toshiba, and the Philips/Hamilton Sundstrand art at a high level, but I could not pull full claim text / every paragraph of each reference before hitting the step limit. Where a mapping is inferential rather than verbatim, I say so.

1. The governing legal framework

Under Graham v. John Deere Co., 383 U.S. 1 (1966), and KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007), the § 103 inquiry has four parts:

1. Scope and content of the prior art;
2. Differences between the prior art and the claims;
3. Level of ordinary skill in the pertinent art; and
4. Secondary considerations (objective indicia).

KSR also supplies the "motivation to combine" rationales codified at MPEP § 2143: (A) combining prior-art elements by known methods to yield predictable results; (B) substitution of one known element for another to obtain predictable results; (C) use of a known technique to improve similar devices in the same way; (D) applying a known technique to a known device ready for improvement; (E) "obvious to try"; and (F) design incentives / market forces. Teaching away, unpredictable results, and the "bodily incorporation" / "changed principle of operation" doctrines are the principal rebuttals.

I flag up front that this patent appears susceptible to a fairly strong § 103 challenge on the independent claims (1, 9, 16), for the reason developed below: every element is individually old; the only open question is whether the specific linkage — reducing gate-drive frequency because V_DS has collapsed — would have been obvious. The dependent-claim numeric ranges (8.5–12 kHz; 200–400 kHz) are the harder limitations to defeat and are the patent's best (though not bulletproof) non-obviousness anchor.

2. Level of ordinary skill in the art (PHOSITA)

The '750 patent sits at the intersection of analog power-management IC design and memory-system power delivery. A reasonable PHOSITA would be:

• a person with a B.S. in Electrical Engineering (or equivalent) and 2–4 years of experience designing switching regulators, gate drivers, and/or charge pumps; or an M.S. in EE with 1–2 years of such experience; and
• familiarity with MOSFET gate-drive techniques, charge-pump/voltage-controlled-oscillator operation, V_DS sensing, and PMIC power sequencing.

This is a mature, crowded art: the cited references span 2006–2018 and are dominated by power-electronics companies (Infineon, Fairchild, Silergy, Philips, Hamilton Sundstrand) and analog-IP houses (Vidatronic). A PHOSITA here would be highly motivated to reduce quiescent/operating power of gate-drive circuitry, because that is the stated commercial problem across essentially all of these references.

3. Claim construction of the key terms

Two claim-construction points drive the analysis:

• "lower an operation frequency of a gate voltage to the switch to a second frequency" (claim 1; similarly claim 9's "lower a frequency of an operation frequency generator"). Read in light of the specification, this means reducing the operating frequency of the VCO/oscillator that clocks the charge-pump gate driver, which in turn sets the rate at which charge is delivered to the gate. The specification is explicit: the "operation frequency generator (106) comprises a voltage controlled oscillator" driving a "gate driver (108)" (charge pump or push-pull driver), and the sensor "transmit[s] a signal to operation frequency generator (106) to lower the frequency of the oscillator." So the claim term maps to charge-pump/VCO clock frequency, not to the physical "frequency" of a DC gate voltage (there is no such thing). This is how a PHOSITA and a court would read it.

• "collapse of the drain-source voltage" (claims 1, 9, 16). The specification defines this functionally: V_DS collapse signals that the FET is "fully saturated"/"fully turned on." Dependent claims 7/8 (and 19/20) give the two disclosed detection modes: (i) comparing V_DS to a known breakdown voltage, or (ii) monitoring instantaneous voltage changes in V_DS.

Cross-reference / flag (carried over from the earlier summary): as noted in the previously generated Patent Summary, the specification's narrative of V_DS behavior is non-standard — it says V_DS "increase[s] during charging of the gate (i.e., the ohmic region)" and "once saturated, V_DS continues to increase until reaching the switch's breakdown voltage (i.e., when V_DS collapses)." Textbook MOSFET turn-on has V_DS decreasing toward R_DS(on)·I as the device enhances. I report this as-is; it does not change the § 103 mapping, because the claim is drafted functionally around "collapse," not around a specific waveform. If anything, the loose description broadens the claim and makes prior-art V_DS-transition sensing more likely to read on it.

4. The prior-art references and what each supplies

5. Independent-claim analysis and specific combinations

5.1 Claim 1 (circuit: switch + V_DS sensor + frequency-lowering on V_DS collapse)

Element (a) — "a switch." Met by essentially every reference (Infineon's driven switch; Fairchild's synchronous-rectification transistors; Vidatronic's pass/cascode device).

Element (b) — "a voltage sensor configured to monitor a drain-source voltage of the switch." Met squarely by Fairchild '006 (a detection circuit monitoring the drain voltage of a MOSFET via comparators and a low-pass filter), and by the Silergy family (sampling "a drain-source voltage of a main power transistor").

Element (c) — "lower an operation frequency of a gate voltage … to a second frequency in response to detecting a collapse of the drain-source voltage." This is the only genuinely combinable element. No single listed reference shows all of it, but each half is shown:

• Condition-responsive, power-saving control of a charge-pump gate driver → Vidatronic. Vidatronic literally claims a "dynamically controlled charge pump block that is ON only when required and OFF otherwise" and a "method for reducing power consumption of a charge pump … (a) sensing a charge pump output level; (b) comparing … against a reference; (c) dynamically controlling the charge pump block…."
• Condition-responsive frequency change of the oscillator driving a power switch → Silergy (frequency-jittering/variable-frequency controller).

Combination 1 (§ 103 core rejection): Vidatronic '223 + Fairchild '006 (+ optionally Silergy '259).

• Vidatronic supplies the dynamic-biasing of a charge-pump gate driver based on a sensed voltage and the express motivation (cut quiescent/time-averaged current).
• Fairchild supplies the V_DS-monitoring sensor and transition/collapse detection.
• Silergy supplies the frequency-adjustment mechanism if Vidatronic's on/off scheme is not deemed to read on "second frequency."

Why a PHOSITA would combine (KSR rationales):

• Design incentive / known problem (KSR (D), (F)): All three references target power efficiency; the '750 patent's own background concedes the problem ("continuous charging of the gate consumes a significant amount of power"). A PHOSITA seeking to cut PMIC load-switch standby power would look precisely to Vidatronic (dynamic charge-pump control) and Fairchild (cheap V_DS sensing).
• Predictable result / known technique (KSR (A), (C)): It was known that a charge pump's delivered charge scales with clock frequency; substituting frequency reduction for Vidatronic's on/off gating to achieve the same "less average drive power" result is a predictable substitution of one known control knob (frequency) for another (duty of on/off). Silergy shows the frequency knob was known.
• "Applying a known technique to a known device ready for improvement" (KSR (D)): The load switch is a known device; Vidatronic's dynamic control is a known technique; applying it to a PMIC load switch is the kind of improvement the art plainly invited.
• No teaching away: Nothing in these references disparages lowering drive frequency after turn-on; to the contrary, reducing charge-pump activity when not needed is the whole point of Vidatronic.

Location of the difference: The sole remaining gap is the coupling — using V_DS collapse (rather than, e.g., a timer or a charge-pump-output level) as the trigger to drop to the maintenance frequency. A PHOSITA would find this an obvious design choice because (i) V_DS collapse is the direct electrical indicator that the FET is fully enhanced and only leakage need be replenished, and (ii) Fairchild already teaches V_DS-transition detection as a status signal.

5.2 Claim 9 (system: load-switch driver + memory devices + lower OFG frequency on V_DS collapse)

Elements (a) load-switch driver, (b) memory devices coupled via a switch, and (c) the V_DS-collapse/frequency-lowering control. Combination 1 supplies (c) and the driver; Toshiba '390 / '465 / US 10,121,519 supply the memory-system context (host voltage → multiple rails, channel gating, voltage monitoring) and thus the motivation to implement the driver in a storage/PMIC environment as recited. Dependent claims 10–12 (second/third load switch drivers feeding a DRAM and an ASIC) are supplied by the routine, well-known practice of one PMIC rail per load domain, expressly taught/predicted by Toshiba's multi-channel power circuit and by the '750 patent's own admission that "the PMIC include[s] a switch driver for each power domain." Claim 13 (gate driver + operation-frequency generator + voltage sensor) is met by the Vidatronic + Fairchild + Silergy combination (charge-pump gate driver = Vidatronic; VCO/OFG = Silergy's oscillator; voltage sensor = Fairchild).

5.3 Claim 16 (method: monitor V_DS → determine collapse → supply gate voltage at second frequency)

Method claims are prima facie obvious where the apparatus that performs the steps is obvious (In re Kuehl; MPEP § 2143.01(V)). Fairchild's method of monitoring drain voltage to determine conduction-interval transitions + Vidatronic's method of dynamically controlling a charge pump based on a sensed level + Silergy's frequency control together teach every step. The claim adds no new machine or unexpected result over claims 1/9.

5.4 Alternate pairing — Infineon as primary

Infineon '520/'918 + Fairchild '006 (+ Silergy). Infineon is arguably the cloest reference on the phrase "active gate bias" and on condition-responsive gate driving of a switch "to reduce losses." A rejection could run: Infineon teaches dynamically biasing a switch gate based on device condition; Fairchild teaches sensing V_DS transitions; Silergy teaches lowering a driver's frequency; combining yields the claim. Infineon is slightly less on-point than Vidatronic for the charge-pump aspect, but stronger on the "switch gate bias" aspect. A robust Office action would likely cite both Vidatronic and Infineon.

6. Dependent-claim analysis

7. Secondary considerations (objective indicia)

None appear in the record I reviewed. There is no evidence of unexpected results, long-felt need, failure of others, licensing, or commercial success tied to the '750 claims (and, per the earlier Litigation Summary, no litigation that would have surfaced secondary-consideration evidence). Absent such evidence, the Graham factor 4 does not rebut the § 103 case on the independent claims.

8. Where a § 103 rejection is vulnerable (candid assessment)

1. The "coupling" is the whole invention. The novelty/obviousness fight is not over any component but over using V_DS collapse as the trigger to reduce gate-drive frequency. The prior-art references individually use charge-pump output level (Vidatronic) or switch deactivation (Infineon) as their control variables — not V_DS collapse. An applicant can argue that no reference "recognizes the problem" of post-turn-on gate-charge maintenance or uses V_DS collapse as the mode-switch trigger. The counter is that V_DS collapse is the ordinary, well-understood indicator of full enhancement, so its use as a trigger is a predictable variation (KSR (B)).
2. The numeric ranges (8.5–12 kHz; 200–400 kHz). These are the strongest non-obviousness foothold. A rejection must frame them as optimizations of result-effective variables and, ideally, supply art showing comparable charge-pump maintenance frequencies. The listed references do not show these numbers.
3. The "sequencer" of claim 6 is not clearly met by the cited art.
4. Reference-availability caveat (§ 102(a)(2)). Infineon US 2018/0159520 A1 published 2018-06-07 and US 10,224,918 issued 2019-03-05 — after the 2018-03-12 priority date — but both have an effective filing date of 2016-12-07, so they qualify as prior art under AIA § 102(a)(2) (U.S. application publication/patent effectively filed before the claimed invention). Toshiba US 2018/0286465 A1 (pub. 2018-10-04) and US 10,121,519 (granted 2018-11-06) likewise qualify via their 2017-03-29 priority. A careful Office action must state the effective filing date basis for each late-published reference; merely citing the publication date would be a procedural defect.

9. Bottom line

• Independent claims 1, 9, and 16 are, in my assessment, vulnerable to a § 103 rejection built from Vidatronic US 2017/0063223 (dynamic charge-pump/gate-driver control to cut power; motivating problem) as primary, in view of Fairchild US 2015/0365006 (V_DS/drain-voltage monitoring and transition detection) and either Silergy US 2016/0156259 (condition-dependent frequency control) or Infineon US 10,224,918 (active gate bias of a switch), with Toshiba US 10,121,519 / US 2018/0046390 supplying the memory-system context for claims 9–13. The KSR hooks are the strong shared motivation (power reduction), the predictable-substitution of frequency control for on/off control, and the absence of any teaching away.
• The dependent numeric-range claims (4/5, 14/15, 17/18) are the least obvious and are the patent's best defense; they would require an "optimization of a result-effective variable" rationale (MPEP 2144.05) and, ideally, art corroborating the specific frequency bands — which the currently-cited references do not provide.
• Claim 6's "sequencer" is not clearly met by the listed art.

Confidence and limitations: I am confident about the characterization of Vidatronic, Fairchild, Infineon, Silergy, and Toshiba based on the retrieved abstracts/summaries, and about the legal framework. I could not retrieve full claim text of every reference before the search-step limit, so the element-by-element mappings above should be treated as analyst inferences to be verified against each reference's disclosure before being relied upon in an Office action. No secondary-considerations evidence and no litigation (consistent with the earlier Litigation Summary) were found.