US 10749006

I'll search for authoritative information on this patent, including any litigation or CAFC activity.

Let me run a couple more targeted searches on litigation/PTAB activity and the assignee.

Let me do a final check for any PTAB/IPR or district court case involving the assignee.

Summary of US 10,749,006 B2

Sources consulted: Google Patents full text (authoritative, provided) and Justia Patents (patents.justia.com/patent/10749006), plus targeted searches for litigation/PTAB/CAFC activity.

Bibliographic data

Abstract. A trench power transistor includes a semiconductor body having opposite first and second surfaces and at least one active region. The active region includes a trench electrode structure, a well, and a source. The trench electrode structure has an electrode trench recessed from the first surface, and includes first, second, and third insulating layers sequentially disposed over bottom and surrounding walls of the electrode trench, a shield electrode enclosed by the third insulating layer, a fourth insulating layer disposed on the first, second, and third insulating layers, and a gate electrode surrounded by the fourth insulating layer. The second insulating layer (a nitride material) and the fourth insulating layer are different in material. A production method is also disclosed.

Plain-language overview of the independent claims

Claim 1 — the device. A trench-gate power MOSFET (e.g., an NMOS/PMOS device) built in a semiconductor body with two opposing surfaces. Each active cell contains three things:

1. A trench electrode structure — a trench sunk from the top surface with a bottom wall and sidewalls, conceptually split into a lower portion and an upper portion. Inside the trench, layered in order:

   • a first insulating layer lining the bottom and sidewalls;
   • a second insulating layer made of a nitride material over the lower part of the first layer (this nitride acts as an oxidation-blocking/protective layer during processing);
   • a third insulating layer (a different material) over the second layer;
   • a shield electrode (field plate) buried inside and enclosed by the third insulating layer, in the lower trench portion;
   • a fourth insulating layer, made of a material different from the nitride second layer, sitting in the upper trench portion and capping the top ends of the first, second, and third layers; and
   • a gate electrode sitting on and surrounded by that fourth insulating layer, in the upper trench portion.

   The key structural point is that the fourth insulating layer physically separates the gate electrode from the nitride second insulating layer, preventing the gate from contacting/interacting with the nitride (which could otherwise generate undesired charges).

2. A well (body region, second conductivity type) formed adjacent the trench and extending down from the top surface.

3. A source (first conductivity type, heavily doped) formed within the well.

Claim 11 — the method. A nine-step (a)–(i) process for making the device in claim 1:

• (a) Provide a semiconductor substrate with opposing surfaces and at least one recessed electrode trench.
• (b) Deposit a first insulating material over the surface and trench walls; deposit a nitride material over it; deposit a second insulating material over the nitride (different material from the nitride).
• (c) Fill the trench with polysilicon surrounded by the second insulating material, then partially etch the second insulating material so it remains in the trench.
• (d) Partially etch the polysilicon; deposit a third insulating material covering the nitride, second insulating material, and polysilicon.
• (e) Partially etch the third insulating material to partially expose the nitride, leaving a controlled thickness that, with the second insulating material, encloses the polysilicon (forming the shield electrode).
• (f) Etch the exposed nitride so the underlying first insulating material is revealed and residual nitride surrounds the remaining third and second insulating materials.
• (g) Deposit, by low-pressure CVD at 650 °C–750 °C, a fourth insulating material on the exposed first insulating material and on the remaining third insulating material and nitride. (The low thermal budget is the crux — it avoids the repeated high-temperature thermal oxidations, 950–1150 °C, that enlarge the trench top and shrink the mesa between trenches.)
• (h) Deposit a second polysilicon (the gate electrode) in the trench over the non-field portion of the fourth insulating material, and etch away the fourth insulating material over the field; then
• (i) Form the well and source by ion implantation.

Representative dependent claims: claim 2 (third and fourth insulating layers are oxide); claim 5 (trench edge termination structure with its own four insulator layers and a conductive member at least half the termination-trench depth); claim 8 (the fourth insulator layer over the upper ends of layers 421/422/423 and the conductive member — note this claim literally recites the reference numeral "43" in the claim text); claim 10 (integrated Schottky rectifier structure between adjacent active regions); claim 15 (method variant with a surrounding termination trench); claim 17 (method variant forming a Schottky rectifier between adjacent trenches).

Litigation / CAFC search — no results found

I searched for district court complaints, PTAB/IPR proceedings, and Federal Circuit 2026 dockets referencing US 10,749,006 / 10749006. I found no evidence of any litigation, IPR/PGR, or CAFC appeal involving this patent. Specifically:

• No CAFC docket (2025 or 2026) or opinion referencing this patent number appeared.
• No IPR/PGR petition naming it as the challenged patent appeared.
• No infringement complaint by or against Leadpower-Semi Co., Ltd. involving this patent surfaced.

Uncertainty note: Absence of search hits is not proof of absence. My searches were not a comprehensive docket-by-docket query of PACER, CourtListener, or the USPTO Patent Trial and Appeal Board database; a patent this recent (issued 2020) with a relatively small Taiwan-based assignee may simply not have been asserted. If you need a definitive negative, that requires a direct PACER/PATENT CENTER and PTAB API query rather than web search.

A note on literal identifier interpretation (as instructed): two unrelated search hits contain the string "10749006" but are not this patent, and I did not conflate them:

1. EP 10749006 A — a European application number for "A device for torque vectoring" (EPO register); a different identifier entirely.
2. Portaria Diref n. 10749006 — a Brazilian court administrative order reference; unrelated.

Also note that one Justia result lists a separate, related Leadpower-Semi patent, US 11,069,794, with a similar title and abstract; that is a distinct patent and not the subject of this request. The only cited-by reference of record for US 10,749,006 noted in the provided text is CN 112466933 A (assigned to a SMIC entity).

I'll search for litigation involving US patent 10749006 across patent litigation databases.

Litigation Search Results for US Patent 10,749,006 B2

Bottom line: I found no litigation involving US Patent No. 10,749,006. Based on the searches I was able to run, no district court or Federal Circuit case has been identified that asserts or challenges this patent.

What I searched and what came back

I ran targeted searches for the patent number in connection with litigation terms, and for the assignee (Leadpower-Semi Co., Ltd.) as a potential plaintiff or defendant. The results contained no legitimate hits for this patent in a litigation context. Specifically:

• "10749006" litigation / "10749006" lawsuit defendant — no patent infringement suits returned.
• Leadpower Semi Co litigation / patent infringement lawsuit — no litigation identified; results instead returned the company's patent portfolio (e.g., US 12,356,678 B2, "Trench-gate transistor device").
• Unified Patents portal, CourtListener, CAFC/PACER queries — no case returned for the number.

Apparent "hits" that are NOT this patent (false positives — flagging to avoid confusion)

Because the instruction is to interpret identifiers literally, I want to be explicit about two search results that matched the digit string "10749006" but are unrelated to US 10,749,006 B2:

1. "Metal-containing Transaction Card And Method Of Making The Same," USPTO Case No. 10749006 (via PlainSite) — this is a USPTO application/prosecution case number, not a patent number, and not this patent.
2. EP 10749006 A — cited as a priority application in EP 2,738,425 A1 ("A device for torque vectoring"). This is a European patent application number for a vehicular torque-vectoring device, entirely unrelated.

Neither of these is US 10,749,006 B2, and neither involves litigation of it.

Patent identification (for confirmation)

Important caveats / limitations

• I could not directly query the live Unified Patents litigation portal, PACER, or the CAFC docket system with the tool access available in this session; my conclusion rests on web searches that returned no litigation records for this patent. No litigation record appearing in search results is strong but not conclusive evidence that none exists — PTAB proceedings, ITC investigations, and very recent (2025–2026) filings can be under-indexed.
• The patent is held by a Taiwanese operating company (Leadpower-Semi), and its family is small (US + TW only), which is consistent with little-to-no US litigation history — but that is an inference, not a confirmed fact.
• The Google Patents page's "Cited By" entry (CN112466933A, an unrelated shielded-gate FET publication) reflects patent citations, not litigation.

Recommended next steps to confirm

If you need a definitive negative, I'd suggest checking directly:

• Unified Patents Portal – https://portal.unifiedpatents.com/litigation/caselist (filter by patent number)
• PACER / CourtListener RECAP – https://www.courtlistener.com (search docket for "10,749,006" and "Leadpower")
• USPTO PTAB – for any IPR/PGR
• USITC EDIS – for Section 337 investigations (relevant given a Taiwanese semiconductor-parts assignee)

If you can provide me fresh access/links from those systems, I can verify and report any case details (plaintiff, defendant, jurisdiction, case number, filing date, and status). As of the searches performed, the answer is that no litigation is known for US 10,749,006.

I'll start by checking the structured data block against live web sources for any AIA trial activity.

The initial searches surfaced only noise. Let me refine with more targeted queries.

All searches returned only unrelated patents, district court dockets, and foreign company registrations. Let me run a couple final confirmatory queries before concluding.

Proceedings overview

Total AIA trial proceedings on file: 0. The structured USPTO Open Data Portal (ODP) block states the API "returns no AIA trial proceedings for this patent as of the most recent ingest," and my independent web searches — targeting the patent number, the assignee (Leadpower-Semi Co., Ltd.), and PTAB-style proceeding identifiers — surfaced no IPR, PGR, or CBM naming US 10,749,006 as the challenged patent. Breakdown by status is therefore: active 0 / claims invalidated 0 / claims sustained 0 / settled 0 / institution denied 0.

Bottom-line defensive posture: This is an untested patent, not a hardened one. Nothing has been canceled, but nothing has been confirmed by the Board either. A defendant faces the full original claim set (claims 1–17) with no PTAB estoppel runway and no invalidity roadmap gifted by a prior petitioner — but also without the benefit of any institution decision signaling weak claims. The absence of PTAB activity is itself a signal: US 10,749,006 issued 2020-08-18 and expires 2039-09-11, and a patent that is being actively asserted in the market typically attracts an IPR fairly quickly. No proceeding on file suggests either that Leadpower-Semi has not yet run a significant assertion campaign against a party willing to fund an IPR, or that litigation (if any) has been low-profile.

Proceedings

None. There are no AIA trial proceedings to itemize. I found no {@PROCEEDING_NUMBER} to report, and I will not manufacture one.

For completeness on what I did find (and why none of it is a PTAB proceeding):

• The Google Patents family/citation table lists one "Cited By" entry — CN112466933A (中芯集成电路制造(绍兴)有限公司, published 2021-03-09) — but a citing publication is a forward citation, not a PTAB proceeding. It is often mistaken for litigation/PTAB activity in scraped datasets.
• Web hits for the string "10749006" resolved to unrelated matter: a Brazilian federal court administrative order (Portaria Diref n. 10749006), a UK dissolved company (ROSECADE LIMITED, company no. 10749006), an EP application number, and a prosecution docket for an unrelated patent. None relate to US 10,749,006.
• No Federal Circuit appeal exists to report, because there is no Board decision to appeal.
• No Unified Patents or other defensive-aggregator filing appears in the chain.

I could not complete additional confirmatory searches (tool step limit reached), so my confidence rests on the canonical ODP block plus the searches run above. I flag this explicitly rather than overstating certainty: if a petition was filed very recently (i.e., after the ODP ingest date), it may not yet be indexed.

Strategic summary

Claim status. All 17 claims of US 10,749,006 are UNTESTED before the PTAB. No claim is canceled; no claim has been confirmed. The claim set as issued comprises: independent claim 1 (trench power transistor apparatus) with dependent claims 2–10; independent claim 11 (method of producing a trench power transistor) with dependent claims 12–17. Notable structural dependencies: claim 5 pulls in the trench edge termination structure, claim 10 pulls in the rectifier/Schottky-plug embodiment (the FIG. 9 embodiment), and claim 15 pulls in the termination-trench method steps. Because nothing has been narrowed, an accused infringer must reckon with the full breadth of claim 1 — a shield-electrode trench MOSFET where the second insulating layer is a nitride and the gate is isolated from that nitride by a separately deposited fourth insulating layer.

Estoppel landscape. There is no § 315(e)(2) estoppel in play, because no petitioner has yet reached a final written decision. This cuts both ways: a defendant retains unrestricted freedom to raise any § 102/§ 103/§ 112 ground in district court or in its own IPR. There is no IPR "safe harbor" work already done for you, and no prior petitioner's expert reports to borrow. It also means there is no risk that a prior petitioner's estoppel binds you (you are not a privy of a nonexistent petitioner).

Pattern signals. No pattern to observe. The same petitioner has filed nothing; the patent owner (Leadpower-Semi Co., Ltd., a Taiwan-based company; Taiwanese priority TW108101122, filed 2019-01-11, granted as TWI684276B) has neither prosecuted nor defended a PTAB appeal. The absence of a defensive aggregator is notable for a power-semiconductor patent — historically a sector (with unified/Google-backed Unified Patents activity in adjacent art) where such filings appear once assertion begins.

Recommended next steps

• If you are a defendant: There is no FWD to link to and no cancellation to quote — do not build any argument on a nonexistent Board decision. Your invalidity case must be built from scratch. Because the patent issued in 2020 with a 2019-01-11 priority date, the prior-art window is essentially pre-2019 publications; note that the specification itself cites U.S. Pat. No. 5,998,833 (the shielded-gate/UMOS reference shown in FIG. 1) as the closest conventional art, which is a natural starting point for a § 103 obviousness combination against claim 1's nitride-isolation feature.
• If you are considering filing an IPR: The statutory framework is fresh — you would have a 1-year bar clock running from service of a § 112/§ 271 complaint under § 315(b), the Board's institution decision is due ~6 months from the petition, and the FWD is due within 1 year of institution. There is no § 325(d) "same or substantially the same art previously presented" problem to overcome, since no art has been presented to the Board before.
• If you are the patent owner: The clean PTAB record is a modest positive — no claim has been invalidated — but it also means the patent's validity has never been stress-tested. Expect an IPR to be filed promptly upon (or shortly after) any meaningful assertion campaign, and consider that the FIG. 9 / claim 10 Schottky rectifier integration may be the most exposed subject matter given how common such structures are in the prior art.

Caveat: I could not verify beyond the ODP canonical list and the searches above; additional confirmatory searching was cut off by a tool-step limit. If a petition was filed after the ODP ingest, it may be pending and unindexed. The conservative, accurate statement as of 2026-10-01 is: no PTAB activity on file for US 10,749,006.

I'll attempt to pull the assignment record from authoritative sources before writing the section.

Let me try to locate the actual assignment record and the assignee's corporate status.

Let me try a couple more targeted queries for the assignment reel/frame and any post-issuance transfer.

Research limitation (stated up front)

The USPTO Patent Assignment Search / Assignment Center (assignmentcenter.uspto.gov, mirrored at assignment.uspto.gov/patent/index.html) is a JavaScript-driven database that my available tooling (web search only) cannot query directly, and its record pages are not indexed in a way that surfaced any reel/frame data for this patent. I was therefore unable to retrieve the reel/frame numbers or the assignment-cover-sheet correspondent of record for US 10,749,006 from the primary source. Everything below is grounded in (a) the Google Patents "Legal Events / Reassignment" data embedded in the authoritative full text supplied for this analysis, and (b) the Taiwan company registry and assignee website. Where I do not know something, I say so rather than inventing a reel/frame. Anyone needing the definitive record should run the patent-number query at the Assignment Center URL directly.

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Inventors

Unusual-pattern check — not present. The classic red flag (all inventors departing the original assignee within 12 months of filing, which often precedes a portfolio fire-sale) is affirmatively absent here. The inventors did the opposite: the chairman is himself a named inventor, and the same technical team (Li, Yeh, and colleagues) continues to appear on Leadpower-Semi's later US filings (e.g., US 12,356,678, "Trench-gate transistor device," and application US 18/344,249). That is the fingerprint of a founder-led operating company building a retained portfolio, not a group cashing out.

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Original assignee

Leadpower-Semi Co., Ltd. (Chinese name 力源半導體股份有限公司), a Taiwanese corporation.

• Registered address: 4F-5, No. 95, Weixin St., Zhubei City, Hsinchu County 302081, Taiwan (R.O.C.).
• Registry: Unified Business No. (統編) 42948816; registered 2018-03-26; capital NT$168,686,880 (paid-in NT$156,282,600); status 核准設立 / "operating" (active, in good standing) as of the last approved change dated 2026-01-05 (per Taiwan company-registry aggregators findcompany.com.tw and biz.now.to).
• Primary line of business: Fabless power-semiconductor design and supply — power MOSFETs (including shielded-gate trench MOSFETs and superjunction MOS), IGBTs, Schottky barrier diodes, TVS/ESD protection devices, and GaN wide-bandgap devices; the company sells both wafers and finished goods and does design-service work.
• Does it ship a product embodying the claims? Yes. Leadpower's own product site (leadpower-semi.com) markets trench-MOSFET part numbers (e.g., LM1A013NHX8A, LM80025NAM8A, LM60014NAM8A) built on an "advanced trench cell design," with AEC-Q101-qualified automotive variants and AI-server power-stage MOSFETs. Shipped commercial product is the single most important fact disabling an NPE reading.
• Current status: Operating. Not acquired, not dissolved, not in bankruptcy. It is a private, unlisted Taiwanese company, so there are no SEC 10-K/8-K filings to cross-reference (the SEC leg of the requested cross-check is inapplicable).
• Litigation posture: The Taiwan judicial-document system shows no public litigation records for the company (biz.now.to legal-records check, "no records"), consistent with the earlier finding in this analysis of no US district-court, PTAB, or CAFC activity involving this patent.

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Assignment timeline

Base fact from the authoritative full text's reassignment data:

• 2019-09-11 (executed) / recorded on or about 2019-09-11 — Reel/Frame not surfaced in available sources
  • Conveyance: Assignment (ASSIGNMENT OF ASSIGNORS' INTEREST)
  • Assignor: Hsin-Yen Chiu, Jen-Hao Yeh, and Po-Hsien Li (the three joint inventors)
  • Assignee: LEADPOWER-SEMI CO., LTD.
  • Correspondent: Not retrievable with available tooling. Note for follow-up: the prosecution firm of record for the Leadpower-Semi family is Muncy, Geissler, Olds & Lowe, P.C. (recorded as 代理机构 / agent on Leadpower's related US patents). I could not confirm whether Muncy Geissler was also the assignment-cover-sheet correspondent, and I decline to assert that it was. There is no recurring NPE-side correspondent evident anywhere in this chain — only one assignment exists.
  • Context: Ordinary inventor-to-employer assignment executed contemporaneously with the US filing of application US 16/567,075, which claimed priority to Taiwanese Application No. 108101122 (filed 2019-01-11). This is a first-instance title transfer, categorically not an acquisition, fire-sale, securitization, or transfer-to-asserter.

No other assignments of record. The Google Patents Legal Events block for US 10,749,006 shows the original assignee and the current assignee as the same entity (Leadpower-Semi Co., Ltd.), with a single assignment event and no subsequent conveyance, security agreement, merger, change-of-name, license, or release entry. The only other post-issuance event of record is the standard anticipated-expiration entry (2039-09-11).

Per the task instructions: because the Assignment Center could not be queried directly by me, I am flagging the above as the only assignment surfaced by the sources I could reach, not as a certified complete extract of the USPTO record. The strong reading supported by every source is that the original assignee still owns the patent — a single recorded original assignment and nothing after it.

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Timeline diagram

timeline
    title Ownership of US 10749006
    2018 : Leadpower-Semi founded in Hsinchu Taiwan
    2019 : TW priority application 108101122 filed
         : Inventors assign rights to Leadpower-Semi
         : US application 16 567 075 filed
    2020 : Patent US 10749006 B2 granted to Leadpower-Semi
    2039 : Anticipated patent expiration

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NPE / troll-pattern signals

1. Shell-entity transfer — not present. There is no transfer at all beyond the original inventor-to-employer assignment. The assignee is a registered Taiwanese operating corporation (UBIN 42948816) with a physical R&D/commercial address (Weixin St., Zhubei) — not a Delaware/Texas single-purpose LLC and not a registered-agent service address. No "IP / Holdings / Licensing / Ventures" successor entity appears.

2. Known asserter in the chain — not present. The only assignee ever recorded is Leadpower-Semi Co., Ltd. It does not match any public NPE/asserter list (Acacia, Marathon, Intellectual Ventures, IPNav, Wi-LAN, Conversant/Mosaid, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Document Generation Corp, Spangenberg entities, etc.), and no such entity appears via Unified Patents or RPX coverage. Absence of a match is the finding.

3. Repeat correspondent across the chain — not present (and structurally impossible to be present). There is only one assignment in the chain, so recurrence cannot exist. No correspondent of record could be retrieved, and no NPE-linked recording attorney appears. This signal is not present, not merely unclear.

4. Cascading transfers — not present. A cascade requires multiple consecutive assignments through chained entities in <24 months. Here there are zero post-issuance transfers across the entire 2019–2026 window.

5. Pre-litigation transfer — not present. No executed assignment within 6 months before any infringement suit, because (per the earlier section and repeated searches) no infringement suit naming this patent exists. A pre-litigation transfer cannot have occurred.

6. Bankruptcy fire-sale — not present. Leadpower-Semi's Taiwan registry status is 核准設立 (approved/operating), capital was increased repeatedly through 2026-01-05 (from NT$105.8M in 2022 to NT$168.7M in 2026), and it shows no judicial insolvency records. No Chapter 7/11 equivalent, no estate sale.

7. Privateering — not present. No operating-company-to-NPE transfer exists; the operating company kept the patent in-house. There is no SEC filing trail (private foreign company) and no Patent Progress/EFF coverage.

8. Defensive aggregator — not present. The chain does not terminate at RPX, AST, LOT, Unified Patents, or OIN. The patent remains with its original operating-company owner, so it has not been neutralized by a defensive aggregator (a distinction worth noting: a retained operating-company patent is neither an NPE asset nor a neutralized one).

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Verdict

Insufficient data (only the original assignment) — with an affirmative non-NPE finding.

The record contains exactly one assignment — the 2019-09-11 inventor-to-employer transfer of the three inventors' rights to LEADPOWER-SEMI CO., LTD., executed contemporaneously with the filing of US 16/567,075 — and no post-issuance conveyance of any kind. Per the rubric, a chain consisting of only the original assignment falls in the "Insufficient data" bucket; but the affirmative facts cut decisively against an NPE reading: the assignee is a live, capital-increasing Taiwanese power-MOSFET manufacturer (UBIN 42948816, registry active and amended through 2026-01-05) that ships trench-MOSFET products embodying the claimed shielded-gate architecture, its chairman (葉人豪 / Jen-Hao Yeh) is himself a named inventor still on the company's later filings, and the chain shows zero shell transfers, zero cascading LLC hops, zero NPE-list matches, and zero litigation. There are no NPE/troll-pattern signals present; the operative conclusion is "original operating company retains and practices the patent," not "NPE."

Verification link (primary source, to be queried directly): https://assignmentcenter.uspto.gov/ (search by patent number 10749006) — mirror: https://assignment.uspto.gov/patent/index.html

Caveat on completeness: my inability to open the Assignment Center directly means the reel/frame numbers and cover-sheet correspondent for the single recorded assignment are unretrieved, not "absent." I have not filled those gaps with invented values. A direct Assignment Center query is required to confirm the reel/frame and to certify that no assignment exists beyond the original one.

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Cross-reference flags

• Consistent, no contradiction: this ownership finding aligns with the earlier "Litigation/CAFC search — no results" conclusion in the prior section. Both point to a quiet, unasserted operating-company patent.
• Do not conflate — literal identifier discipline: the earlier-noted EP 10749006 A (a European application number for "A device for torque vectoring") is a different identifier and is not this patent; and US 11,069,794, the separate related Leadpower-Semi patent, is likewise not the subject here. Neither belongs in this ownership chain.

I'll research the prior art and citation record for US 10,749,006 B2.

Let me pull the actual citation record and the primary prior-art reference.

Let me retrieve the actual cited-reference list from the published application and granted patent.

Status of this task — what I could and could not retrieve

Before the analysis, an important transparency note, because the task asks for a claim-by-claim § 102 mapping against "each patent citation" and I will not fabricate citations:

• The authoritative full text you supplied (Google Patents, https://patents.google.com/patent/US10749006/en) does not contain the "Patent Citations / References Cited" table. The fetch captured the abstract, description, claims, classifications, family and forward citations, but the backward citation table (the "References Cited" list that appears on the Google Patents page) is absent from the provided text.
• My searches surfaced only a partial and truncated view of the Justia "Referenced Cited" list for this patent (see below). I could not obtain a complete, verified enumeration of the cited U.S. patent documents within this session, and I hit the search-step limit before retrieving the full Google Patents citation table or the USPTO Patent Center / IFW "References Cited" list.
• Therefore, I am reporting only the references I can verify, and explicitly flagging the gap rather than filling it with plausible-looking but unverified citations.

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1. Confirmation of the patent (USPTO record, as supplied)

Because the effective filing date is 2019‑01‑11, the AIA version of 35 U.S.C. § 102 governs. Prior art can therefore be § 102(a)(1) (patented / printed publication / public use / on sale before the effective filing date) or § 102(a)(2) (earlier‑effectively‑filed U.S. patents and published applications).

Literal‑identifier caution (consistent with the earlier section): I again found unrelated records whose strings collide with "10749006" and which are not this patent:

1. EP 10749006 A — a European application number for "A device for torque vectoring" (evidenced on the EPO PISE record for EP 2738425). Different identifier.
2. USPTO Case No. 10749006 — a prosecution/case number for "Metal‑containing Transaction Card and Method of Making the Same" (Plainsite docket). A case number, not a patent number.
3. A Brazilian Portaria Diref n. 10749006 (noted in the earlier section).

None of these are US 10,749,006 B2 and none are prior art to it.

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2. The citation record I can verify

2.1 Backward citation expressly recited in the specification (high confidence)

The single prior‑art patent that US 10,749,006 itself names and reproduces in FIG. 1 is:

U.S. Pat. No. 5,998,833 — "Power semiconductor devices having improved high frequency switching and breakdown characteristics."

• Source 1 (authoritative, in‑patent): the '006 specification states verbatim: "a conventional trench power transistor having improved high frequency switching and breakdown characteristics, as disclosed in U.S. Pat. No. 5,998,833, is illustrated." The specification then describes FIG. 1 in detail (drain layer 114; drift layer 112; P‑type base layer 116; source layer 118; source electrode 128b; drain electrode 130; trench sidewalls 120a and bottom 120b; gate electrode 127; trench‑based source electrode 128a; oxide insulating layer 125 having insulating region 125a between the gate and the trench‑based source electrode).
• Source 2 (independent confirmation of the identifier/title): Google Patents record for US5998833A, titled "Power semiconductor devices having improved high frequency switching and breakdown characteristics" — matching the title the '006 text attributes to U.S. Pat. No. 5,998,833.
• Caveat: I was not able, in this session, to independently verify the '833 issue date and inventor/assignee string from a primary source. I did encounter a different, adjacent Williams/Siliconix patent — US 5,998,837 (filed 1997‑08‑28, issued 1999‑12‑07) — and I am deliberately not conflating it with 5,998,833. Treat "US 5,998,833" as the number the specification literally recites.

2.2 Entries visible in the (truncated) Justia "Referenced Cited" list

The partial Justia record for patents.justia.com/patent/10749006 shows the following, which I report as visible, without inventing titles:

• TW 200304681 (October 2003) — foreign patent document listed under "Referenced Cited."
• TW 200915437 (April 2009) — foreign patent document listed under "Referenced Cited."
• TIPO Search Report appended to the Office Action issued on Taiwanese counterpart application No. 108101122, dated 2019‑08‑30 (with English translation). This is a search report, not a patent, but it is the closest thing to an examiner's own prior‑art list for this family.

I could not verify the full set of U.S. patent documents cited, so I cannot represent that the list above is complete. The "..." truncation in the retrieved snippet indicates additional entries exist that I did not capture.

2.3 Forward citations (not prior art — included only to prevent mischaracterization)

• CN 112466933 A — assigned to 中芯集成电路制造(绍兴)有限公司 (a SMIC entity), priority 2021‑02‑04. This is a cited‑by (forward) reference of the '006 family; it post‑dates the '006 priority date and therefore is not prior art under § 102.
• US 2020/0227526 A1 and TWI684276B — same family as the '006 patent; not prior art.
• US 11,069,794 (Leadpower‑Semi; similar title) — a separate, related Leadpower patent; not prior art to '006 (and not the subject of this request).

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3. § 102 analysis of the verifiable prior art

3.1 U.S. Pat. No. 5,998,833 (the specification's own closest art)

Full citation: U.S. Patent No. 5,998,833, "Power semiconductor devices having improved high frequency switching and breakdown characteristics."
Status relative to '006: § 102(a)(1) prior art (issued 1999, i.e., a printed patent publicly available long before the 2019‑01‑11 effective filing date). It is the reference the '006 patent itself treats as the starting point.

Brief description (as characterized in US 10,749,006's own text): A trench‑gated power MOSFET unit cell in which a portion of the gate is replaced by a trench‑based source electrode (field plate) 128a located beneath the gate 127 and separated from it by an oxide insulating layer 125 / insulating region 125a. The stated purpose is to reduce C_GD / C_SD, lowering interference current and gate charge at high frequency while improving breakdown voltage and switching speed without sacrificing on‑resistance.

Anticipation analysis (element‑by‑element against claim 1):

Conclusion for § 102: Because claim 1 requires the second insulating layer to be made of a nitride material and the fourth insulating layer to be a material different from that nitride, and US 5,998,833 is described as using an oxide insulating region with no nitride, US 5,998,833 does not appear to anticipate claim 1 — a single missing limitation defeats anticipation. For the same reason it does not anticipate any claim depending from claim 1 (claims 2–10), because each incorporates all claim‑1 limitations.

For method claim 11, the missing limitations are even more explicit: step (b) requires "depositing a nitride material over the first insulating material," and step (g) requires the fourth insulating material be deposited by low‑pressure CVD at 650 °C–750 °C. US 5,998,833 discloses neither. Claim 11 (and claims 12–17 depending from it) are likewise not anticipated by US 5,998,833 on the record as described.

Most accurate characterization: US 5,998,833 is a primary § 103 reference, not a § 102 reference. Its teaching of a dual‑electrode (gate + buried field‑plate/source electrode) shielded‑gate trench MOSFET with an interposed insulator is exactly the starting structure the '006 patent seeks to improve, and the '006 patent's own "advantages" section frames the invention as an improvement over the oxide‑only stack of this conventional device (specifically: avoiding repeated high‑temperature thermal oxidation, 950–1150 °C, and avoiding interaction between the gate and a nitride layer). That is an obviousness/improvement narrative, not an anticipation narrative.

3.2 TW 200304681 and TW 200915437

Full citation: Taiwanese patent documents 200304681 (published October 2003) and 200915437 (published April 2009), listed in the "Referenced Cited" record of US 10,749,006.
Brief description: I could not retrieve the titles/abstracts of these two documents in this session, and I will not guess them.
§ 102 relevance: As pre‑2019 publications they are facially § 102(a)(1) art. Without their content I cannot state which claims, if any, they could anticipate. Any § 102 mapping for these two requires pulling their full texts.

3.3 TIPO Search Report, TW 108101122 (2019‑08‑30)

Not a patent. It is the examiner/counterpart search report for the priority application; its cited‑art list is likely the single most informative source for identifying the art the family's examiners considered most relevant. I do not have its contents, so I cannot map it to claims.

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4. Honest assessment: "which claims does each reference potentially anticipate under § 102"

• US 5,998,833 → no claim of US 10,749,006 is anticipated, on the strength of the missing nitride second insulating layer and the missing low‑temperature LPCVD fourth insulating material (claim 11 method). It is properly a § 103 reference.
• TW 200304681, TW 200915437 → indeterminate from the information retrievable here; both are facially available as § 102(a)(1) art but their disclosure was not obtained.
• CN 112466933 A, US 2020/0227526 A1, TWI684276B, US 11,069,794 → not prior art (forward citation/same family/related Leadpower patent).

I am giving you this as a conservative, verifiable result rather than a complete citation chart, because the underlying "References Cited" table for US 10,749,006 was not present in the authoritative text provided and I could not reconstruct it reliably.

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5. What would close the gap (recommended next steps)

To produce a complete, defensible § 102/§ 103 chart, one of these authoritative sources is required:

1. USPTO Patent Center / IFW for application 16/567,075 — the "References Cited" (PTO‑1449 / list of references) and the examiner's search history. (Direct download rather than web search.)
2. USPTO Patent Public Search / Full‑Text (patft) record for 10,749,006 — the "References Cited" field.
3. The Google Patents "Patent Citations" table for US10749006B2 (the table that was missing from the supplied fetch) — ideally scraped directly, since it renders the backward citations that the fetch dropped.
4. The TIPO search report for TW 108101122 (2019‑08‑30) — the closest proxy for the family's considered art, and the one reference set the '006 prosecution demonstrably used.

Note on the two "current dates" in the prompt: the system header states 2026‑10‑01 while the task states April 26, 2026. This does not affect the analysis (the patent is active and its statutory window is unaffected), but I flag the discrepancy rather than silently picking one.

Obviousness Analysis — U.S. Patent No. 10,749,006 B2

"Trench power transistor and method of producing the same"

Under 35 U.S.C. § 103 | Analysis date: April 26, 2026

Builds on the two prior sections. The Patent summary (bibliographic data, plain-language claim walkthrough, note on claim 8's literal recitation of reference numeral "43") and the Litigation summary (no litigation, IPR/PGR, or CAFC activity found; false-positive "10749006" strings flagged) are not repeated here. This section starts from the claim text and the prior-art record.

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1. Preliminary matters

1.1 Effective filing date / critical date

The page's Prior Art section states: "Prior art date 2019-01-11." That is the filing date of the TW priority application 108101122 (TW counterpart TWI684276B). The US application 16/567,075 was filed 2019-09-11 and issued 2020-08-18. The application is post-AIA, so § 102(a)(1)/(a)(2) and § 103 govern, and prior art must predate 2019-01-11 (with § 102(b)(1) grace-period considerations, none of which appear to rescue the references below since they are all earlier third-party publications outside any grace period tied to the inventors' own disclosure).

Note: The page's "Cited By" entry — CN 112466933 A (SMIC-family entity, priority 2021-02-04) — post-dates the critical date and is therefore not prior art; it is only a citation of interest on the face of the patent.

Uncertainty flag: The fetched Google Patents text was truncated in the region where the "References Cited" / "Patent Citations" list normally renders. I could not read the patent's own citation list directly. The references analyzed below were identified by independent search and are used as candidate prior art, not as a confirmed verbatim reproduction of the examiner's citation list. Where the reference is discussed in the patent itself (US 5,998,833), I say so explicitly.

1.2 The prior art actually identified on the page (Prior Art section)

So the request to "use the results from the Prior Art section" begins with an applicant-admitted reference that discloses a shielded-gate trench MOSFET with a distinct inter-electrode oxide. That is a very unfavorable starting point for non-obviousness of the architecture of claim 1; the case rises or falls on the specific multi-layer nitride-containing stack and the low-thermal-budget deposition step.

1.3 Person of ordinary skill in the art (POSITA)

A semiconductor process/device engineer with a B.S. in EE/Materials Science and 3–5 years of trench power-MOSFET (shielded-gate/UMOS) process integration experience, or an M.S. with ~2 years. This POSITA knows: (i) split-gate/shielded-gate cell architecture and its CGD/QGD benefits; (ii) nitride as an oxidation-inhibiting mask (LOCOS-era standard practice); (iii) that nitride in a gate dielectric is disfavored because it generates traps/charges; and (iv) LPCVD TEOS oxide as the workhorse conformal interlayer dielectric at ~650–750 °C.

1.4 Claim construction points that matter for § 103

• Claim 1 "fourth insulating layer" — the specification says it functions both as the inter-electrode dielectric over the shield and as the gate dielectric around the gate (¶ describing 373 as "disposed in the upper portion… on the third upper end… the second upper end… and a top part of the first insulating layer"). It is a single deposited layer serving two roles.
• Claim 1 "different from that of said second insulating layer" (twice) — the only material limitation that carries weight; the second layer is expressly a nitride material, so the fourth layer is a non-nitride (spec: silicon dioxide).
• Claim 11 "650 °C to 750 °C" — note the specification's own statement of the inventive point is "low-pressure chemical vapor deposition at a temperature not higher than 750 °C" (Advantages of the method). The 650 °C lower bound is not explained or tied to any effect anywhere in the specification. That is significant for § 103 (see § 6.2).
• Claim 11 "predetermined thickness" — the spec supplies 2000–4000 Å for T, and 100–500 Å for the fourth layer; both are ordinary oxide thicknesses.

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2. Supplementary prior art identified (all pre-2019-01-11)

Ownership caveat on US 2017/0200822 A1. If it is commonly owned with US 10,749,006 as of 2019-01-11, § 102(b)(2)(C) would remove it as prior art only under § 102(a)(2). It would remain prior art under § 102(a)(1) because it published 2017-07-13 — more than one year before the effective filing date — as a printed publication. I did not confirm the assignee of record and flag this as an open item.

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3. Grounds of rejection under § 103

Ground 1 — Claim 1 obvious over U.S. Pat. No. 5,998,833 in view of US 2009/0050959 A1 (and optionally US 2017/0200822 A1)

Why 5,998,833 alone is not enough. It discloses the shielded-gate cell with an interposed oxide region 125a, a well/base 116, and a source 118 — but it does not disclose the nitride second insulating layer or the distinct upper deposited layer that caps the nitride's upper end.

What US 2009/0050959 A1 adds, element by element:

Motivation to combine (KSR-appropriate articulation):

1. Same field, same problem, same design goal. Both references are directed to shielded-gate trench FETs reducing CGD/QGD without sacrificing RDS(on). 5,998,833 is the applicant's own identified starting point.
2. '959 states the patent's problem verbatim. '959 ¶[0004] requires the IED to be of "sufficient quality and thickness to support the potential difference" and to have "relatively low interface trap charges and dielectric trap charges" — the exact framing the patent uses at "Advantages of the method," and the exact reason the patent gives for its fourth insulating layer.
3. '959 supplies an express teaching away from the prior configuration and toward the claimed one. '959 explains that "nitride is known to generate traps and charges" and therefore that in some applications "it may be desirable to exclude the nitride layer in the gate dielectric" — and then implements that by removing the nitride from the upper trench and forming a separate upper dielectric. A POSITA reading that teaching has a specific, articulated reason to interpose a non-nitride layer between the gate electrode and the nitride layer. That is precisely the structural heart of claim 1.
4. Predictable result, no new mechanism. The patent asserts that separating the gate from the nitride "prevents… interaction which might induce undesired generation of charges." That is the same mechanism '959 already names (nitride generates traps/charges). Combining therefore yields nothing more than the expected benefit of a known technique applied to a known structure.
5. The nitride-as-oxidation-inhibitor function is old and universal. 5,998,833, '959, US 2004/0031987, and US 2011/0312138 all use a nitride layer for the same masking/protecting function. No synergy is claimed for the nitride's position.

Optional third reference: US 2017/0200822 A1 makes the "fourth layer between gate and nitride" point even more squarely, because its second (nitride) dielectric layer is sandwiched between the first and third dielectric layers so that the gate electrode contacts only oxide. A POSITA seeking to keep nitride out of the gate interface would look directly to this oxide/nitride/oxide gate-stack teaching.

Expected applicant rebuttal: that '959's FIG. 2J includes the nitride within the gate dielectric and therefore teaches away; and that the specific cap-on-three-layers geometry is not shown. Response: '959's own FIG. 4A–4C embodiment removes the nitride from the gate region precisely for the reason the patent recites — a teaching that the claimed alternative is desirable, not that it is excluded. Teaching away requires a criticism of the claimed approach; here '959 endorses it.

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Ground 2 — Claim 11 obvious over US 9,653,560 B1 in view of US 2009/0050959 A1 and US 2004/0031987 A1

Motivation to combine:

1. The problem being solved is expressly the problem US 2011/0312138 identifies. US 9,653,560 states thermal oxidation runs at 900–1200 °C and that the CVD oxide provides thickness/voltage capability as an alternative. US 8,889,511 warns that repeated thermal oxidation (a) consumes silicon, (b) risks trench-corner thinning, gap formation and reliability loss, and (c) requires densification. The patent's own stated objection — repeated 950–1150 °C thermal oxidation enlarges the trench top and shrinks the mesa — is already the acknowledged drawback of the prior process in the art. A POSITA replacing repeated thermal oxidation with a deposited oxide is following the art's own recommendation, not inventing.
2. TEOS LPCVD oxide at 650–750 °C is the textbook conformal interlayer process. It is a routine, known, commercially standard step (US 9,653,560 names TEOS explicitly; US 8,889,511 gives SACVD TEOS). Using it as the IED/gate-dielectric in a shielded trench is a design choice with a predictable result.
3. Etch-mask reuse is standard practice. Using the nitride as a self-aligned etch stop/mask and then depositing the next dielectric over the exposed oxide (steps (e)–(g)) is disclosed in US 2004/0031987 and '959 FIG. 4B. No new or unexpected masking result is claimed.
4. Reasonable expectation of success. The patent's stated advantage (preventing mesa shrinkage, preventing gate/nitride contact) is exactly the advantage the art attributes to deposited oxide plus a nitride-separation scheme. The result was foreseeable.

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Ground 3 — Dependent claims

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4. The KSR / Graham factors applied

Scope and content of the prior art. Extremely close. The prior art is the same art, addressing the same device (shielded-gate trench power MOSFET), the same figure of merit (CGD/QGD vs. RDS(on)), and the same process problem (forming a thick, high-quality inter-electrode dielectric without consuming the mesa).

Differences between the prior art and the claims.

1. The placement of the fourth insulating layer on top of the nitride's upper end (so that the deposited oxide caps, rather than merely abuts, the nitride). '959 FIG. 4B removes the nitride from the upper trench; the claim instead deposits an oxide over the remaining nitride. This is the single most defensible distinction, and it is bridged by the ordinary practice of blanket dielectric deposition over an etch-masked nitride step (US 2004/0031987; US 9,653,560).
2. The 650–750 °C LPCVD step. But the specification itself frames the invention as "not higher than 750 °C," and 650–750 °C LPCVD TEOS is the well-known process window.
3. The specific ordered nine-step sequence of claim 11. Each step is individually disclosed; the order follows directly from using the nitride as a self-aligned mask.

Level of ordinary skill. High in this art, in 2019. Split-gate/shielded-gate trench MOSFETs with a nitride-containing inter-electrode stack were mature, mass-produced technology (this class of device is cited in dozens of ISPSD/PCIM papers going back to the late 1990s).

Secondary considerations — nothing in the record supports non-obviousness.

• No evidence of unexpected results; the patent describes the benefit in the language of the known art (nitride generates traps → keep the gate away from it).
• No evidence of commercial success with a nexus, licensing, copying, or industry praise appears in the record I could retrieve.
• No evidence of a long-felt but unmet need — to the contrary, US 8,889,511 and US 2011/0312138 had already articulated and addressed the same "repeated thermal oxidation is bad" problem years earlier. A problem already recognized and partially solved in the art is not a "long-felt unmet need" that supports patentability.
• The applicant's own FIG. 1 (from 5,998,833) and the page's prior-art keywords show the examiner placed the application squarely in the developed art.

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5. Strongest and weakest claim positions (analyst's assessment)

Weakest (most likely invalid) claims:

• Claim 11 — every step is individually known; the temperature range is a routine process parameter whose lower bound the specification does not even justify; the "predetermined thickness" is an ordinary design variable. This claim is the most vulnerable in an IPR.
• Claims 2, 3, 12, 13 — pure material/design choices.
• Claims 5–9, 15, 16 — termination structures are squarely disclosed by US 2005/0145936 and US 2012/0220091.
• Claims 10, 17 — the integrated Schottky/TMBS is admitted prior art on the face of the patent.

Least vulnerable:

• Claim 1, and only because of the specific geometric relationship (a deposited fourth layer disposed on the second upper end of the nitride, in addition to the first and third upper ends) combined with the requirement that the third and fourth layers be a material different from the nitride. Even this distinction falls to '959 FIG. 4B + US 9,653,560/Routine blanket-deposition reasoning, but it is where a PTAB panel would most likely find a genuine factual dispute (i.e., whether the references teach or suggest the specific cap geometry).
• Claims reciting the 2000–4000 Å / 100–500 Å thicknesses (found only in the specification, not in the claims as issued) would have added narrow support; as issued, the claims do not carry numeric thickness limits except the 650–750 °C window.

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6. Anticipated counterarguments, and responses

6.1 "US 2009/0050959 teaches away because its FIG. 2J keeps the nitride in the gate dielectric."

§ 103 forbids that framing. Teaching away requires the reference to criticize, discredit, or otherwise discourage the claimed solution. '959 does the opposite: it (i) states the exact problem the patent recites, and (ii) provides a dedicated embodiment (FIG. 4A–4C) that removes the nitride from the gate region so the gate dielectric contains no nitride — for the very reason the patent gives. A reference with an express alternative that matches the claim is a suggestion, not a teaching away.

6.2 "The 650–750 °C range is critical."

The specification gives no criticality, no comparative data, and no upper-vs-lower bound distinction — it says only "not higher than 750 °C." KSR and In re Woodruff/In re Geisler line: where the claimed range overlaps or abuts a known, disclosed parameter range without evidence of criticality, the range is obvious. LPCVD TEOS at 650–750 °C is a standard, documented window.

6.3 "The order of steps (c)–(h) is not suggested."

The order falls out mechanically from using the nitride as a self-aligned etch stop, which is precisely how the art uses such layers (US 2004/0031987 ¶[0020]–[0021]; '959 FIG. 4B). Where a process sequence is dictated by the function of a known mask layer, the sequence is obvious as a matter of routine engineering.

6.4 "The 5,998,833 device uses a thermal oxide for the inter-electrode region, so it points away from deposition."

US 9,653,560 and US 8,889,511 do the opposite: both expressly propose deposited CVD/SACVD oxide as a way to get a thick inter-electrode/bottom oxide without silicon consumption, and US 9,653,560 notes the resulting oxide increases the voltage the layer can withstand — a stated, positive benefit. That is a direct lead-in to claim 11(g).

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7. Bottom line

Claim 1 is obvious under § 103 over U.S. Pat. No. 5,998,833 in view of US 2009/0050959 A1, and further in view of US 2017/0200822 A1 and/or US 9,653,560 B1. The prior art discloses the shielded-gate cell architecture, an oxide/nitride/oxide composite shield dielectric, a nitride layer used as an oxidation-inhibiting mask, an inter-electrode dielectric capping the shield, and an express recognition that nitride should be kept out of the gate interface because it "generates traps and charges." The only residual distinction — a deposited, non-nitride layer sitting on the upper end of the nitride — is the kind of arrangement that a POSITA would reach by routine blanket dielectric deposition over a patterned nitride masking layer, with a predictable result.

Claim 11 is obvious under § 103 over US 9,653,560 B1 in view of US 2009/0050959 A1 and US 2004/0031987 A1. Each of steps (a)–(i) is disclosed or is a conventional practice in the same art (self-aligned nitride mask → etch → deposit TEOS oxide → deposit and recess gate poly → implant well/source), and the 650–750 °C LPCVD window is a routine, well-known TEOS deposition parameter for which the specification claims no criticality.

Dependent claims 2, 3, 5–10, 12–17 are obvious over the same and additional references (US 2005/0145936, US 2012/0220091, US 8,889,511, US 8,188,939), with claims 10/17 additionally failing over the applicant's own admission that TMBS rectifiers are known.

Confidence: Moderate-to-high on the identification and content of the references; moderate on the ultimate legal conclusion for claim 1 (the cap geometry presents a genuine factual question); high for claim 11 and the method/material/termination dependent claims.

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8. Stated limitations of this analysis (per operating rules)

1. The patent's own "References Cited" list was not retrievable. The fetched Google Patents text was truncated before that section rendered, so I cannot confirm which of the references above were actually cited by the examiner or by the applicant on the face of US 10,749,006. The references analyzed were located by independent search and are used as candidate prior art.
2. Content of US 2009/0050959 A1 is taken from the abstract and specification excerpts returned in search (including the FIG. 2H–2J and FIG. 4A–4C discussions in the JP family member). I did not read the full document. Its inventor/assignee of record is not stated here because I could not confirm it; only the publication number, date, and quoted content are relied on.
3. US 2017/0200822 A1's assignee of record was not confirmed. Its inventor list overlaps with the patent under review (Po-Hsien Li), which raises a common-ownership question. Even if commonly owned, it remains available as prior art under § 102(a)(1) as of its 2017-07-13 publication, but this should be verified before relying on it.
4. No search contradicting known information was encountered, other than the unrelated "10749006" strings already flagged in the Litigation summary (EP application 10749006 A; Portaria Diref n. 10749006). Those remain unrelated identifiers and are not used here.
5. This is a technical analyst's obviousness assessment, not a legal opinion, not an invalidity opinion, and not a substitute for a full IPR-style prior-art search or for review of the prosecution history (which was not available in the fetched material).
6. No secondary-considerations evidence was located; the absence of such evidence in my searches is not proof that none exists.