US 10739201

I'll search for litigation and docket records for this specific patent number.

Let me run additional targeted searches for USPTO records and any court/CAFC activity.

Search results: litigation / docket status

I ran targeted searches for this specific number (US 10,739,201) against public litigation, PTAB, CourtListener, and CAFC-oriented sources. I found no litigation, PTAB proceeding, or CAFC appeal docketed for US 10,739,201 as of the search date. The only hits referencing the number were bibliographic aggregator listings (e.g., patentleaderboard.com/heimann-sensor-gmbh/jrg-schieferdecker/533706) and the Google Patents family page (patents.google.com/patent/US10739201/en).

Two caveats, stated explicitly because this is a negative finding, not verified absence:

• A general web search is not a docket-of-record search. I could not execute a native PACER / CourtListener RECAP / CAFC CM/ECF docket query in this session; "no results found" here means "nothing surfaced in general web indexes," not "confirmed clean."
• The file history shows ordinary, non-adversarial post-grant activity only (assignment 2019, small-entity status, grant 2020, 4th-year maintenance fee paid 2024-01-31). No reissue, reexam, or IPR entries appear.

If you need a docket-of-record confirmation, that requires a direct PACER/CM-ECF and PTAB API query, which I cannot run here.

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US 10,739,201 B2 — bibliographic summary

Abstract (as published): A high-resolution thermopile infrared sensor array having parallel signal processing channels for the signals of a sensor array and a digital port for serially emitting the signals. Each channel comprises at least one analog-to-digital converter and is assigned a memory for storing the ADC results. Power consumption is reduced in a sensor array with at least 16 rows and at least 16 columns in that no more than 8 or 16 pixels are connected to a signal processing channel. The number of channels corresponds to at least 4 times the number of rows. Some channels are disposed in the intermediate space between the pixels and others in an outer edge region of the sensor chip surrounding the sensor array along with other electronics.

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Claim 1 in plain language (the sole independent claim)

A thermopile infrared image sensor chip that combines, in one monolithic integrated structure:

1. The imager — thermopile pixels arranged in a matrix of at least 16 rows and 16 columns on a sensor chip (SP).
2. Massively parallel on-chip readout — many parallel signal-processing channels (K1…KN) for the pixel signals, rather than one shared amplifier/ADC.
3. Serial digital output — a digital port (DIO) that emits the pixel signals serially.
4. Per-channel signal chain — each channel contains at least one analog-to-digital converter plus low-pass filtering.
5. Per-channel buffering — each channel has its own storage area in a memory (RAM) holding that channel's ADC results.
6. Bounded channel sharing — no more than 16 pixels share any one channel.
7. Channel-count floor — the number of channels must be at least 4× the number of rows.
8. Physical placement rule — some channels sit in the space between the pixels, and the remaining channels sit in the outer margin of the chip surrounding the array, together with other electronics.
9. Multiplexing condition — where a channel serves more than one pixel (a > 1), a signal multiplexer selects which assigned pixel feeds that channel.
10. ADC quality floor — resolution of at least 10 bits.
11. Noise-bandwidth limit — the low-pass filtering cutoff frequency must be "less than three times and no more than eight times" the product of (frame rate) × (pixels per channel). Read literally, claim 1 requires both conditions simultaneously, so the operative cap is the narrower one, < 3× frame rate × a.
12. Pixel pitch limit — center-to-center pixel spacing less than 200 μm.

Consequence in plain terms: instead of one fast amplifier/ADC front end that must run at m×n×framerate (high bandwidth → high noise → poor thermal resolution), the chip runs many slow, low-power, high-resolution ADCs in parallel, each integrating over an entire frame period, so each channel's noise bandwidth is limited to roughly framerate × a. That is the core of the NETD/thermal-resolution improvement the specification claims (up to ~8× for 64×64, ~11× for 128×128 versus the prior-art single/column-amplifier architectures).

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Dependent claims (brief, for completeness)

• 2 — A preamplifier upstream of the ADC in each channel with gain factor < 500 (specification commentary adds < 100 preferred; auto-zero/chopper single-stage amplifiers).
• 3 — ADC operates on the charge-balancing or Delta-Sigma method.
• 4 — Each channel contains an explicit low-pass filter whose cutoff is ≥ (frame rate × a). Combined with claim 1, the intended window is ≥ 1× and < 3× the product.
• 5 — The ADC is integrating and the low-pass function is located inside the ADC.
• 6 — Noise bandwidth set as a function of frame rate via an externally supplied or internally generated mother clock and the defined ADC conversion rate.
• 7 — A portion of the channels may instead be placed on a separate chip (ROIC) underneath the sensor chip, the two chips being fixedly joined (with TSVs or edge-routed rewiring).

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Notes, anomalies, and uncertainties

• Internal inconsistency in the specification text (not corrected, per the literal-reading rule): the specification sometimes recites a pixel center-to-center spacing of "less than 200 nm" (an evident typographical error for μm, since 200 nm pixel pitch is physically implausible and inconsistent with the recited 60–90 μm working examples), while claim 1 recites "less than 200 μm." I have reported both as written and am not auto-correcting.
• Claim 7's dependency is mis-stated in the published text as "as claimed claim 1" (missing "in"); I treat it as depending from claim 1.
• Claim 4's numeric range is facially in tension with claim 1's, since claim 4 requires cutoff ≥ 1× product while claim 1 requires < 3× product; the combined scope is the intersection (1× to <3×).
• Priority record is slightly ambiguous in the Google Patents family table, which lists DE 10 2017 102 833 with both a 2017-01-18 priority date and a 2017-02-13 filing date. I treat the earliest priority as 2017-01-18 per the application data block.
• Related but separate: HEIMANN's US 10,948,355 B2 / US 20180283958A1 (from WO2017/059970A1, priority 2015-10-05, "High resolution thermopile infrared sensor array having monolithically integrated signal processing") is cited in this patent's prior-art/related-documents list. It is a distinct patent, not US 10,739,201, and I am flagging it only to avoid conflation.
• I could not independently verify the current assignee chain, any license/encumbrance, or the absence of 2026 litigation beyond the web-index search described above. Those would require USPTO Assignment records (which I did not query directly) and PACER/CM-ECF.

I'll research litigation involving US Patent 10,739,201. Let me search several sources.

Let me search more targeted litigation databases.

Let me check dedicated litigation trackers and the patent's own page.

Summary of findings on U.S. Patent No. 10,739,201

Bottom line: I could not identify any litigation involving U.S. Patent No. 10,739,201 ("High-resolution thermopile infrared sensor array," assigned to HEIMANN Sensor GmbH). No district court case, ITC action, or PTAB post-grant proceeding naming this specific patent appeared in the searches I was able to run. I want to be explicit that this is a negative finding based on limited searching, not a positive confirmation of "no litigation exists."

What I searched

• General web queries for the patent number and for "litigation"
• Patent-number queries combined with the assignee (HEIMANN Sensor GmbH)
• Queries aimed at the litigation trackers you named (Unified Patents portal, Docket Alarm, Justia)

I did not obtain a direct hit on any PACER docket, Unified Patents case list, Docket Alarm page, or CAFC opinion referencing this patent number. The only hits for the number itself were bibliographic (e.g., a PatentLeaderboard inventor page listing Schieferdecker's patents).

Important caveats

1. I did not reach the primary sources directly. My last batch of targeted searches (PACER, Docket Alarm, Justia) hit the tool-call limit before returning results, so they were not completed. The absence of results above should not be read as a thorough PACER or Docket Navigator clearing search.
2. Unified Patents' portal only lists its own challenges (IPRs/PGRs), not general district-court litigation, so it is not a comprehensive litigation source.
3. Litigation trackers frequently identify patents by number without the commas — i.e., "10739201" vs. "10,739,201" — and I tried both forms, but I cannot rule out indexing gaps.
4. This patent has a closely related family that any real enforcement campaign would likely assert together with it. If litigation exists, it may be docketed under a sibling number rather than '201. The family per the patent's own page includes:
   • US 11,187,589 B2 (continuation, US 16/946,589)
   • US 10,948,355 B2 / US 2018/0283958 A1 (related earlier Heimann case, WO 2017/059 970 A1 family)
   • Foreign counterparts: EP 3 571 482 B1, JP 7,061,624 B2, KR 10-2376929 B1, CN 110199181 B, CN 113390517 B, WO 2018/134288 A1

Recommended next steps to confirm

Because the authoritative answer requires database access I could not complete:

• PACER Case Locator (pacer.uscourts.gov) — search "Patent Number" = 10739201 across all district courts, and separately search party "Heimann Sensor" as plaintiff.
• Docket Navigator litigation module — search by patent number and by assignee.
• USPTO PTAB (PTAB Center / Patent Trial and Appeal Board EndPoint) — check for any IPR/PGR/CBM involving this patent.
• Cross-check the four sibling patents above (especially US 11,187,589) since a campaign against a competitor's thermopile array would likely include them.

On the patent itself (context, not litigation)

• Assignee: HEIMANN Sensor GmbH (Dresden, Germany); inventors Jörg Schieferdecker, Bodo Forg, Michael Schnorr, Karlheinz Storck, Wilhelm Leneke, Marion Simon.
• Priority date: 2017-01-18 (DE 10 2017 100 910); filed 2018-01-18; granted 2020-08-11; anticipated expiration 2038-01-18; status Active per Google Patents.
• The Google Patents record I have shows only "Cited By" forward citations (e.g., US 10,989,603 B2 to Panasonic; US 2023/0014361 A1 / US 12,484,321 B2 to ams International AG) — these are patent-office citations, not litigation.

If you can grant access to PACER or a commercial litigation database, I can run the confirmation search and, if any cases exist, populate the plaintiff/defendant/jurisdiction/case-number/filing-date/status fields you specified.

I'll run targeted searches to confirm whether any AIA trial proceedings exist against this patent before defaulting to "no PTAB activity."

Let me run a couple more confirmatory searches on litigation/PTAB activity involving Heimann's thermopile array family.

Proceedings overview

Total AIA trial proceedings on file for US 10,739,201: 0.

The structured "PTAB proceedings on file" block sourced from the USPTO Open Data Portal returns no IPR, PGR, or CBM proceeding against this patent, and my independent web checks surfaced no petition, institution decision, Final Written Decision, or Federal Circuit appeal naming it. Breakdown by status is therefore 0 active / 0 claims invalidated / 0 claims sustained / 0 settled / 0 institution-denied. The defensive posture this gives a defendant is the opposite of a hardened-patent story: the patent has never been tested at the Board, so nothing is canceled — but nothing is corroborated either. All seven claims stand unadjudicated, and an IPR is still fully available to you. Note the modest caveat below on confidence.

Confidence note (don't skip this). Absence of evidence here is reasonably strong but not absolute. AIA petitions are filed and indexed publicly, and a petition against a patent in an actively sold product family like Heimann's thermopile arrays would almost certainly appear in either the ODP feed or general web results within a few weeks of filing. But my web search could not directly query PTAB E2E (https://ptacts.uspto.gov/ptabweb/), and any proceeding filed and terminated in the last very short window before the ODP ingest would be missed. Treat this as "no PTAB activity found" rather than "no PTAB activity exists," and confirm with a PTAB E2E patent-number search before you rely on it for a § 315(b) one-year-bar calculation.

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No proceedings to report

There are no proceeding entries for US 10,739,201. To be explicit about the fields you asked for: there is no proceeding number to quote, no petitioner to name, no APJ panel, no grounds, no institution decision, no FWD, no settlement, and no CAFC docket. I am not going to manufacture one, and I am not going to fill this section with the family's other patents (US 10,948,355; US 11,187,589; US 10,578,493; US 11,268,861) — those are different patents with different claim sets, and an IPR against one of them would not be an IPR against this one.

For completeness on the procedural posture that matters for your timing analysis:

• Patent grant date: 2020-08-11 (per the bibliographic record).
• PGR window: because the effective filing date (2017-01-18 priority; 2018-01-18 PCT/national-stage filing) is well after 2023-03-16's predecessor date, the patent was PGR-eligible, but the 9-month PGR window closed on 2021-05-11. PGR is no longer available.
• IPR window: opened 2021-05-11 and remains open indefinitely. There is no deadline to petition other than the § 315(b) one-year bar running from service of a complaint on you or your privy.
• Maintenance: 4th-year maintenance fee paid 2024-01-31; anticipated expiration 2038-01-18.

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Strategic summary

Claim status: everything is UNTESTED. Claims 1–7 are all live. Nothing has been canceled, narrowed by amendment, or confirmed by the Board. Claim 1 is the sole independent claim and carries the load: it requires (i) ≥16 rows and 16 columns of pixels, (ii) at most 16 pixels sharing a signal processing channel, (iii) signal processing channels numbering at least 4× the number of rows, (iv) channels split between the inter-pixel intermediate space and the outer edge area, (v) a multiplexer per channel where a > 1, (vi) an ADC with resolution of at least 10 bits, (vii) low-pass filtering with a cutoff at "less than three times and no more than eight times" the product of frame rate and pixels-per-channel (note the internal tension in that claim language — it recites both a lower and an upper bound in a way that reads awkwardly), and (viii) a center-to-center pixel distance under 200 µm. Dependent claims 2–7 add the preamplifier gain <500, charge-balancing/Delta-Sigma ADC, the ≥1× lower cutoff bound, the integrating ADC with in-converter low-pass, the mother-clock conversion-rate determination, and the separate ROIC chip under the sensor chip. Because a number of these limitations are numeric and structural rather than pure signal-processing abstractions, the claim set is a mixed IPR target — the numeric thresholds are the soft spots, and a § 103 combination built to hit them is the natural attack.

Estoppel landscape: there is none. No petition has ever been filed, so § 315(e)(2) estoppel has never attached to anyone. You have the entire prior-art universe available — patents, printed publications, and (for the system-art angles) the applicant-admitted prior art in the specification itself, which candidly concedes that each individual element (parallel preamplifiers, low-pass filters, multiplexed ADCs, per-pixel channels) was known, and frames the invention as an arrangement/architecture problem. That spec text is unusually useful: the Background section recites that WO 2006/122529 A1 already integrated one preamplifier plus one low-pass filter per row, that DE 103 22 860 B4 already placed preamplifiers in front of a multiplexer with cyclic power-down, and that Kassovski et al. (IRS 2011) already described a 4×16 array with one signal processing channel per pixel, a 16-bit 2nd-order Delta-Sigma ADC, a digital low-pass filter, and on-chip RAM buffering. The patent's own distinguishing argument is essentially "do that, but at 16×16 or larger with a pixel pitch under 200 µm and channels split between inter-pixel gaps and the chip edge, using a low-gain preamp plus a slow high-resolution ADC to save power." Whether that survives an obviousness challenge hinging on design incentives for higher pixel count and reduced power is exactly the question the Board has never been asked. Nothing in the record prevents you from asking it.

Pattern signals: the patent owner has never had to defend at the Board, and no defensive aggregator is in the chain. Heimann Sensor GmbH (Dresden) is the assignee of record, small-entity status, and the patent family is prosecution-heavy — the same invention family produced US 10,578,493, US 10,739,201, US 10,948,355, and US 11,187,589 as continuations/divisionals, plus EP 3571482 B1, JP 7061624 B2, KR 102376929 B1, and CN 110199181 B. That kind of layered continuation strategy usually signals a patentee preparing for assertion rather than one responding to attacks. There is no USPTO assignment to a monetization entity and no Unified Patents or other aggregator filing history visible on this patent in the cited-by/citing-by data (Unified's portal surfaces WO 2006/122529 A2 from the same family, but that is a clearance-page listing, not a challenge). The two visible "Cited By" hits are Panasonic's US 10,989,603 (infrared sensor chip) and ams International's US 2023/0014361 (CMOS-compatible NIR sensor system) — competitor art-citations, not challenges.

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Recommended next steps

• This is the rare case where the absence of PTAB activity is itself the most exploitable fact. There is no FWD to link to, no disposition to quote, no intervening rights, no prosecution-history narrowing forced by an IPR, and no estoppel wall. If you are defending an assertion, an IPR is on the table as a first-instance weapon rather than a follow-on, and you can build it on the applicant's own admitted prior art plus the Kassovski and WO 2006/122529 references without being pre-empted.
• Verify before relying on it. Run a patent-number search on PTAB E2E (https://ptacts.uspto.gov/ptabweb/) and a CourtListener docket search (https://www.courtlistener.com/) for "10,739,201" and for "Heimann Sensor." If a complaint has been served on you, calendar the § 315(b) one-year bar immediately from the service date — with no prior petitioner, you are the first mover and get no benefit from anyone else's filing date.
• If you find a live proceeding I missed, the statutory clocks are: institution decision within 6 months of the petition's filing (or of PO's preliminary response, if filed); trial completes within 12 months of institution, extendable up to 6 months for good cause. Non-institution decisions are not appealable (35 U.S.C. § 314(d), Thryv, Inc. v. Click-to-Call Technologies LP), so a denial is effectively terminal — the leverage has to go into the petition itself.
• Target the numeric limitations. The pixel-pitch-under-200 µm and ≥4×-rows channel-count limits are the easiest to meet with a prior-art combination, since both are straightforward design consequences of higher pixel count, which the specification itself frames as the known market direction. The pixel-splitting limitation ("one portion … in an intermediate space between the pixels and another portion … in an outer edge area") is the limitation most likely to require a second reference and a motivation-to-combine argument.
• Nothing to do on the patent-owner side. There is no motion to amend history, no adverse judgment, and no PTAB-imposed narrowing — so there is no "patent owner estoppel" (37 C.F.R. § 42.73(d)(3)) that would constrain a reissue or continuation strategy if the patentee tries to route around an adverse ruling later.

If you need a second, cheaper read on this: request the patent's complete file wrapper and any terminal-disclaimer certificates via USPTO PatentCenter (https://patentcenter.uspto.gov/), which is the fastest way to confirm that none of the four family members were subject to a proceeding that the ODP feed might have keyed to a sibling application number rather than to US 10,739,201 itself.

I'll start by pulling the authoritative assignment data for this patent.

Let me verify whether any subsequent assignments or litigation exist.

Let me check the attorney of record and any litigation or assignment correspondence for this family.

Assignment & Ownership Analysis — US 10,739,201 B2

Patent: US 10,739,201 B2 — "High-resolution thermopile infrared sensor array"
App. No.: 16/477,273 (371 of PCT/EP2018/051166) · Filed: 2018-01-18 · Granted: 2020-08-11
Priority: DE 10 2017 100 910.8 (2017-01-18) and DE 10 2017 102 833.1 (2017-02-13)

Methodological note / limitation: assignmentcenter.uspto.gov is a JavaScript application that could not be queried programmatically within this session, and the underlying Google Patents legal-events feed (fetched 2026-09-24) exposes only the summary fields of the single recorded conveyance — not the correspondent field or the reel/frame PDF. I therefore report what is verifiable and explicitly flag the one field I could not retrieve. No assignment is invented below.

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Inventors

Pattern assessment: No unusual inventor pattern. Four of the six residencies (Mainz, Bad Schwalbach, Taunusstein, Lorch am Rhein/Hünstetten) cluster around HEIMANN's Eltville am Rhein development branch (Rohrbergstraße 7, 65343 Eltville); Schieferdecker and Storck tie to the Dresden HQ. This is a single-employer R&D team, not a mixed-provenance group.

No inventor-exodus signal. Schieferdecker remained Managing Director until his death in July 2026; Schnorr is still with the company as of 2026; the same six names recur as inventors on HEIMANN's later US 11,187,589 and US 11,988,561. This is the inverse of the pre-fire-sale pattern — the inventing team stayed put for a decade.

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Original assignee

HEIMANN Sensor GmbH — Maria-Reiche-Str. 1, 01109 Dresden, Germany (later records also show Grenzstr. 22 / Rohrbergstraße 7, Eltville).

• Line of business: Design and manufacture of infrared thermopile sensors, thermopile arrays and array modules, pyroelectric sensors, IR light sources and MEMS Pirani vacuum sensors.
• Ships products embodying the claims — yes, directly. HEIMANN's HTPA digital array line is the commercial embodiment of this disclosure: monolithic on-chip signal conditioning with integrated ADCs and a digital interface, stated frame rates up to 12 Hz at full resolution with 16-bit on-chip ADCs, and pixel pitches of 60 µm (120×84 array) and 90 µm (80×64 array) — squarely inside claim 1's "less than 200 µm" centre-to-centre limitation and the "at least 10 bits" ADC limitation. The company's own 2020 conference paper describes the 120×84 / 60 µm part as the productisation of this work. The current portfolio reaches 160×120 px at 45 µm pitch.
• Status: operating, independent, growing. Founded 2002; ~220 employees; >15 million sensors/year; manufacturing in Dresden and at Heimann Sensor Packaging Sdn. Bhd., Senai, Malaysia; sales offices on four continents. No bankruptcy, no acquisition, no known change of control. The company continued filing US applications (US 11,988,561 granted 2024-05-21) well after this patent issued.

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Assignment timeline

Records located: exactly one. There is no post-issuance assignment chain.

• 2019-06-19 to 2019-07-01 (executed) / recorded 2019-07-11 — Reel 049724/0640
  • Conveyance: Assignment (ASSIGNMENT OF ASSIGNORS' INTEREST)
  • Assignor: Jörg Schieferdecker, Bodo Forg, Michael Schnorr, Karlheinz Storck, Wilhelm Leneke, Marion Simon (all six named inventors, individually)
  • Assignee: HEIMANN SENSOR GMBH (Germany)
  • Correspondent: not retrievable from the sources available in this session — the Google Patents legal-events feed carries the reel/frame and the assignor/assignee names but not the correspondent field, and assignmentcenter.uspto.gov could not be queried directly. I am not going to guess a name. (For context only, and not as an assignment correspondent: prosecution counsel of record on the sibling continuation US 11,187,589 is listed as Smartpat PLC by a secondary aggregator; the attorney of record on HEIMANN's earlier US 7,842,922 was Heslin Rothenberg Farley & Mesiti P.C. Neither is confirmed as the correspondent on reel 049724/0640.)
  • Context: Confirmatory national-stage assignment. Executed ~2.5 years after the 2018-01-18 filing and recorded 2019-07-11 — seven days before the 30-month national-stage deadline of 2019-07-18. This is a routine PCT/§371 formality perfecting title in the applicant company, not a transfer of economic control.

Nothing thereafter. Google Patents legal events for this patent show no further assignment, security agreement, merger, change of name, licence or release through the fetch date (2026-09-24). The only other legal events are the patent grant (2020-08-11), the anticipated expiration (2038-01-18), and a 4th-year maintenance-fee payment on 2024-01-31 by a small entity — i.e. HEIMANN paying its own annuity, which is itself affirmative evidence that HEIMANN still owns the patent.

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Timeline diagram

timeline
    title Ownership of US 10739201
    2017 : Priority DE applications filed
    2018 : PCT and US national stage filed
    2019 : Inventors assign to Heimann Sensor GmbH
    2020 : Patent granted to Heimann Sensor GmbH
    2024 : Heimann pays 4th year maintenance fee

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NPE / troll-pattern signals

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Verdict

Operating-company assertion — as the nearest fit in the supplied taxonomy, with one explicit caveat: the "assertion" prong is not evidenced. No infringement litigation naming US 10,739,201 was located.

The chain consists of exactly one recorded conveyance — reel 049724/0640, executed 2019-06-19/2019-07-01 and recorded 2019-07-11 — transferring the six inventors' rights to HEIMANN Sensor GmbH, which is the original applicant, remains the assignee of record, and paid the 4th-year maintenance fee itself on 2024-01-31. Every NPE-signal test above returns not present; there is no LLC, no licensing vehicle, no asserter, no cascading transfer, no bankruptcy, and no defence aggregator. The correct disposition of this file, from an NPE-tracking standpoint, is a clean negative: an operating manufacturer that commercialises the claimed subject matter in its HTPA array line and has never parted with the patent.

Verify at: https://assignmentcenter.uspto.gov/ (search by patent number 10739201) and the legacy index at https://assignment.uspto.gov/patent/index.html — specifically to retrieve the correspondent field on reel 049724/0640, which is the one gap in this report.

I'll research this patent and its prior-art citations. Let me start with searches on the patent itself and its key references.

I have strong grounding on the patent and several citations. Let me confirm details on the remaining references.

Prior-Art Analysis — U.S. Patent No. 10,739,201 ("High-resolution thermopile infrared sensor array")

Built on, and not repeating, the earlier litigation-summary section. All identifiers are read literally. Where I could only reach secondary sources (patent PDFs, Google Patents, the AMA conference site), I say so.

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1. Confirmation of the patent (USPTO record)

A search on the literal number 10739201 returns exactly one grant, and no "similar-number" contamination:

Because the application was filed after 2013‑03‑16, AIA-style 35 U.S.C. §102 governs. Prior art therefore has two relevant channels: §102(a)(1) (something "patented, described in a printed publication, … or otherwise available to the public before the effective filing date") and §102(a)(2) (a U.S. patent/published application, or a WIPO application designating the U.S., "effectively filed before" and naming another inventor). The effective filing date is at least 2017‑01‑18 (and no later than 2017‑02‑13).

Source: https://patents.google.com/patent/US10739201/en

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2. The §102 touchstone — claim‑1 limitations

Anticipation requires one reference to disclose every limitation, arranged as claimed. Claim 1 requires (element‑lettered for the mapping below):

• (a) pixels in ≥16 rows and 16 columns;
• (b) monolithic integrated signal processing on a sensor chip;
• (c) a plurality of parallel signal-processing channels;
• (d) a digital port for serial pixel-signal output;
• (e) each channel with ≥1 ADC and one low-pass filtering;
• (f) a RAM storage area per channel for the ADC results;
• (g) ≤16 pixels share a channel;
• (h) number of channels ≥ 4 × number of rows;
• (i) one portion of channels between the pixels and another portion in the outer edge area with other electronics;
• (j) a MUX per channel when pixels/channel a > 1;
• (k) ADC resolution ≥ 10 bits;
• (l) low-pass cutoff < 3× and ≤ 8× the product (frame rate × pixels/channel);
• (m) center-to-center pixel distance < 200 µm.

Dependent claims: 2 (preamp gain <500), 3 (charge-balancing / Δ‑Σ ADC), 4 (LPF cutoff ≥ frame‑rate × pixels/channel), 5 (integrating ADC; LPF inside the ADC), 6 (noise bandwidth set by mother clock + conversion rate), 7 (a portion of channels on a separate chip beneath the sensor chip, fixedly joined).

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3. The 16 patent citations — one by one

Dates are from the patent's own citation table (authoritative) verified against Google Patents/Justia.

3.1 Kassovski-adjacent / Heimann "background" art

WO 2006/122529 A2 — Heimann Sensor GmbH — "Thermopile infrared sensor array"

• Priority 2005‑05‑17; published 2006‑11‑23. (US equivalent US 2008/0216883 A1, pub. 2008‑09‑11.)
• Description: Membrane under each thermopile element exposed by back-side etching in a honeycomb pattern; electronics in the chip border; one preamp + downstream low-pass filter per row or column (per "at least every fourth" element).
• §102: Discloses element (e) (per-channel preamp + LPF) and, arguably, a row/column channel architecture, but for a 64×64 array it yields only 64 channels — it does not meet (g)/(h) in the claimed sense and says nothing about (k)/(l)/(m). Not anticipatory of claim 1; it is the art the '201 specification expressly criticizes (Bandwidth "up to 64 times higher than necessary"). Relevant only as §103 background for claims 2 and 4.

DE 10 2010 042 108 A1 — Heimann Sensor GmbH — "Thermopile infrared sensor in monolithic Si micromechanics"

• Priority 2010‑01‑18; published 2011‑07‑21. (US equivalent US 2011/0174978 A1, pub. 2011‑07‑21.)
• Description: Monolithic Si‑micromechanical thermopile IR sensor (pixel/membrane architecture).
• §102: Pixel-architecture background; no channel/ADC/LPF/placement teaching. Not anticipatory of any claim.

US 2011/0174978 A1 — same family/document as DE 10 2010 042 108 A1 (see above).

WO 2017/059970 A1 — Heimann Sensor GmbH — "High-resolution thermopile infrared sensor array having monolithically integrated signal processing"

• Priority DE 10 2015 116 866.9, 2015‑10‑05; PCT filed 2016‑07‑05; published 2017‑04‑13. US equivalents: US 2018/0283958 A1 (pub. 2018‑10‑04), granted as US 10,578,493 B2 and (as a continuation) US 10,948,355 B2.
• Description (this is the closest reference in subject matter): High-resolution thermopile IR array with monolithically integrated, parallel channels each having ≥1 ADC and an assigned RAM area; ≤16 (preferably ≤8, ideally 1) pixels per channel; MUX to select pixels when a>1; preamp gain <500, preferably <100; ADC ≥10 bits (16–24 preferred), charge-balancing/Δ‑Σ; LPF cutoff ≥ (frame rate × pixels/channel), preferably not more than 2–3×; integrating ADC; a portion of channels in the interspace between pixels, and a portion with other electronics in the outer edge area; pitch <300 µm, preferably <200 µm or <100 µm.
• §102 — important nuance: On subject matter alone this reference maps to nearly every element of claim 1 (b–e, g–j, k, l, and approximated m). But it is very likely not §102 prior art to the '201 claims at all:
  • It published 2017‑04‑13, after the '201 effective filing date (2017‑01‑18 / 2017‑02‑13) → not §102(a)(1) art.
  • Under §102(a)(2) it must "name another inventor." The inventive entity of WO '970 and of the '201 patent is the same six inventors (Forg, Schnorr, Schieferdecker, Storck, Simon, Leneke). An identically-invented application is not §102(a)(2) art, and the common-ownership exception (§102(b)(2)(C)) would independently remove it.
  • Practical conclusion: the '201 specification itself cites WO '970 in the BACKGROUND as the applicant's own earlier work. It is a §103 / background reference at most, and a serious §102(a)(2) argument against it exists.
• Refinement vs. the earlier section: the earlier "Litigation summary" listed US 10,948,355 B2 and US 2018/0283958 A1 as the '970‑family members. The direct national‑phase grant is US 10,578,493 B2 (15/766,100); US 10,948,355 B2 is a continuation of it. No contradiction — this is additional detail.

US 2018/0283958 A1 — Heimann Sensor GmbH — US publication of the WO '970 family (pub. 2018‑10‑04). Same teaching and same §102(a)(2)/common‑ownership caveat as WO 2017/059970 A1.

3.2 Multichannel-ADC / readout art (mainly relevant to (e)/(k), claims 3 and 5)

US 2006/0243885 A1 — Denso Corporation — "Image sensor and control method of the image sensor"

• Priority 2005‑04‑05; published 2006‑11‑02.
• Description: Image sensor with the light-collection array and A/D converters on one chip; the array is divided into sub-arrays, each assigned an A/D converter plus a sub-array controller for high-speed control.
• §102: Discloses sub-array-parallel ADCs on chip (part of (c)/(e)) and on-chip integration (b). It is not a thermopile array; discloses no per-channel RAM (f), no ≤16-pixel grouping (g), no ≥4×rows rule (h), no mixed placement (i), no MUX teaching (j), no ≥10-bit requirement (k), no cutoff window (l), and no <200 µm pitch (m). Cannot anticipate claim 1.

US 8,179,296 B2 — The Massachusetts Institute of Technology — "Digital readout method and apparatus"

• Priority 2005‑09‑30; granted 2012‑05‑15.
• Description: Digital readout of a sensor array connected to the input of an A/D-converter array; expressly noteable for IR image sensors with high areal resolution (small pixels) and high SNR.
• §102: Supports (c)/(e) (array-parallel ADC) and general small-pixel readout. Silent on the thermopile‑specific, cutoff-formula, RAM-per-channel and placement limitations. Not anticipatory of claim 1; §103 background for ADC-per-channel claims.

US 2007/0194962 A1 — Go Asayama (Sony) — "DA converter, AD converter, and semiconductor device"

• Priority JP 2005‑239686, 2005‑08‑22; filed 2006‑08‑18; published 2007‑08‑23; granted as US 7,423,570 B2 (2008‑09‑09).
• Description: CMOS image sensor with column-parallel, single-slope-integrating (ramp-comparison) ADCs; a DA converter generates the ramp reference; 10-bit column ADCs discussed (10/14-bit examples).
• §102: Background for integrating/ramp ADCs and ≥10-bit converters (elements (e)/(k), claims 3 and 5). It is an imaging (visible-light) device, not a thermopile array; no low-pass-cutoff formula, no ≤16-pixel grouping, no placement teaching. Not anticipatory of claim 1.

US 8,018,579 B1 — Apple Inc. — "Three-dimensional imaging and display system"

• Priority 2005‑10‑21; granted 2011‑09‑13.
• Description: 3‑D imaging and display system (detector array with on-chip readout).
• §102: Only generic array/readout background; no mapping to claim‑1 elements. Examiner-cited (§103 context only). Not anticipatory.

US 9,270,895 B2 — Massachusetts Institute of Technology — "Methods and apparatus for true high dynamic range imaging"

• Priority (US provisional 61/860,438) 2013‑07‑31; filed 2014‑04‑25; granted 2016‑02‑23.
• Description: Digital focal-plane array (DFPA) with an ADC and an m-bit counter in every pixel (demonstrated on a 640×480 long-wave IR array); counters roll over and are "unwrapped" for HDR.
• §102: Discloses per-pixel ADC and per-pixel storage — relevant to (e) and arguably (f) — for an IR array. It has no thermopile signal path, no low-pass-cutoff formula (l), no ≤16-pixel channel sharing (g), no ≥4×rows rule (h), no mixed placement (i), no MUX teaching (j). The '201 specification itself uses this reference only to note "each pixel is assigned an analog-to-digital converter and an m-bit counter." Not anticipatory of claim 1.

3.3 Preamp/MUX readout art (relevant to (j) and claims 2–3)

DE 103 22 860 A1 / B4 — X‑FAB Semiconductor Foundries AG — "Circuit arrangement for reading out electronic signals from high-resolution thermal sensors"

• Priority 2003‑05‑21; published 2004‑12‑23. (US equivalent US 2007/0187602 A1, Wennmacher, pub. 2007‑08‑16.)
• Description: Signals from a plurality of sensor elements serially read out over one/few data lines via a multiplexer, with a preamplifier between each individual thermal sensor element and the MUX; amplifiers cyclically switched on/off to cut thermal load.
• §102: Discloses a per-element preamp ahead of a MUX (elements (j) and claim 2-ish), for a thermal-sensor array. It lacks on-chip ADC per channel (e), RAM per channel (f), the ≤16-pixel grouping (g), the ≥4× rule (h), the placement teaching (i), and the ADC-resolution/cutoff/pitch limitations. The '201 specification criticizes it (cyclically switching amps without noise-bandwidth control). Not anticipatory of claim 1.

US 2007/0187602 A1 — Christian Wennmacher — "Circuit and method for reading out electric signals from a high-resolution thermal sensors"

• Priority 2003‑05‑21; published 2007‑08‑16. US counterpart of DE 103 22 860 (same teaching; see above). Not anticipatory of claim 1.

3.4 Panasonic IR-sensor art (relevant to (g)/(j) and thermopile-array background)

US 2013/0093037 A1 — Panasonic Corporation — "Infrared sensor" and EP 2 587 234 A1 — Panasonic Corporation — "Infrared sensor"

• Priority 2010‑06‑24; published 2013‑04‑18 (US) / 2013‑05‑01 (EP).
• Description: IR sensor suppressing SNR drift on chip warming by heating the cold contact; each IR detector in the array has a MOS pixel-selection switch plus vertical reading lines and horizontal signal lines; series/parallel thermopile connection improves SNR; output signal from each thermopixel is utilized.
• §102: Discloses pixel selection switches / read lines — the functional antecedent of element (j) — and a thermopile array read-out. The '201 specification notes these signals are forwarded "without band limitation, or intermediate preamplifiers." No per-channel ADC (e), no RAM (f), no ≤16-pixel grouping (g), no ≥4× rule (h), no mixed placement (i), no cutoff window (l), no pitch limit (m). Not anticipatory of claim 1.

3.5 Horiba single-preamp art (relevant to claim 2)

JP 2004‑170375 A — Horiba Ltd — "Thermopile array sensor"

• Priority 2002‑11‑22; published 2004‑06‑17.
• Description: Thermopile array sensor that suppresses ambient-temperature white noise and 1/f DC-amplifier noise using a shielded compensation thermopile per row; an op-amp processes the measurement-minus-compensation difference; the '201 specification characterizes it as having "only a single preamplifier."
• §102: Discloses a preamp/difference stage (claim 2 context) and a compensation concept. It has a single preamp and no per-channel ADC/RAM, no ≥4×‑rows rule, no cutoff formula. Not anticipatory of claim 1 and not even of claim 2 (which requires the preamp to be per signal-processing channel with gain <500).

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4. The non-patent citations

NPL‑1 (primary): V. Kassovski, A. Grigorov, H. Hristov, P. Nedelev (Melexis Bulgaria) & B. Forg, F. Herrmann, W. Leneke, J. Schieferdecker (Heimann Sensor), "Miniaturized 4×16 Thermopile Array Sensor with Integrated on Signal Conditioning on Chip," Proc. IRS² 2011, Nürnberg, p. 57; DOI 10.5162/irs11/i2.5; ISBN 978‑3‑9810993‑9‑3 (conference 2011‑06‑07/09). Verified at https://www.ama-science.org/proceedings/details/378.

• Description: 4×16 = 64‑pixel thermopile array with 64 on‑chip signal-conditioning channels (one per pixel); each channel = low-noise amplifier + 2nd‑order Delta‑Sigma ADC + digital low-pass filter; 16‑bit digitization; parallel processing → NETD 0.2 °C @ 1 Hz; grid of 80 contact‑temperature sensors; results in on-chip RAM; I²C; refresh 0.5–512 Hz; 2.4–3.6 V, <4 mA.
• §102 mapping: This is the single most on-point §102 reference for the per-channel sub-combination — it discloses elements (c), (e), (f), the Δ‑Σ conversion of claim 3, and the LPF of claims 4/5; and it satisfies the ratio (h) numerically (64 channels ÷ 4 rows = 16× ≥ 4×) and (g) (a = 1 ≤ 16).
• Why it cannot anticipate claim 1: the array is 4 rows × 16 columns — it fails the ≥16‑row requirement of element (a); and the stated row spacing is 220 µm, which exceeds the <200 µm limit of (m). There is also no disclosure of the (l) cutoff‑frequency window, the (i) mixed placement, or the (k) ≥10‑bit bound as claimed. So Kassovski is best characterized as §103 art for the channel architecture, not an anticipatory reference.

NPL‑2 / NPL‑3 (same paper, alternate citation): Kassovski, V., "Miniaturized 4×16 thermopile array sensor with integrated on chip signal conditioning," in SENSOR+TEST Conferences 2011 – SENSOR, OPTO, IRS2, Wunstorf: AMA Service GmbH, 2011, p. 238, ISBN 978‑3‑9810993‑8‑6. Same disclosure and same §102 limits as NPL‑1.

NPL‑4: M. Kimata, "Trends in small-format infrared array sensors," 2013 IEEE Sensors, 2013‑11‑03, pp. 1–4.

• Description: Review of small-format IR array sensors (thermopile/bolometer), covering shrinking pixel pitch and format trends.
• §102: General state-of-the-art/background; may support motivation to shrink pitch (element (m)) but discloses no claim‑1 combination. Not anticipatory.

NPL‑5: Longmire et al., "Simulation of clutter rejection signal processing for mid‑infrared surveillance systems," 1981, SPIE Proc. — Processing of Images and Data from Optical Sensors, vol. 292, pp. 193–203.

• Description: IR signal-processing/analysis (clutter-rejection) simulation.
• §102: Remote from the structural/readout limitations; background for digital IR signal processing only. Not anticipatory.

NPL‑6: M. Schnorr, B. Forg, F. Herrmann, W. Leneke, M. Simon, J. Schieferdecker (Heimann Sensor), "New miniaturized Thermopile IR Arrays with medium resolution," Proc. IRS² 2015, AMA Conferences 2015 (Nürnberg, 2015‑05‑19/21), pp. 957–960.

• Description: Heimann's own disclosure of miniaturized medium-resolution thermopile IR arrays (the applicant's contemporaneous work).
• §102: Close to the sensor architecture, but it is the applicant's own publication (same inventor group) — a potential §102(b)(1)(A) exception may apply if it is the inventors' own disclosure within the grace period, and in any event it does not disclose all claim‑1 limitations. Not anticipatory of claim 1.

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5. Bottom line

1. No single reference appears to anticipate claim 1. Claim 1 is a combination limitation — ≥16×16 array; ≤16 pixels/channel; channels ≥4× rows; split placement between pixels and chip edge; a MUX where a>1; ≥10‑bit ADC; a narrow cutoff window (<3× and ≤8× frame‑rate×pixels); and <200 µm pitch. Each cited reference supplies at most a subset, and the closest two are blocked by specific facts:

   • Kassovski (IRS² 2011) — the best per-channel teaching (LNA + Δ‑Σ ADC + digital LPF + on‑chip RAM) — is 4 rows and 220 µm pitch, so it fails (a) and (m).
   • WO 2017/059970 A1 / US 2018/0283958 A1 (closest overall) published after the '201 priority date and names the identical inventive entity, so it is likely not §102(a)(1) or §102(a)(2) art at all.

2. Most relevant references, ranked, with the claims they most bear on:

   • WO 2017/059970 A1 / US 2018/0283958 A1 (Heimann) — claims 1–7 substantively, but see the §102(a)(2) "another inventor"/common‑ownership caveats.
   • Kassovski et al., IRS² 2011 — claims 1(e), 3, 4, 5 (per-channel LNA + Δ‑Σ ADC + digital LPF + RAM); §103 core.
   • US 9,270,895 B2 (MIT) — claim 1(e) and (f)-adjacent (per-pixel ADC + counter); §103.
   • US 8,179,296 B2 (MIT) and US 2006/0243885 A1 (Denso) — claim 1(c)/(e) (on‑chip array-parallel ADC); §103.
   • WO 2006/122529 A2 / US 2008/0216883 A1 (Heimann) and Panasonic US 2013/0093037 A1 / EP 2 587 234 A1 — claims 1(e), 2, 4 and the pixel‑select switch of 1(j); §103.
   • DE 103 22 860 / US 2007/0187602 A1, US 2007/0194962 A1 (Sony), JP 2004‑170375 A (Horiba), US 8,018,579 B1 (Apple), DE 10 2010 042 108 A1 / US 2011/0174978 A1 (Heimann) — supporting §103 art for individual elements (preamp‑before‑MUX; integrating/≥10‑bit column ADC; single‑preamp difference stage; general thermopile/imaging architecture).

3. Caveats / limits of this analysis. I did not access the full examination record (e.g., the Form‑892/IDS or the EPO/PCT search opinion for the '201 family) in this pass; my mappings are derived from the patent's own citation table plus the reference documents I could retrieve. Two identifiers in the patent's front page deserve literal attention: the specification contains a typo "less than 200 nm" where the claims and the rest of the text say < 200 µm — I have read the claim limitation (m) as < 200 µm per claim 1. Finally, the §102 status of the WO '970 family turns on inventive-entity identity and publication timing, which I flag rather than resolve definitively.

I'll ground the reference contents with a few targeted searches before building the § 103 analysis.

Two strong findings already. Let me check the search report for this application's own PCT filing, which often identifies the most material art.

Obviousness analysis — US 10,739,201 B2 under 35 U.S.C. § 103

0. Framework, ground rules, and two threshold findings

Legal frame. The '201 has an effective filing date of 2017-01-18 (DE 10 2017 100 910 / DE 10 2017 102 833). AIA §§ 102/103 apply. The reference set I am working from is the "Prior art" section of the patent page itself — the 16 patent citations and 6 non-patent citations — supplemented only where I retrieved the reference's own text (which I flag).

A. The patent's own Background is the most useful § 103 document in the file. The specification concedes that every individual building block was known: parallel preamplifiers, per-row low-pass filters (WO 2006/122529 A1), preamplifiers in front of a multiplexer with cyclic power-down (DE 103 22 860 B4), on-chip ADCs, RAM buffering, and — decisively — a 4×16 array with one signal-processing channel per pixel, a 16-bit 2nd-order Delta-Sigma converter, a digital low-pass filter and on-chip RAM (Kassovski et al., IRS 2011). The patent frames the invention as an architecture/arrangement problem, expressly stating that "no measures are specified for a power-saving and space-saving solution." Under KSR, that framing hands a petitioner the motivation and the problem statement.

B. I retrieved Kassovski's actual abstract, and it is stronger than the patent admits. Per the conference record: "We present a 4x16 Thermopile Array (TPA) with 64 signal conditioning channels integrated on a CMOS silicon chip. Each channel consist of a low noise amplifier, a 2nd order Delta Sigma converter and a digital low-pass filter. The digitization resolution of the channel is 16-bit… Next to the 4x16 IR sensors a grid of 80 contact temperature sensors is implemented in the array… The measurement results for all 64 IR and 80 contact temperature sensors are stored in on-chip RAM and can be accessed through standard I2C… the chip supports refresh rates in a very wide range: from 0.5 to 512 Hz… less than 4mA current." (https://www.ama-science.org/proceedings/details/378)

Two corrections to the record worth carrying into any petition:

• The '201 states "each pixel contains 80 contact temperature sensors." Kassovski says a grid of 80 contact sensors in the array, not 80 per pixel. Do not adopt the patent's mischaracterization.
• Kassovski is 2011 art, i.e. § 102(a)(1)/102(b)(1) prior art more than one year before the priority date. It is co-authored by Heimann personnel (B. Forg, F. Herrmann, W. Leneke, J. Schieferdecker), but the § 102(b)(1)(A) inventor-disclosure exception has a one-year grace period and is unavailable. Kassovski is therefore fully available art against its own co-authors' later application.

C. Threshold risk on Heimann's own earlier application. WO 2017/059 970 A1 / US 2018/0283958 A1 (= US 10,578,493 B2; see also US 10,948,355 B2) is, for the '201, at best § 102(a)(2) art (published 2017-04-13 and 2018-10-04, both after the 2017-01-18 critical date; its § 102(a)(2) date is its 2015-10-05 priority). Both are Heimann Sensor GmbH filings with overlapping inventive entities, so § 102(b)(2)(C) common ownership very likely disqualifies it as prior art. Do not lead with it. Where it is used below, it is used as a secondary teaching and its 102(b)(2)(C) exposure is flagged.

D. Claim construction of the low-pass limitation — the highest-leverage point in the case. Claim 1 recites a cutoff "which is less than three times and no more than eight times the value of the product of a frame rate … and a number (a) of pixels per signal processing channel." Read literally, this is a conjunction whose operative bound is "< 3×," with no lower bound. The German priority text, DE 10 2017 102 833 A1 ¶[0037], reads "mindestens das Produkt …, höchstens jedoch dem achtfachen Betrag des Produktes, bevorzugt weniger als dem dreifachen Betrag" — i.e. ≥ 1× the product, ≤ 8×, preferably < 3×. (https://patentimages.storage.googleapis.com/d5/47/a8/443c3d14b21e0e/DE102017102833A1.pdf) The issued claim appears to have dropped the "at least the product" lower bound and collapsed the range into a nonsensical conjunction; dependent claim 4 then re-imports the ≥ 1× floor. This refines — and explains, rather than contradicts — the "internal tension" flagged in the earlier strategic summary, and it may also support an indefiniteness attack. Practical consequence: under the literal issued language this is the EASIEST limitation to meet, not the hardest (any cutoff below 3× the product reads on it), while the patent's own specification says the "minimum necessary" noise bandwidth is exactly frame-rate × a. Plead both constructions; the § 103 outcome is the same either way.

(One drafting artifact to ignore: the description's stray "less than 200 nm" at ¶ on pixel spacing. The claim says 200 µm, the German priority says µm, and every other passage says µm. Nothing should be built on the nm variant.)

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1. Claim 1 mapped against Kassovski alone

Only three gaps: array size (row count), pitch, and the split placement. That is an unusually tight starting position, and it is corroborated by documentary evidence: the international search report for Heimann's own earlier application PCT/EP 2016/065844 cited Kassovski as an "X" reference against claims 1–11 — i.e. a national-office examiner already concluded that Kassovski, alone, deprives the family's core claim of novelty/inventive step. (https://patentimages.storage.googleapis.com/e0/a4/75/f11b639a14a6c9/JP2018531399A.pdf)

Also note how little work the "channels ≥ 4× rows" limitation does. With a = 1 and the claimed 16 columns, N = 16 × rows, which is inherently ≥ 4 × rows. Once a POSA adopts Kassovski's one-channel-per-pixel architecture in any array of ≥ 4 columns, this numerical limit is satisfied automatically. There is no criticality data anywhere in the '201 tying the 4× multiple to a change in kind.

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2. Ground 1 — Kassovski + Kimata (2013) + Schnorr (2015), with the '201's own admissions as the motivation

Combination: Kassovski in view of Kimata, "Trends in small-format infrared array sensors," IEEE Sensors 2013, and Schnorr et al., "New miniaturized Thermopile IR Arrays with medium resolution," IRS² 2015 (both cited on the patent page as non-patent art), plus the applicant's own admissions in the '201 Background.

Motivation, articulated as a POSA would:

1. The '201's Background admits the market direction: arrays of "16×16, 32×32, 64×64, 128×128" on one chip, with pixel side lengths driven "to 100 µm, or even down as far as 25 µm," and states that "a lower pitch allows more pixels SE to be accommodated on a sensor chip of given size … to obtain a higher optical resolution capacity." That is an applicant admission of (a) the design goal and (b) the predictable consequence of pitch reduction.
2. Kimata 2013 is a survey of exactly this trend; Schnorr et al. 2015 (again Heimann-authored, and again § 102(a)(1) art predating the 2017 priority) documents miniaturized medium-resolution thermopile arrays. Both supply the reason to extend a 4×16 row array to a two-dimensional ≥16×16 field.
3. Going from 4 rows to ≥16 rows while keeping the per-pixel channel architecture is a scaling of a known architecture, producing nothing more than the predictable benefit of more pixels and more parallel channels — the KSR "combination of familiar elements according to known methods" with "predictable results."
4. Reducing the 220 µm row spacing to below 200 µm — a <10% reduction — is routine design optimization, squarely within the "known design incentive" to shrink pitch for cost and resolution, and the '201 offers no evidence of criticality at 200 µm.

Predictable-results check. The only asserted advantage of the arrangement is thermal-resolution improvement. The specification itself derives it: noise scales with the square root of noise bandwidth, so per-pixel channels yield √(m·n) improvement — hence the claimed "factor of 4" (16×16), "5.5" (32×32), "8" (64×64) and "11" (128×128). That is arithmetic, not an unexpected result, and it cannot rebut obviousness. What remains (placement, pitch, array size) is layout, and layout is where the patent's real problem — routing ~256 channels for a 16×16 array at a = 1, a point the specification concedes ("32 instead of two channels would be needed per side") — lives.

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3. Ground 2 — adding a teaching for the split placement (the only genuinely soft limitation)

The split ("one portion … in the intermediate space between the pixels and another portion … in the outer edge area … together with other electronics") is the limitation most likely to require a second reference. Viable secondary references, in descending order of cleanliness:

• Denso, US 2006/0243885 A1 (cited on the patent page). It discloses an image sensor in which "the light collection array and the A/D converters are arranged on one chip," achieved by "dividing the image sensor array into a plurality of sub-arrays, which are each assigned to an A/D converter with an associated sub-array controller." A distributed sub-array converter/controller architecture necessarily places conversion electronics among the pixel field, with the remainder at the periphery. Motivation: Denso's stated aim is "improved image sensor with small dimensions" — the same objective as the '201.
• Panasonic, US 2013/0093037 A1 / EP 2 587 234 A1 (both cited on the patent page). Each IR detector in the array has a MOS transistor as a pixel selection switch plus vertical reading lines and horizontal signal lines — i.e. readout circuitry physically interleaved with the pixels, which is precisely the "intermediate space between the pixels" teaching, and it also supplies the multiplexing/selection element.
• MIT, US 8,179,296 B2 and US 9,270,895 B2 (both cited). The former connects the sensor array to the input of an A/D converter array and is expressly said to serve "IR-image sensor applications with high areal resolution (small pixels) and high signal-to-noise ratio"; the latter assigns each pixel an ADC and an m-bit counter. Both teach converter-per-pixel (or per-column) placement within the imaging field, and both are motivated by exactly the '201's goals (small pixels, high SNR).
• Heimann's WO 2017/059 970 A1 / US 2018/0283958 A1 / US 10,578,493 B2 — explicitly recites edge-region channel placement and (in its CN counterpart, claims 11–13) channels placed on a separate chip under the sensor chip. But see § 102(b)(2)(C) risk above. Use it as a secondary teaching only, and only if you can show non-common ownership (e.g. differing inventive entity or evidence the subject matter was not commonly owned at the time the claimed invention was made).

Motivation to combine: the '201 itself supplies it — "the power losses of the various modules should be distributed over the sensor chip SP as homogeneously and symmetrically as possible," to avoid the admitted consequence of self-heating and "thermal shock" of the thermopile elements. Splitting channels between the inter-pixel gaps and the chip periphery is the ordinary way to satisfy two admitted constraints simultaneously (per-pixel channels + small pitch → no room at one location only).

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4. Ground 3 — the alternative architecture line

WO 2006/122529 A2 (Heimann) + Kassovski + US 8,179,296 B2. WO 2006/122529 discloses the membrane-etched thermopile array with "preamplifiers with low-pass filters … for at least every fourth, preferably for every column or row of sensor elements" — i.e. the preamp-plus-LPF channel, at a channel count of ~1× rows (which alone fails the ≥ 4× limit). Kassovski supplies the teaching that per-pixel channels with on-chip ΔΣ ADCs, a digital LPF and RAM are practical at 64 channels; MIT '296 supplies the A/D-converter-array readout. Motivation: the '201's own bandwidth algebra (noise ∝ √bandwidth; one amplifier per array ⇒ m·n × frame rate of bandwidth) makes it obvious to multiply channel count until each channel sees few pixels — which is the whole of the "≤16 pixels/channel" and "≥4× rows" limitations.

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5. Dependent claims

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6. Rebuttals the patent owner will press

• "DE 103 22 860's cyclic power-down doesn't work without band-limiting." True but irrelevant: WO 2006/122529 is the band-limiting teaching, and the § 103 combination supplies it. A reference cannot "teach away" when the combination cures the very deficiency alleged. KSR / In re Etter logic.
• "Kassovski is a 4-row line array, not a 2D imager." The patent's own Background answers this: it acknowledges the 16-row/64-row scaling arithmetic and identifies the obstacle as layout, not feasibility — then claims the layout fix.
• "Unexpected thermal-resolution gain." Not unexpected; √bandwidth arithmetic (above). No objective indicia (commercial success, licensing, copying, industry praise, failure of others) appear in the record.
• "Criticality of 200 µm / 4× rows / 3×." No data. Numbers chosen without disclosed criticality are classic obvious-to-optimize territory.
• Watch for: the '201's Background statements that "no measures are specified" for power/space savings. These are attorney characterizations of the art, not evidence, and are undercut by the on-chip channel of Kassovski and the per-row LPF of WO 2006/122529.

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7. Bottom line

Strongest § 103 case: Kassovski et al. (IRS 2011) as primary reference, in view of Kimata 2013 and/or Schnorr 2015 for the ≥16×16 array and the sub-200 µm pitch, in further view of Denso US 2006/0243885 A1 (or Panasonic EP 2 587 234 A1 / US 2013/0093037 A1) for splitting the channels between the inter-pixel intermediate space and the chip edge. Kassovski alone reaches every other limitation of claim 1, including the ≥ 10-bit ADC, the ≤ 16 pixels per channel, the ≥ 4× rows channel count, the per-channel RAM and the low-pass bound. Claims 3 and 5 are the most exposed dependents (ΔΣ conversion and in-converter filtering are literally disclosed). Claim 7 is the vulnerable flank on the patentee's side; the split-placement limitation of claim 1 is the vulnerable flank on the petitioner's.

Confidence and caveats (do not omit):

1. Medium-high on the mapping and motivation; I have not read the full texts of every listed reference. Kassovski's abstract and the PCT/EP 2016/065844 ISR are quoted from retrieved sources; for WO 2006/122529 A2, DE 103 22 860 B4, US 2006/0243885 A1, US 8,179,296 B2, US 9,270,895 B2 and EP 2 587 234 A1 I have relied on the '201's own characterizations plus the reference summaries returned by search. Pull the full texts and the figures before filing.
2. Resolve the § 102(b)(2)(C) question before relying on WO 2017/059 970 A1 / US 2018/0283958 A1 — pull the assignment records and inventive entities.
3. Get the '201's own file wrapper (USPTO PatentCenter) to see whether the examiner cited Heimann's own earlier application and how the applicant distinguished it; and obtain the ISR/written opinion for PCT/EP 2018/051166 (WO 2018/134288 A1), which is the closest thing to an examiner's own § 103 map of this claim set and which I was unable to retrieve.
4. No PTAB estoppel, no prior adjudication, no narrowing amendment — consistent with the earlier sections of this analysis; every limitation above remains fair game in a first-instance IPR.