Prior art

Here is an analysis of the most relevant prior art for US Patent 10115439, identified from the examiner-cited patent references within the provided patent text.

Most Relevant Prior Art for US Patent 10115439

The most relevant prior art identified are those patent citations explicitly marked as "Cited by examiner" within the US10115439 patent document.

1. US20060107186A1

• Full Citation: US20060107186A1, International Business Machines Corporation, "System, method and storage medium for providing a high speed test interface to a memory subsystem".
• Publication/Filing Date:
  • Publication Date: 2006-05-18
  • Priority Date: 2004-10-29
• Brief Description: This patent describes a system and method primarily focused on providing a high-speed test interface for memory subsystems. It discloses memory devices with on-die termination (ODT) circuitry and a memory controller or test device that can provide a "termination control value" to set the termination. The disclosure refers to "dynamically adjustable on-die termination" and "programmable termination" within a memory system for testing purposes.
• Potential Anticipation (35 U.S.C. § 102):
  US20060107186A1, published on May 18, 2006, is prior art to US10115439 (priority date December 21, 2006) under 35 U.S.C. § 102(b). It generally anticipates the concept of dynamic and programmable on-die termination in memory devices, where a memory controller can influence ODT settings via a "termination control value". However, US10115439's independent claims (Claims 1, 12, 20) specify that the memory controller stores register values in the memory device to selectively enable application of ODT impedances for chip select signals and clock signals, in addition to general command/address signals. While US20060107186A1 discusses setting impedance values, it does not explicitly disclose the granular and selective enabling of ODT for these specific control signal types (chip select and clock) through register values stored in the memory device by the controller for operational rather than purely test scenarios. Therefore, while it anticipates the broad idea of dynamic ODT configuration by a controller via values, it likely does not fully anticipate the specific combination of elements and control mechanisms claimed in US10115439 for selectively enabling ODT on chip select and clock signals using register values stored in the memory device.

2. US6675272B2

• Full Citation: US6675272B2, Rambus Inc., "Method and apparatus for coordinating memory operations among diversely-located memory components".
• Publication/Filing Date:
  • Publication Date: 2004-01-06
  • Priority Date: 2001-04-24
• Brief Description: This patent describes a memory system and methods for coordinating operations among multiple memory components. It discusses a memory controller communicating various signals, including control and address signals, to memory components. The abstract explicitly mentions "an on-die termination circuit selectively connectable to one or more signal lines of a data bus" within the memory components.
• Potential Anticipation (35 U.S.C. § 102):
  US6675272B2, published on January 6, 2004, is prior art to US10115439 (priority date December 21, 2006) under 35 U.S.C. § 102(b). It broadly discloses memory systems and on-die termination. However, a key distinction from US10115439 is its explicit focus on "on-die termination circuit selectively connectable to one or more signal lines of a data bus". In contrast, US10115439 is specifically directed to on-die termination of address and command signals (RQ signals), which include chip select and clock signals. While US6675272B2 mentions control and address signals, it does not disclose the specific mechanism of a memory controller storing register values in the memory device to selectively enable ODT for distinct command and address signals such as chip select and clock, as detailed in the claims of US10115439. Therefore, it is unlikely to anticipate the specific subject matter of US10115439's claims.