Obviousness

To analyze the obviousness of US patent 10115439 under 35 U.S.C. § 103, we will examine combinations of prior art references that disclose the features claimed in US10115439. The patent generally claims a memory controller configured to program register values in a memory device to control on-die termination (ODT) impedances for address, command, chip select, and clock signals, particularly in a fly-by topology.

Key Features of US10115439's Claims:
The independent claims (Claims 1, 12, and 20) of US10115439 focus on a memory controller that:

• Drives command/address (CA) signals, chip select (CS) signals, and clock signals.
• Stores/programs register values in the memory device to control ODT impedances for these signals.
• The register values can selectively enable ODT for CS and clock signals.
• The register values can specify impedance values for the ODT.

Relevant Prior Art References and Their Disclosures:

Based on the provided patent text's "Citations" and "Family Cites Families" sections, the following references are highly relevant:

1. US7142461B2 (Micron Technology, Inc.): "Active termination control though on module register". This patent directly teaches the control of active termination using registers.
2. US6356106B1 (Micron Technology, Inc.): "Active termination in a multidrop memory system". This patent addresses the need for active termination in multidrop memory systems, which is explicitly identified as "fly-by" topology in US10115439.
3. US20050228912A1 (Walker Clinton F): "Memory address bus termination control". This reference focuses on the control of termination specifically for memory address bus signals.
4. US7123047B2 (Intel Corporation): "Dynamic on-die termination management". This patent suggests dynamic control (enable/disable) of ODT.
5. US5666078A (International Business Machines Corporation): "Programmable impedance output driver". This patent teaches the concept of programmable impedance.
6. WO1998004041A1 (Kaplinsky Cecil H): "Programmable dynamic line-termination circuit". This reference also teaches programmable and dynamic line termination.
7. KR100422451B1 ([[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.)): "method for controlling on-die termination and control circuit therefore". This broadly covers ODT control.
8. US10115439's own disclosure (Background/Description): The patent itself acknowledges the existence of certain concepts as known or obvious, such as the general termination of command, address, and control (RQ) signals, and the need for different impedance values for different signal classes. It also mentions that register control can override pin-based enable methods.

Obviousness Combinations and Rationale:

A person having ordinary skill in the art (POSITA) in semiconductor memory design, faced with known challenges in signal integrity and power consumption in high-speed memory systems, particularly those using fly-by (multidrop) topologies, would have been motivated to combine the teachings of the prior art references to arrive at the claimed invention.

Combination 1: US7142461B2 + US6356106B1 + US20050228912A1 + General Knowledge

• Claim 1 Analysis: This claim describes a memory controller storing register values in a memory device to control ODT impedances for CA signals and selectively enabling chip select ODT impedance via register values.

  • US6356106B1 discloses active termination in a multidrop (fly-by) memory system. A POSITA would be motivated to apply termination to address and command signals in such a topology to improve signal integrity, as reflections on these critical control lines are a known problem, as acknowledged in the background of US10115439.
  • US20050228912A1 specifically teaches controlling termination for memory address bus signals. It would be an obvious design choice for a POSITA to extend this control to chip select signals, which are closely related control signals for memory access and often routed similarly (as noted in US10115439, "chip select (CS) signals may also be routed with the same fly-by connection topology as the CA signals").
  • US7142461B2 teaches "active termination control though on module register". A POSITA, having identified the need for termination for CA and CS signals in a fly-by system, would be motivated to use this known and flexible method of register-based control to manage the ODT settings in the memory device. This provides the mechanism for the memory controller to "store register values, in the memory device" to control the ODT.
  • The "selective enablement" of chip select ODT impedance via register values would be an obvious design choice for power management and signal integrity optimization, as dynamic termination is a well-known concept (e.g., US5467455A "dynamic bus termination", US7123047B2 "Dynamic on-die termination management"). Enabling termination only when needed for specific signals (like a selected chip select) conserves power and can improve signal quality.
  • Motivation to Combine: The motivation for a POSITA would be to achieve robust and flexible signal integrity management for critical control signals (CA, CS) in high-speed, multidrop memory architectures while optimizing power consumption. Register-based control (US7142461B2) offers programmability and flexibility that would be highly desirable when implementing active termination (US6356106B1) for specific bus signals like address and chip select (US20050228912A1).

• Claim 2 Analysis (adds clock signal termination): This claim adds a circuit to drive a clock signal, and includes register values to selectively enable clock signal ODT impedance.

  • Building on the combination for Claim 1, it is well-established general knowledge in the art that clock signals, like CA and CS signals, are critical for timing and require proper termination to maintain signal integrity and prevent reflections, especially in high-speed memory systems. US10115439 itself notes that clock signals (CK/CKN) are "RQ signals" and are often terminated.
  • Motivation to Combine: A POSITA would naturally extend the already established register-based, selectively enabled ODT control (from Claim 1's combination) to clock signals. The goal would be to provide a comprehensive termination solution for all critical "RQ" (command, address, control, and clock) signals on the memory bus, using a consistent and flexible control mechanism.

• Claim 3 Analysis (adds specifying impedance value for clock ODT): This claim specifies that the register values can define the impedance value for the clock signal ODT.

  • US5666078A teaches a "Programmable impedance output driver", and WO1998004041A1 teaches a "Programmable dynamic line-termination circuit". These references establish the concept of programming termination impedance values.
  • Motivation to Combine: Given the inclusion of register-controlled ODT for clock signals (as per Claim 2), a POSITA would be motivated to make the value of that termination impedance programmable via registers. This allows for fine-tuning the termination impedance to optimize signal integrity based on system characteristics, environmental conditions, or different operating modes, a benefit explicitly recognized in US10115439 ("the impedance value of the termination may be determined by signal integrity studies, and may be different for different 'classes' of signals").

• Claim 5 Analysis (adds ODT enable signal): This claim adds a circuit to drive an ODT enable signal (e.g., first/second voltage) to enable/disable ODT for CA signals.

  • US7123047B2 teaches "Dynamic on-die termination management", implying an enable/disable mechanism for ODT. Many prior art references (e.g., US5467455A, US6894691B2, WO2004061690A2) disclose dynamic termination, which inherently involves enabling and disabling termination.
  • Motivation to Combine: While register values can control enabling/disabling, a dedicated ODT enable signal (e.g., a pin-based signal like the CAODT pin 16 in US10115439) provides a direct and fast mechanism for dynamic control. A POSITA would be motivated to integrate such a signal, alongside register control, to achieve efficient power management and real-time signal integrity adjustments. This aligns with the "power saving advantage" described in US10115439 for dynamically controlling termination.

• Claim 6 Analysis (adds override register values): This claim includes register values to override the ODT enable signal (from Claim 5).

  • US10115439's own description states, "Other embodiments may also utilize register control, either as an override, or as a replacement, for the enable pin configuration method. For example, in one embodiment register fields may be utilized to override the RQ ODT enable". This indicates that the concept of using register control as an override for a pin-based enable method was considered known or an obvious alternative.
  • Motivation to Combine: A POSITA, seeking to provide maximum flexibility and control, would find it obvious to implement register-based override capabilities for a pin-driven ODT enable signal. This allows for both dynamic, fast control via a pin and more persistent, configurable control via registers, giving system designers different levels of authority over the termination settings.

• Claim 10 Analysis (different register values for CA and CS ODT): This claim specifies that register values for CA signal ODT impedance are different from those for selectively enabling chip select ODT impedance.

  • US10115439's own description states, "the impedance value of the termination... may be different for different 'classes' of signals. For example, the chip select signal lines may have a different impedance value as compared to the address signal lines".
  • Motivation to Combine: Given the established understanding that different signal types may require different termination characteristics, it would be an obvious design choice for a POSITA to use separate (different) register fields or values to control the termination of distinct signal groups (like CA vs. CS). This allows for independent optimization of signal integrity and power consumption for each class of signal, maximizing system performance and efficiency.

Conclusion:
Claims 1, 2, 3, 5, 6, and 10 (and by extension, their dependent claims and similar independent claims like 12 and 20) of US10115439 would have been obvious to a person having ordinary skill in the art at the time of the invention. The motivation to combine the various prior art references would stem from well-known design goals in memory systems, such as improving signal integrity, reducing power consumption, and providing flexible and programmable control over critical signal parameters like termination impedance in complex bus topologies like fly-by architectures. The patent itself articulates many of these motivations, implicitly acknowledging them as desirable outcomes or known challenges in the art.