US 10056902

US patent 10056902, titled "On-die termination control," was issued on August 21, 2018, from an application filed on April 28, 2017. The original assignee was Rambus Inc., with the current assignee listed as Signal LLP. The inventors are Kyung Suk Oh and Ian P. Shaeffer.

Abstract:
A memory control component outputs a memory write command to a memory IC and also outputs write data to be received via data inputs of the memory IC. Prior to reception of the write data within the memory IC, the memory control component asserts a termination control signal that causes the memory IC to apply to the data inputs a first on-die termination impedance during reception of the write data followed by a second on-die termination impedance after the write data has been received. The memory control component deasserts the termination control signal to cause the memory IC to apply no termination impedance to the data inputs.

Plain-Language Overview of Independent Claims:

• Claim 1 (Integrated Circuit Device): This claim describes an integrated circuit device (e.g., a memory controller) that controls a Dynamic Random Access Memory (DRAM). The device includes a first interface to send a write command to the DRAM (indicating data will be received), a chip-select signal (to make the DRAM respond), and commands to store a digital control value in a DRAM register. This digital control value specifies a termination impedance value for the DRAM's data interface. The impedance is connected before the write data arrives (based on a set time after the write command) and disconnected after the write data is received. The device also has a second interface to send the actual write data to the DRAM's data interface.

• Claim 11 (Method of Control): This claim describes a method for controlling a DRAM. The method involves transmitting a write command to the DRAM, along with a chip-select signal to ensure the DRAM responds. It also includes transmitting commands to store a digital control value in a DRAM register. This digital control value dictates the termination impedance that the DRAM should apply to its data interface in response to the chip-select signal and write command. Crucially, the termination impedance is connected to the data interface at a predetermined time before the write data arrives and is then disconnected after the write data has been received. Finally, the method includes transmitting the write data to the DRAM's data interface.

Litigation Information:
According to the patent's Google Patents page, there is active litigation related to this patent. US cases have been filed in the Texas Western District Court (case 7:26-cv-00095) and the Texas Eastern District Court (case 2:26-cv-00093), both in 2026. There is also mention of the first worldwide family litigation filed. No specific CAFC 2026 dockets were found for patent 10056902 in the search results.