US 9412758

Patent Overview — US 9,412,758 B2

Title: Semiconductor on insulator (SOI) structure with more predictable junction capacitance and method for fabrication

Assignee / Inventors: Original assignee Newport Fab LLC (dba Jazz Semiconductor); inventors Robert L. Zwingman and Marco Racanelli.

Key dates: Priority date 2007-12-10; application US12/286,471 filed 2008-09-29; published as US20090146210A1 on 2009-06-11; granted 2016-08-09. Anticipated expiration 2028-09-29 (per source listing).

Purpose / Problem: Conventional SOI wafers (device layer, buried oxide layer, bulk semiconductor layer) isolate transistors well, but in a conventional SOI structure the source and drain extend through the device layer to the buried oxide, leaving little or no semiconductor junction and therefore little or no junction capacitance. That absence of predictable junction capacitance prevents reuse of well-understood bulk-silicon design methodologies, device models, and design kits, forcing reliance on newer, less developed SOI-specific design kits.

Plain-language scope (from supplied text): The invention is directed to an SOI structure and fabrication method providing more predictable junction capacitance. The disclosure describes an SOI structure comprising device layer, buried oxide layer, and bulk semiconductor layer, with trenches (e.g., LOCOS or STI-filled) extending through the device layer to the buried oxide, and a transistor (source, gate, drain) formed in the isolated device-layer island. Exemplary dimensions given: device layer ~800 Å, buried oxide ~1200 Å, bulk layer ~725 µm with ~3–20 ohm-cm resistivity. Figures 2, 3, 5, and 6 show embodiments; FIG. 4 is a fabrication flowchart. The source notes SOI wafers may be made by wafer-bonding/annealing/grinding or oxide-growth, hydrogen-implant, and thermal-shock methods.

Source: https://patents.google.com/patent/US9412758/en

What the excerpt does not establish: It does not set out the specific claims or their exact language and scope; it does not detail the distinguishing structural or process features of the disclosed embodiments relative to the conventional structure beyond the general problem statement; it does not identify prior art references; and it does not provide prosecution history, claim construction, or legal conclusions on validity or infringement. Figures referenced are not fully reproduced in the excerpt.