US 7342266

Patent Overview — US7342266B2

Title: Field effect transistors with dielectric source drain halo regions and reduced Miller capacitance

Patent number: US7342266B2 (application US11/306,710)

Assignee: International Business Machines Corporation (original assignee; assignment recorded 2006-01-09, naming inventors Belyansky, Chidambarrao, and Gluschenkov)

Key dates (as listed): Priority/filing date 2006-01-09; publication of US20070161169A1 on 2007-07-12; granted/publication date 2008-03-11; adjusted expiration 2026-03-16. Legal status shown as "Expired – Fee Related."

Purpose: The invention relates generally to semiconductor device processing, and more particularly to a structure and method for reducing short channel effects and parasitic capacitances in field effect transistors (FETs).

Plain-language scope (from the excerpt): The patent addresses problems that arise as FET gate lengths shrink — namely short channel effects (e.g., increased drain-to-source leakage in the off state) and edge effects, notably gate-to-source/drain capacitance. That capacitance includes direct overlap (C_do), outer fringe (C_of), inner fringe (C_if), and gate-to-contact stud (C_stud) components, the first three collectively termed overlap capacitance (C_ov). A portion of this parasitic fringe capacitance can be amplified as Miller capacitance, described as an amplification of gate-to-drain capacitance in CMOS applications. The excerpt notes overlap capacitance can account for as much as about 50% of overall capacitance at a scaled gate length of roughly 30 nanometers. The title indicates dielectric source/drain halo regions are used to reduce Miller capacitance while the device maintains low series resistance between channel and source/drain.

Source: https://patents.google.com/patent/[US7342266](/patent/US7342266)/en

Not established by this excerpt: The excerpt is partial and truncated mid-sentence ("...whil"). It does not provide the full claims, the complete detailed description, specific materials or process steps for forming the dielectric halo regions, drawing contents, or the specific structures recited in the claims. It also does not establish the accuracy of the listed dates, inventorship, assignee, or legal status, which the source itself labels as assumptions or non-legal conclusions.