Invalidity dossier
US 6882025
Strained-channel transistor and methods of manufacture
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Added 9/23/2026, 3:33:46 PM
Active provider: DeepSeek · deepseek-flash
Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Patent Overview: US 6,882,025 B2
Title: Strained-channel transistor and methods of manufacture
Patent number: US 6,882,025 B2 (application US 10/423,513)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC)
Inventors: Yee-Chia Yeo, Chih-Hsin Ko, Wen-Chin Lee, Chenming Hu
Key dates:
- Priority/filing date: 2003-04-25
- Publication date (as granted): 2005-04-19
- Legal status listed: Expired – Lifetime; anticipated expiration 2023-04-25
- Related priorities/publications noted: TW092127405A, CN2003101019562A, SG200402719A, US 2004/0212035 A1, and continuations US 7,052,964 B2 and US 8,569,146 B2
Purpose: The patent addresses strained-channel transistors and their manufacture. Per the classification data, it concerns arrangements for exerting mechanical stress on the crystal lattice of FET channel regions, specifically stress induced via lateral device isolation regions such as shallow trench isolation (STI), including integration into CMOS fabrication and formation of isolation regions.
Plain-language scope (from the supplied excerpt): The disclosure relates to field-effect transistors whose channel region is mechanically stressed to modify performance, and to methods of making such devices where the stress originates in or is applied through the lateral isolation structures (e.g., STI) adjacent the channel. The excerpt also indicates applicability to complementary (CMOS) device integration and to silicon-based (including SiGe) process technologies.
Source: https://patents.google.com/patent/US6882025/en
What the excerpt does not establish: The supplied text omits the abstract, specification, and full claim language, so the precise claimed scope, specific process steps, materials, and stress magnitudes cannot be verified from it. It also does not establish inventorship disputes, ownership changes beyond the recorded assignment, validity, enforceability, or the content of any prior art. The legal status and priority dates shown are expressly identified by the source as assumptions, not legal conclusions.
Generated 10/1/2026, 9:51:29 PM
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Litigation summary
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Proceedings on file (0)
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No PTAB proceedings on file. This patent has not been challenged via IPR, PGR, or CBM. The absence is itself a signal — well-asserted patents eventually attract IPRs. The LLM analysis below may surface filings the ODP feed hasn’t indexed yet.
PTAB challenges
AIA trial proceedings at the USPTO Patent Trial and Appeal Board — IPR, PGR, and CBM. Petitioners, judge panels, claim-level invalidation outcomes from Final Written Decisions, and Federal Circuit appeals. The single most important defensive datapoint after litigation history.
Assignment history
Inventors, original assignee, and the chain of ownership recorded with the USPTO — including the correspondent attorney who recorded each assignment, since shell-LLC chains often share one repeat-player attorney even when the entity names look unrelated. Surfaces NPE / patent-troll patterns: shell-entity transfers, known asserters in the chain, repeat correspondent fingerprints, pre-litigation assignments, and bankruptcy fire-sales.
Prior art
Earlier patents, publications, and products that may anticipate or render the claims unpatentable.
Obviousness
Combinations of prior art that suggest the claimed invention would have been obvious under 35 U.S.C. § 103.
Extensions
Patent term adjustments, term extensions, continuations, divisionals, family members, and expiration dates.
Derivative works
Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.