US 6855964

US6855964 — Overview

Title: Triggering of an ESD NMOS through the use of an N-type buried layer

Patent number: US6855964B2
Application number: US10/280,313
Inventor: Ronald B. Hulfachor (assignment names "HULFACHOR, RONAL B." as assignor)
Original assignee: Fairchild Semiconductor Corp.; current assignee listed as Semiconductor Components Industries LLC
Priority date: 2001-11-02 | Filed: 2002-10-25 | Granted/Published: 2005-02-15
Status as listed: Expired – Fee Related; anticipated expiration 2022-10-25

Purpose. The patent addresses protection of integrated circuits from electrostatic discharges (ESD's). Because dielectric layers and isolation barriers may be harmed by voltage alone, and modern ICs may be harmed by levels only a few volts above typical Vcc, there is a need for on-chip ESD devices that "reliably trigger at fairly low levels."

Plain-language scope. An ESD NMOS device has an output contact connectable to circuitry to be protected. A P-type well is formed, and at least two—preferably an odd number—of N-type structures are diffused into it. N-type buried layers (NBL's) substantially bridge the gaps between those structures, with openings opposite the N-type structures. Gate structures (polysilicon or metalization) are formed over the N-type structures, insulated from them, substantially bridging the gaps. The stated effect is to increase P-well resistivity by creating a depletion zone during a positive ESD event and to raise the P-well voltage as current travels through lateral NPN transistors that have broken down in snap-back—both acting to lower the ESD trigger voltage. An N-type tap connects the NBL's to the surface; the NBL's are described as finger-like strips, not a full blanket buried layer, so they will not shield the drain from receiving large currents.

Source: https://patents.google.com/patent/US6855964/en

Not established by this excerpt. The excerpt is expressly partial and omits claim text, so no claim scope, claim count, or dependency can be confirmed. It also does not establish the full specification, figures' details, any litigation, validity, or prior-art analysis, and the legal-status/assignee entries are stated by the source itself to be assumptions, not legal conclusions.