Invalidity dossier
US 6836172
Semiconductor switch apparatus including isolated MOS transistors
Current assignee: Renesas Electronics Corp
Added 9/23/2026, 2:48:29 PM
Active provider: DeepSeek · deepseek-flash
Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Patent Overview — US 6836172 B2
Title: Semiconductor switch apparatus including isolated MOS transistors
Patent number: US 6836172 B2 (application US10/443,007)
Inventor: Tomonori Okashita
Original assignee: NEC Compound Semiconductor Devices Ltd. Current assignee listed as Renesas Electronics Corp.
Key dates: Prior art date 2002-05-30; filing date 2003-05-22; publication of US20030222704A1 on 2003-12-04; granted 2004-12-28; anticipated expiration 2023-05-22. Legal status shown as "Expired – Fee Related."
Purpose and plain-language scope: The source text is largely bibliographic and classification data rather than full claim language, so the described scope rests on the title and classification record. The title indicates a semiconductor switch apparatus built from MOS transistors that are isolated from one another. The classification record is consistent with this: H03K17/6871 covers "the output circuit comprising more than one controlled field-effect transistor" within electronic switching using field-effect transistors; H10D84/0151 addresses manufacture of isolation regions; H10W10 groupings cover isolation regions in semiconductor bodies between components, including dielectric isolation, silicon-on-insulator (SOI) isolation, and PN-junction isolation; H10D86/201 covers devices on SOI substrates. Taken together, these indicate an integrated switching circuit in which multiple MOS transistors are separated by isolation structures. The listed prior-art keywords are "terminal," "power supply," "MOS transistor," "semiconductor switch," and "switch apparatus," suggesting the apparatus involves switching between power-supply and terminal connections.
Source: https://patents.google.com/patent/US6836172/en
What the excerpt does not establish: The supplied text does not include the abstract, claims, detailed description, drawings, or any prior-art references, so claim scope, specific circuit topology, operating voltages, and technical advantages are not established. The assignee, status, and date entries are expressly noted in the source as assumptions or non-legal conclusions, and this overview repeats them only as listed. No litigation, ownership-transfer, validity, or prior-art analysis is made here.
Generated 10/1/2026, 9:51:56 PM
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Litigation summary
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Proceedings on file (0)
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PTAB challenges
AIA trial proceedings at the USPTO Patent Trial and Appeal Board — IPR, PGR, and CBM. Petitioners, judge panels, claim-level invalidation outcomes from Final Written Decisions, and Federal Circuit appeals. The single most important defensive datapoint after litigation history.
Assignment history
Inventors, original assignee, and the chain of ownership recorded with the USPTO — including the correspondent attorney who recorded each assignment, since shell-LLC chains often share one repeat-player attorney even when the entity names look unrelated. Surfaces NPE / patent-troll patterns: shell-entity transfers, known asserters in the chain, repeat correspondent fingerprints, pre-litigation assignments, and bankruptcy fire-sales.
Prior art
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Obviousness
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Extensions
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Derivative works
Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.