Invalidity dossier

US 6823409

Coherency control module for maintaining cache coherency in a multi-processor-bus system

Current assignee: Valtrus Innovations Ltd.

Added 9/17/2026, 12:49:25 AM

At a glanceNo PTAB challenges1 lawsuit on fileasserted by Valtrus Innovations Ltd.

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Patent summary

Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.

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Patent Overview — US 6,823,409 B2

Title: Coherency control module for maintaining cache coherency in a multi-processor-bus system

Patent number / application: US 6,823,409 B2; Application US 09/965,894

Inventors: Phillip M. Jones; Paul B. Rawlins

Assignee of record in the excerpt: Original assignee Hewlett Packard Development Co LP; current assignee listed as Valtrus Innovations Ltd and Hewlett Packard Enterprise Development LP. The excerpt also shows assignment to Compaq Information Technologies Group, L.P. (2001) and later to Hewlett-Packard Development Company, L.P. (2004).

Dates: Priority/filing date 2001-09-28; publication of US 2003/0070016 A1 on 2003-04-10; patent publication date 2004-11-23. Status listed as expired – lifetime, with adjusted expiration 2022-11-16.

Purpose (from the text): The invention "relates generally to a multi-processor-bus memory system and, more particularly, to an efficient mechanism for filtering processor cache snoops in a multi-processor-bus-system." It addresses cache coherence, where separate processor caches sharing common memory must be kept coherent, and where a host controller "must maintain memory coherency throughout all the processor caches," requiring snoop cycles on non-originating buses.

Plain-language scope: The disclosed approach uses a snoop filter to minimize snoop cycles on other buses. To maintain efficiency, the snoop filter should allow data lookup from tag RAMs quickly enough to determine the proper snoop response on the processor bus within a minimal number of clock cycles. The figures described include an exemplary multi-processor-bus computer system (eight microprocessors in a split bus configuration), a snoop filter and a more detailed embodiment thereof, and a "two dimensional doubly linked list structure."

Source: https://patents.google.com/patent/US6823409/en

What the excerpt does not establish: It provides no claim text, so the precise claimed scope is not shown. It does not establish validity, enforceability, or the merits of any litigation. It gives no complete description of the linked-list structure, snoop-filter operation, or the omitted portions of the specification. Assignee and legal-status entries are expressly disclaimed as assumptions, not legal conclusions.

Generated 10/1/2026, 10:03:21 PM

Cases on file (1)

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Specific litigation cases in our database that name US patent 6823409. The free-form analysis below may also discuss cases beyond this list.

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Proceedings on file (0)

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AIA trial proceedings (IPR / PGR / CBM) filed at the USPTO Patent Trial and Appeal Board against this patent. Sourced from the USPTO Open Data Portal and refreshed every six hours; each proceeding number deep-links to the PTAB E2E docket.

Current assignee: Valtrus Innovations Ltd.

No PTAB proceedings on file. This patent has not been challenged via IPR, PGR, or CBM. The absence is itself a signal — well-asserted patents eventually attract IPRs. The LLM analysis below may surface filings the ODP feed hasn’t indexed yet.

PTAB challenges

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Assignment history

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Prior art

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Obviousness

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Extensions

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Derivative works

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This patent in court (1)

1 tracked lawsuit name US 6823409.