Invalidity dossier
US 6737682
High voltage tolerant and low voltage triggering floating-well silicon controlled rectifier on silicon-on-insulator for input or output
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Added 9/23/2026, 2:48:59 PM
Active provider: DeepSeek · deepseek-flash
Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Patent Overview — US 6,737,682 B1
Title: "High voltage tolerant and low voltage triggering floating-well silicon controlled rectifier on silicon-on-insulator for input or output"
Patent number / application: US 6,737,682 B1; application US 10/209,150.
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd (original assignee; assignment lists inventor Ta-Lee Yu as assignor).
Inventor: Ta-Lee Yu.
Key dates: Filed 2002-07-30; priority date 2002-07-30 (stated as an assumption, not a legal conclusion); granted/publication date 2004-05-18; anticipated expiration 2022-07-30; legal status listed as "Expired - Lifetime" (status noted as an assumption, not a legal conclusion).
Purpose: The invention relates to silicon-on-insulator (SOI) devices and, more particularly, to a method to form a low voltage triggering silicon-controlled rectifier (SCR) SOI device having improved ESD performance. The excerpt states that ESD protection of SOI devices remains a significant challenge, and that a principal object is to provide an effective and manufacturable method of forming an LVT-SCR ESD device on a SOI substrate.
Plain-language scope: The disclosure describes SCR structures having an n-well and p-substrate with heavily doped n+ and p+ regions. First n+/p+ regions coupled together form an ANODE; second n+/p+ regions coupled together form a CATHODE, forming npn and pnp bipolar devices that conduct anode-to-cathode current during an ESD event. In a low voltage trigger SCR (LVT-SCR), an additional n+ region is added at the n-well/p-substrate interface, with a MOS gate between the second and third n+ regions, the gate coupled to the cathode, adding an NMOS device that reduces SCR triggering voltage. The excerpt notes integration difficulties in SOI, where shallow trench isolation is formed down to the buried insulator layer and is found to degrade SCR-ESD protection by reducing parasitic bipolar gains and lateral heat transfer. Cited background patents include U.S. Pat. Nos. 5,012,317; 5,530,612; 5,629,544; and 5,465,189.
Source: https://patents.google.com/patent/US6737682/en
What the excerpt does not establish: The full claim set, the complete detailed description, the method steps in full, and the omitted "floating-well" and high-voltage-tolerant aspects are not fully recoverable from the supplied excerpt; the excerpt contains only fragments of the description and no complete claims.
Generated 10/1/2026, 9:51:55 PM
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Litigation summary
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PTAB challenges
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Assignment history
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Prior art
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Obviousness
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Extensions
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Derivative works
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