Invalidity dossier
US 6711447
Modulating CPU frequency and voltage in a multi-core CPU architecture
Current assignee: UNM Rainforest Innovations
Added 9/23/2026, 9:35:51 PM
Active provider: DeepSeek · deepseek-flash
Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Patent Overview: US6711447B1
Title: Modulating CPU frequency and voltage in a multi-core CPU architecture
Patent number: US6711447B1
Application number: US10/349,537
Inventor: Ali Saeed
Original assignee: Intel Corporation
Current assignee (as listed): UNM Rainforest Innovations
Priority/filing date: 2003-01-22
Publication (grant) date: 2004-03-23
Legal status (as listed): Expired – Lifetime; anticipated expiration 2023-01-22
Purpose: The patent addresses saving power in dual-processor and multi-processor ("multi-core") systems, particularly battery-powered computers such as laptops and notebooks, by modulating CPU core frequency and voltage according to the level of multi-threadedness of the workload.
Plain-language scope (from the supplied excerpt):
- A workload threshold level is defined; the operating system (OS) determines a workload created by an application, where the workload may be defined by the level of multi-threadedness (e.g., percentage of multi-threaded (MT) vs. single-threaded (ST) threads, optionally tracked with one or more counters) (FIG. 1).
- If the measured workload is less than the threshold, a first CPU core is deactivated, or its voltage and/or frequency is reduced to a predetermined value; frequency/voltage modulation may be applied to more than one or all cores, and a core may later be deactivated once multi-threadedness drops below a threshold (operation 130).
- The workload may be determined by comparing the number of threads with the number of CPU cores: if threads exceed cores, all cores remain active; if cores exceed threads, a first CPU core is deactivated (operations 130/140).
- FIG. 2 describes an integrated circuit with a power control circuit coupled to first, second, and third CPU cores, receiving measured workload input from the OS; predetermined voltage/frequency values may be stored in microcode or BIOS.
- FIG. 3/4 describe user-defined power schemes: maximum frequency mode (all cores at maximum frequency), auto mode (cores modulated between predetermined frequencies using thresholds and a lookup table or logic circuit), and maximum battery mode (first core at minimum frequency, other cores deactivated; or all cores at minimum frequency).
- Classifications include G06F1/3203, G06F1/324, G06F1/329, G06F1/3296, and Y02D10/00.
What the excerpt does not establish: It does not provide complete claim language, the full specification, exact equations (the power equation is referenced but omitted), drawing details, or the complete text following the second threshold level discussion. Legal status and assignee listings are explicitly stated as assumptions/not legal conclusions. This overview is limited to the supplied source.
Source: https://patents.google.com/patent/[US6711447](/patent/US6711447)/en
Generated 10/1/2026, 9:34:10 PM
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PTAB challenges
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Assignment history
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Prior art
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Obviousness
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Extensions
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Derivative works
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