US 5949997

Patent Overview: US 5,949,997 A

Title: Method and apparatus for programming a microprocessor using an address decode circuit

Patent number: US 5,949,997 A (application US08/778,519)

Original assignee: NCR Corporation; current assignee listed as Teradata US Inc (listed assignees may be inaccurate; no legal analysis performed)

Key dates: Priority/filing date 1997-01-03; granted/publication date 1999-09-07; anticipated expiration 2017-01-03; status "Expired – Lifetime"

Inventor: Gregory James Smith

Source: https://patents.google.com/patent/US5949997/en

Purpose: To allow a microprocessor used as an embedded controller in high-reliability systems to have its programming updated in the field (flash programming) "in a fail-safe manner"—without adversely affecting the controlled system, and with the ability to return to a known state if the updated program fails.

Plain-language scope: The invention uses first and second memory banks (flash bank A, bank B), a reset circuit, and an address decode circuit. The first bank holds a current program; the second holds an updated program. The microprocessor boots from the current program, then reboots from the updated program. During that reboot it runs diagnostics (e.g., checksum, functional testing). A timer in the reset circuit runs from de-assertion of RESET; a CONFIRM signal from the microprocessor must arrive before timeout, or RESET is re-asserted. If the updated program is good, its bank becomes the default for future boots; if not, the microprocessor reboots using the current program and a FAIL signal is generated. Bank selection is determined by data in non-volatile memory within the reset circuit, which distinguishes a hardware/power-on reset from a SWITCH signal asserted by the microprocessor (default vs. non-default bank). The reset circuit can hold the rest of the system in reset via a SYSTEM RESET signal. In one embodiment the microprocessor is a Neuron™ microprocessor.

What the excerpt does not establish: It is a partial excerpt (text truncated at Block 56 onward), so the full specification, all claims, the complete FIG. 2/FIG. 3 state diagrams, and any claim language are not reproduced. It also does not establish claim scope, validity, enforceability, or prior art, and lists no cited references.