US 5920108

Patent Overview — US 5,920,108 A

Title: Late process method and apparatus for trench isolation

Patent number / application: US 5,920,108 A; Application US 08/745,104.

Inventors: Donald Frank Hemmenway and Lawrence George Pearce.

Assignee information (as listed): Original assignee Harris Corp; current assignee listed as Intersil Corp.

Dates (as listed): Prior art date 1995-06-05; filing date 1996-11-07; publication/grant date 1999-07-06; anticipated expiration 2015-06-05. Legal status listed as "Expired - Lifetime." (The source states legal status is an assumption, not a legal conclusion.)

Purpose. The invention "relates in general to a method and apparatus for trench isolation and, in particular, for providing trench isolation after completion of a final thick thermal oxidation step and a final deep diffusion step."

Plain-language scope. The patent addresses isolating conductive regions or layers in an integrated circuit. Isolation may be by junction isolation (juxtaposing differently doped regions) or dielectrically, using a dielectric region, layer, or structure between selected conductive regions and between selected transistors or other devices. In some devices the whole integrated circuit is insulated from bulk substrate material by a buried dielectric layer — silicon-on-insulator (SOI) devices. Certain SOI devices may be formed using a bonded wafer technique, in which a device wafer is bonded to a silicon dioxide surface layer of a handle wafer, giving a buried dielectric layer beneath the device wafer. One technique provides trenches around devices: trenches are patterned in the semiconductor substrate surface where devices are formed or are to be formed. Per the excerpt, prior-art trench isolation processes are performed early in integrated-circuit fabrication, before the major diffusions that form transistors and other devices and before completion of thick thermal oxide growth. The excerpt notes trench filling with dielectric material and polysilicon, oxide fill by thermal oxidation of the substrate forming the trench walls and floor, and oxide fill during local thermal oxidation. It also notes that most devices include a thermal oxidation step growing oxide thicker than 500 Angstroms, and that such thermal oxide is generally performed after substantial diffusions form larger device regions (e.g., collector regions in bipolar devices or well regions in MOS devices).

Source: https://patents.google.com/patent/US5920108/en

What the excerpt does not establish. The supplied text is marked as excerpted and omits material. It provides no claim language, so the actual claimed scope cannot be determined. It does not describe the specific "late process" sequence, apparatus structure, embodiments, or figures. It establishes nothing about prior art beyond general background statements, and nothing about validity, enforceability, litigation, or ownership transfers beyond the assignment entries listed.