Invalidity dossier

US 5241503

Dynamic random access memory with improved page-mode performance and method therefor having isolator between memory cells and sense amplifiers

Current assignee: NXP USA Inc

Added 9/21/2026, 1:07:52 PM

At a glanceNo PTAB challengesNo litigation on file

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Patent summary

Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.

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Patent Overview — US 5,241,503 A

Title: Dynamic random access memory with improved page-mode performance and method therefor having isolator between memory cells and sense amplifiers.

Patent number / application: US 5,241,503 A; application US 07/660,066.

Inventor: Lik T. Cheng.

Assignee: Motorola, Inc. (original assignee); Schaumburg, IL, a corp. of DE. Current assignee listed as NXP USA Inc., though the source notes listed assignees may be inaccurate and that no legal analysis was made.

Key dates: Filed 1991-02-25; priority date 1991-02-25 (also priority to JP 06996292A on 1992-02-21); published/granted 1993-08-31; anticipated expiration 2011-02-25; status "Expired – Lifetime." Classifications include G11C11/4091 (sense/sense-refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating).

Purpose / plain-language scope: The invention relates to DRAMs performing page-mode access cycles. In page mode, the DRAM avoids repeatedly row-decoding to reselect the same word line, since adjacent addresses are likely to be accessed, so maximizing page-mode performance is advantageous.

In plain terms, the DRAM comprises a memory cell activated by a word line that provides a differential voltage to true and complement bit lines; isolation means coupling those bit lines to true and complement sense lines and isolating them a predetermined time after an access cycle starts; a first sense amplifier coupled to the sense lines that latches their differential voltage; and a second sense amplifier coupled to the bit lines that latches a differential voltage in response to termination of the access cycle. A corresponding method includes providing bits to bit lines, latching in first sense amplifiers, isolating bit lines from sense lines, equalizing bit lines, coupling selected sense lines to input/output signal lines, recoupling at the end of page-mode cycles, and writing the first sense amplifier's logic state back to the bit lines.

Source: https://patents.google.com/patent/US5241503/en

What the excerpt does not establish: The excerpt reproduces front-matter, classifications, abstract-like "Definitions," and figure descriptions, but omits the detailed description, full claims, drawing contents, and any prior-art analysis. Descriptions of FIGS. 3–6 (second and third embodiments) are listed but not explained here.

Generated 10/1/2026, 10:00:54 PM

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PTAB challenges

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Assignment history

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Prior art

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Derivative works

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